EE 330 Lecture 15
Devices in Semiconductor Processes
• Diodes • Capacitors • MOSFETs Review from Last Lecture Basic Devices and Device Models
• Resistor • Diode • Capacitor • MOSFET • BJT Review from Last Lecture Analysis of Nonlinear Circuits (Circuits with one or more nonlinear devices) What analysis tools or methods can be used?
KCL ? Nodal Analysis
KVL? Mesh Analysis
Superposition? Two-Port Subcircuits
Voltage Divider ?
Current Divider?
Thevenin and Norton Equivalent Circuits? Review from Last Lecture Diode Models
Diode Characteristics Diode Characteristics 0.01
0.008 0.01 0.008 0.006 0.006 0.004 Id (amps) 0.004
0.002 Id (amps) 0.002 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Vd (volts) Vd (volts)
ID
VD
Which model should be used?
The simplest model that will give acceptable results in the analysis of a circuit Review from Last Lecture Diode Model Summary Piecewise Linear Models ID
Idd = 0if V < 0 V Vdd =0 if I > 0 D
Diode Characteristics
0.01
0.008 I = 0if V < 0.6V 0.006 0.004
dd Id (amps) 0.002
0 V =0.6V if I > 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 dd Vd (volts)
Diode Characteristics
0.01 Idd = 0if V < 0.6 0.008 0.006
0.004 Id (amps) Vdd =0.6+I dd R if I > 0 0.002 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Vd (volts) Diode Equation
Vd I = I eVt -1 dS Review from Last Lecture Diode Model Summary Piecewise Linear Models
Idd = 0if V < 0
Vdd =0 if I > 0
Idd = 0 if V < 0.6V
Vdd =0.6V if I > 0
Idd = 0if V < 0.6
Vdd =0.6+I dd R if I > 0
Diode Equation Vd I = Ie -1Vt dS When is the ideal model adequate?
When it doesn’t make much difference whether Vd=0V or Vd=0.6V When is the second piecewise-linear model adequate?
When it doesn’t make much difference whether Vd=0.6V or Vd=0.7V Review from Last Lecture Example: Determine IOUT for the following circuit 10K
IOUT
12V D1
Solution: Strategy:
1. Assume PWL model with VD=0.6V, RD=0 2. Guess state of diode (ON)
3. Analyze circuit with model
Select Select Model 4. Validate state of guess in step 2 (verify the “if” condition in model)
5. Assume PWL with VD=0.7V 6. Guess state of diode (ON)
7. Analyze circuit with model Model 8. Validate state of guess in step 6 (verify the “if” condition in model) Validate 9. Show difference between results using these two models is small 10. If difference is not small, must use a different model Review from Last Lecture Solution:
1. Assume PWL model with VD=0.6V, RD=0 2. Guess state of diode (ON) 10K
IOUT
12V 0.6V
3. Analyze circuit with model 12V-0.6V I=. 1 14mA OUT 10K 4. Validate state of guess in step 2
To validate state, must show ID>0
ID =I OUT =1.14mA>0 Review from Last Lecture Solution:
5. Assume PWL model with VD=0.7V, RD=0 6. Guess state of diode (ON) 10K
IOUT
12V 0.7V
7. Analyze circuit with model 12V-0.7V I=. 1 13mA OUT 10K 8. Validate state of guess in step 6
To validate state, must show ID>0
ID =I OUT =1.13mA>0 Review from Last Lecture Solution:
9. Show difference between results using these two models is small
are close I=1.14mAOUTOUT and I=1.13 mA
Thus, can conclude IOUT 1.14mA Example: Determine IOUT for the following circuit
10K
IOUT 0.8V D1
Solution: Strategy:
1. Assume PWL model with VD=0.6V, RD=0 2. Guess state of diode (ON) 3. Analyze circuit with model 4. Validate state of guess in step 2
5. Assume PWL with VD=0.7V 6. Guess state of diode (ON) 7. Analyze circuit with model 8. Validate state of guess in step 6 9. Show difference between results using these two models is small 10. If difference is not small, must use a different model Solution:
1. Assume PWL model with VD=0.6V, RD=0 2. Guess state of diode (ON) 10K
IOUT 0.8V 0.6V
3. Analyze circuit with model 0.8 - 0.6V I= 20 A OUT 10K 4. Validate state of guess in step 2
To validate state, must show ID>0
ID =I OUT =20 A>0 Solution:
5. Assume PWL model with VD=0.7V, RD=0 6. Guess state of diode (ON) 10K
IOUT 0.8V 0.7V
7. Analyze circuit with model 0.8V-0.7V I= 10 A OUT 10K 8. Validate state of guess in step 6
To validate state, must show ID>0
ID =I OUT =10 A>0 Solution:
9. Show difference between results using these two models is small
I=10AOUTOUT and I=20A are not close
10. If difference is not small, must use a different model
Thus must use diode equation to model the device
10K VD 0.8-VD IOUT I=OUT 10K 0.8V
VD 0.6V Vt I=IOUTS e
Solve simultaneously, assume Vt=25mV, IS=1fA
Solving these two equations by iteration, obtain VD= 0.6148V and IOUT=18.60μA Use of Piecewise Models for Nonlinear Devices when Analyzing Electronic Circuits
Process: 1. Guess state of the device 2. Analyze circuit 3. Verify State 4. Repeat steps 1 to 3 if verification fails 5. Verify model (if necessary) Observations: o Analysis generally simplified dramatically (particularly if piecewise model is linear) o Approach applicable to wide variety of nonlinear devices o Closed-form solutions give insight into performance of circuit o Usually much faster than solving the nonlinear circuit directly o Wrong guesses in the state of the device do not compromise solution (verification will fail) o Helps to guess right the first time o Detailed model is often not necessary with most nonlinear devices o For practical circuits, the simplified approach usually applies
Key Concept For Analyzing Circuits with Nonlinear Devices Use of Piecewise Models for Nonlinear Devices when Analyzing Electronic Circuits
Process: 1. Guess state of the device 2. Analyze circuit 3. Verify State 4. Repeat steps 1 to 3 if verification fails 5. Verify model (if necessary)
What about nonlinear circuits (using piecewise models) with time-varying inputs? 1K
Vout
D1 80Vsin500t 1K
Same process except state verification (step 3) may include a range where solution is valid Example: Determine V for V =80sin500t OUT IN 1K
Vout
VIN D1 80Vsin500t 1K
Guess D1 ON (will use ideal diode model) 1K
ID Vout
D1 VIN 1K
VOUT=VIN=80sin(500t)
VIN Valid for I >0 ID D 1K
Thus valid for VIN > 0 Example: Determine V for V =80sin500t OUT IN 1K
Vout
VIN D1 80Vsin500t 1K
Guess D1 OFF (will use ideal diode model) 1K
VD Vout D1 VIN 1K
VOUT=VIN/2=40sin(500t) V Valid for V <0 V IN D D 2
Thus valid for VIN < 0 Example: Determine VOUT for VIN=80sin500t
1K
Vout
VIN D1 80Vsin500t 1K
Thus overall solution
VIN
80V
t 80sin 5000tfor V IN VOUT 40sin 5000tforV IN
VOUT
80V
t
-40V Use of Piecewise Models for Nonlinear Devices when Analyzing Electronic Circuits
Process: 1. Guess state of the device 2. Analyze circuit 3. Verify State 4. Repeat steps 1 to 3 if verification fails 5. Verify model (if necessary)
What about circuits (using piecewise models) with multiple nonlinear devices?
1K 20V Vout
80V D1 D2
4K
Guess state for each device (multiple combinations possible) Example: Obtain VOUT
1K 20V Vout
80V D1 D2
4K 20V Example: Obtain V 1K OUT Vout
80V D1 D2
4K Guess D1 and D2 on 1K 20V Vout
80V ID1 I D1 D2 D2
4K VOUT=-20V
Valid for ID1>0 and ID2>0 20V I 50 mA D2 4K Since validates, solution is valid 80V I I 85 mA 0 DD121K Use of Piecewise Models for Nonlinear Devices when Analyzing Electronic Circuits
Single Nonlinear Device Process: 1. Guess state of the device 2. Analyze circuit 3. Verify State 4. Repeat steps 1 to 3 if verification fails 5. Verify model (if necessary)
Process: Multiple Nonlinear Devices
1. Guess state of each device (may be multiple combinations) 2. Analyze circuit 3. Verify State 4. Repeat steps 1 to 3 if verification fails 5. Verify models (if necessary)
Analytical solutions of circuits with multiple nonlinear devices are often impossible to obtain if detailed non-piecewise nonlinear models are used Types of Diodes
pn junction diodes
Id I Id Id d Id Id
Vd Vd Vd Vd Vd Vd
Pin or Light Emitting Signal or Zener Varactor or Rectifier Photo LED Varicap Laser Diode Metal-semiconductor junction diodes
Id Id Id
Vd Vd Vd
Schottky Barrier Basic Devices and Device Models
• Resistor • Diode • Capacitor • MOSFET • BJT Capacitors
• Types – Parallel Plate – Fringe – Junction Parallel Plate Capacitors
A2 C A1 cond1 cond2
d
insulator
A = area of intersection of A1 & A2 One (top) plate intentionally sized smaller to determine C A C d Parallel Plate Capacitors
Cap If C d unit area ε A C d
C CdA where ε C d d Fringe Capacitors C
d
ε A C d
A is the area where the two plates are parallel
Only a single layer is needed to make fringe capacitors Fringe Capacitors
C Capacitance Junction Capacitor
C V p D d d n depletion A region C d Note: d is voltage dependent -capacitance is voltage dependent CjoA φB C n for VFB -usually parasitic caps V 2 D -varicaps or varactor diodes exploit 1 φB voltage dep. of C
φB 0.6V n ; 0.5 Capacitance Junction Capacitor C
1.6 CAj0
1.4
1.2
1 0.8 VD 0.6
0.4
0.2 VD 0 -4 -3 -2 -1 0 1 C A φ C jo for V B n FB 2 VD 1 φB Voltage dependence is substantial
φB 0.6V n ; 0.5 Basic Devices and Device Models
• Resistor • Diode • Capacitor • MOSFET • BJT n-Channel MOSFET
Poly Gate oxide n-active p-sub n-Channel MOSFET Gate Drain Source L
W
LEFF
Bulk n-Channel MOSFET
Poly Gate oxide n-active p-sub depletion region (electrically induced) n-Channel MOSFET Operation and Model
VDS
VGS ID
VBS IG IB
Apply small VGS (VDS and VBS assumed to be small) ID=0 Depletion region electrically induced in channel I =0 Termed “cutoff” region of operation G IB=0 n-Channel MOSFET Operation and Model
VDS
VGS ID
VBS IG IB
Increase VGS (VDS and VBS assumed to be small) ID=0 Depletion region in channel becomes larger IG=0 IB=0 n-Channel MOSFET Operation and Model
VDS
VGS ID
VBS IG IB
ID=0 Model in Cutoff Region IG=0 IB=0 n-Channel MOSFET Operation and Model
VDS
Critical value of VGS ID V that creates GS VBS IG inversion layer IB termed threshold voltage, VT)
(VDS and VBS small)
Increase VGS more Inversion layer forms in channel IDRCH=VDS Inversion layer will support current flow from D to S IG=0 Channel behaves as thin-film resistor IB=0 Triode Region of Operation
ID I G V DS RCH VDS
VGS IB
VBS = 0
For VDS small L 1 RCH W VGS VT COX Behaves as a resistor between drain and source W I D μCOX VGS VT VDS L Model in Deep Triode Region I G I B 0 Triode Region of Operation
ID
IG RCH
VGS IB
VBS = 0
For VDS small L 1 RCH W VGS VT COX
Resistor is controlled by the voltage VGS Termed a “Voltage Controlled Resistor” (VCR) n-Channel MOSFET Operation and Model
VDS
VGS ID
VBS IG IB
(VDS and VBS small)
Increase VGS more Inversion layer in channel thickens IDRCH=VDS I =0 RCH will decrease G Termed “ohmic” or “triode” region of operation IB=0 n-Channel MOSFET Operation and Model
VDS
VGS ID
VBS IG IB
(VBS small)
Increase VDS Inversion layer thins near drain ID=? I =0 ID no longer linearly dependent upon VDS G Still termed “ohmic” or “triode” region of operation IB=0 Triode Region of Operation
ID
IG VDS
VGS IB
VBS = 0
For VDS larger W V L 1 I μC V V DS V R D OX GS T DS CH L 2 W VGS VT COX I G I B 0
Model in Triode Region n-Channel MOSFET Operation and Model
VDS
VGS ID
VBS IG IB
(VBS small)
Increase VDS even more Inversion layer disappears near drain ID=? Termed “saturation”region of operation IG=0 IB=0 Saturation first occurs when VDS=VGS-VT Saturation Region of Operation
ID
IG VDS
VGS IB
VBS = 0
W VDS I D μCOX VGS VT VDS L 2 or equivalently For VDS at onset of saturation W VGS VT ID μCOX VGS VT VGS VT L 2 or equivalently μC W I OX V V 2 D 2L GS T
I G I B 0 n-Channel MOSFET Operation and Model
VDS
VGS ID
VBS IG IB
(VBS small)
Increase VDS even more (beyond VGS-VT) Nothing much changes !! ID=? I =0 Termed “saturation”region of operation G IB=0 Saturation Region of Operation
ID
IG VDS
VGS IB
VBS = 0
For VDS in Saturation
μCOX W 2 ID VGS VT 2L Model in Saturation Region
IG I B 0 Model Summary ID IG VDS
VGS IB V = 0 BS 0V V Cutoff GS T W VDS IDOXGSμCV TDSGSDS VVV GS V T V V V T Triode L2 W 2 μCV VV V V V V Saturation OXGS2L TGS T DS GS T
IGB =I =0 This is a piecewise model (not piecewise linear though) Note: This is the third model we have introduced for the MOSFET L 1 (Deep triode special case of triode where VDS is small R CH ) W VGS VT COX Model Summary
ID 0 VGS VT W V IG DS ID μCOX VGS VT VDS VGS VT VDS VGS VT L 2 VDS VBS W 2 VGS IB μCOX VGS VT VGS VT VDS VGS VT 2L VBS = 0
I=I=0GB
Observations about this model (developed for VBS=0):
I=D1GSDS fV,V
I=G2GSDS fV,V
I=B3GSDS fV,V
This is a nonlinear model characterized by the functions f1, f2, and f3 where we have assumed that the port voltages VGS and VDS are the independent variables and the drain currents are the dependent variables End of Lecture 15