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Modeling for Electronic Packaging at Apl HARRY K. CHARLES, JR., and GUY V. CLATTERBAUGH MODELING FOR ELECTRONIC PACKAGING AT APL In the expanding world of modern electronics and integrated circuits, the need for high-density, high­ performance electronic circuit packaging is paramount. Key to any successful electronic packaging ac­ tivity is the ability to model and analyze electrical, mechanical, and thermal system behavior before actu­ al system design and fabrication. Details of an APL-developed set of computer-based models that allow the design and performance verification (electrical, mechanical, and thermal) of complex, high-speed (lOO-MHz clocks) digital circuits are described and applied to a high-performance radar signal process­ ing circuit. INTRODUCTION The use of complex, high-density, very large scale the basis of a priori application of this software and its application-specific integrated circuits in today's fast, high­ analytical results, rules for the electronic design of very performance systems requires careful attention to all large scale integrated (VLSI) circuits can be generated to aspects of electronic packaging. This includes the minimi­ ensure the successful performance of the system at im­ zation of electrical losses and signal interferences, the plementation. Examples of these design guidelines for elimination of excess thermal buildup, and the selection various chip technology families and common package of proper materials and structural configurations to en­ and board-level structures are presented. We also dis­ sure mechanical integrity over the specified operational cuss the specific application of these models and design environment. To design efficient packaging structures, one guidelines for a digital, radar signal processor using must evaluate (and effectively model) the performance re­ surface-mounted packaging technology on dense, large­ quirements, not only at the integrated circuit level, but area (> 130 cm2), multilayer, thick-film circuit boards. also at the board and system levels. Package, board, and system-level models are not widely available and, except SOFTWARE for a few open literature examples,I,2 exist only as pro­ The creation of software for electronic packaging en­ prietary software. In what follows we describe an integrat­ gineering is time-consuming and costly. It requires not ed set of computer -based models that allow the design only extensive programming but also a well-devised and and performance verification of complex, high-speed executed experimental validation plan. Thus, to mini­ (lOO-MHz) digital circuit packages and boards. The mize cost and have working code on-line as soon as pos­ models are based on several techniques, including finite sible, the packaging engineer must use all existing element and difference, boundary value, analytical or software tools (e.g., commercial, university, govern­ Green's functions, transmission line, and circuit compac­ ment). New software should only be written when the tion or density. 3 These techniques can be used to pre­ required software does not exist or is deemed too costly dict electrical (impedance, signal rise and fall times, to acquire or operate. APL created at least six software frequency response, crosstalk), mechanical Goint and packages (Table 1) to fill holes in the externally avail­ board-level stresses), and thermal (temperature profiles able software. These packages included code for the 3 and thermal resistance) performance. They can also be generation of circuit density (e.g., Rent's Rule ), skin used to develop design guidelines for package selection, resistance, crosstalk, electrical circuit parameters, rise board layout, and circuit partitioning. time, and thermal resistance. For thermal and ther­ In a previous article4 we described in detail the ther­ momechanical analysis, extensive use was made of com­ mal and thermomechanical modeling, analysis, and test­ puterized engineering workstations with commercially ing of electronic packaging systems. Thus, the focus here available finite-element pre- and post-processors (e.g., 5 will be the interdependence of the software and its use PATRAN ) in conjunction with finite-element analysis 6 to predict layout density and electronic performance software (e.g., NASTRAN ) , and finite-difference analy­ parameters. sis software (e.g., SINDA, NET 5) on a mainframe com­ Table 1 summarizes the model information, includ­ puter. Commercial circuit and transmission-line analysis ing the analytical technique, the origin of specific soft­ tools 7 were also used with internally generated soft­ ware codes, and the major parameters calculated. On ware, which was written in Fortran8 and designed to fohns Hopkins APL Technical Digest, Volume 11 , Numbers I and 2 (1990) 137 H. K. Charles, Jr. , and G. V. Clatterbaugh Table 1. Computer-aided design and analysis tools for package and board-level modeling. Parameters Model Software Analysis type calculated basis origin Thermal Steady-state and transient Finite-element method PATRAN/ NASTRAN temperature Thermal resistance Finite-difference method SINDA Thermal contours NET 5 (JHUIAPL) Analytical methods JHUlAPL (e.g., Green's function) Thermomechanical Displacements Finite-element method PATRAN/ NASTRAN Stress Strain Deformed shapes Thermallmechanicalloads Electrical simulation Crosstalk Analytical methods SPICE Pulse shape Signal delay Coupled transmission lines JHUlAPL Overshoot Electrical parametric Resistance, inductance, Finite-element method PATRAN/ NASTRAN capacitance, conductance, JHUlAPL impedance S parameters Skin resistance Analytical methods JHUlAPL Boundary-element method JHUlAPL Coupled transmission lines SPICE S-parameter analysis Touchstone Circuit density A verage wire length Analytical methods JHUlAPL Number of leads Circuit density (lines per inch) Rent's Rule exponent run on a personal computer. The software development fore committing to a particular substrate technology can activity also identified basic requirements for a complete­ prevent costly redesign. When deciding whether a par­ ly integrated software suite for VLSI packaging design. 9 ticular wiring technology is adequate to support the given Finite-element and finite-difference methods are es­ circuit design, one must pecially useful for engineering analysis and modeling of 1. Determine the maximum number of signal lines large, complex, board-level systems. The formulas of the (vertical or horizontal) crossing any respective line on 6 finite-element technique 10 and its associated software the circuit. can be used to model thermal, mechanical, and some 2. Determine the position of those lines where the electrical performance, simply by changing the finite­ crossings have the greatest density. element grid elements and perhaps the boundary condi­ 3. Determine the maximum lead length. tions. Chip carriers, pin grid arrays, and certain quad 4. Determine, on the basis of maximum lead length, flat packages are particularly amenable to this type of the design rules for parallel lead spacing as a function analysis because of their eightfold symmetry, as shown of the board technology, capacitive loading, and noise in Figure 1. parameters. 5. Reduce wiring density caused by electrical vias (in­ CIRCUIT DENSITY terconnections between layers of a multilevel substrate), Some limited success in determining the wiring densi­ thermal heat risers, etc. ty for logic circuits has been achieved 3,11 by using the The first three considerations depend primarily on the empirically derived Rent's Rule for device interconnec­ circuit design and the partitioning of the circuit into dis­ tions. This rule can be generalized for device packages crete integrated circuits. The last two depend strongly and circuit boards. Approximating the wiring density be- on the substrate wiring (board) technology itself and can 138 Johns Hopkins A PL Technical Digest, Volume 11 , Numbers 1 and 2 (1990) Modeling for Electronic Packaging at APL A Level 4 -'W'v-Q Lid PT ~ aCb = [~ N; (P;)l /b]b . (3) Chip In actual circuit application, the number of package in­ ~E---------f--L.-----L~- (die) puts and outputs and the number of active pins are known, but the exponent b is unknown. This Rent's ex­ ponent can be determined through the iterative relation Substrate lib ~ log [~ tv; (P;) lib] flog (PT). (4) B Level 4 This expression will converge as long as the total num­ ber of pins in the package P T is greater than the num­ ber of pins on anyone active device or discrete package. For example, we extend the model described by ~Sfer Schmidt 3 to estimate the maximum lead density for cir­ Level 3 cuit cards with package pins on all four sides as shown in Figure 2A. The chip set includes two 120-pin and six 20-pin devices. The total number of package pins is 176, -~Sfer yielding a Rent's Rule exponent of appproximately 0.5. Level2 ~heattrar To estimate the maximum number of signal lines cross­ ing any horizontal (or vertical) line drawn across the cir­ cuit card, we assume that the maximum number of traveling (crossing) lines will occur at the point where there are G/2 gates above and below (or left and right), that is, y(G/2) and x(G/2), respectively. Thus, the maximum number of leads crossing any horizontal line Ph is Since the number of leads leading to the package pins located beneath (or above) this line will not affect the wire congestion in the vertical direction, we must reduce the number of leads by a factor of 1 - (Pi-/ W), where W is the total number of substrate leads, and Pi- is the Figure 1. Finite-difference thermal modeling
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