DOCSLIB.ORG

The Relationship of Life Prediction for Quad Flat No-Lead Package

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
The Relationship of Life Prediction for Quad Flat No-Lead Package THE RELATIONSHIP OF LIFE PREDICTION FOR QUAD FLAT NO-LEAD PACKAGE (QFN) PACKAGES USING 4 POINT CYCLIC BEND TETSING AND THERMAL CYCLE TESTING by MONISHA MOHAN Presented to the Faculty of the Graduate School of The University of Texas at Arlington in Partial Fulfillment of the Requirements for the Degree of MASTER OF SCIENCE IN MECHANICAL ENGINEERING THE UNIVERSITY OF TEXAS AT ARLINGTON December 2015 Copyright © by Monisha Mohan 2015 All Rights Reserved ii Acknowledgements First and foremost, I would like to start by thanking the almighty for giving me this wonderful opportunity and the strength to tread this path. If there is one person that I would like to thank right next to almighty, it would be Dr. Dereje Agonafer for his continuous guidance and motivation from the time I joined his research group. He was very patient during the tough times and always provided me with plenty of resource and contacts whenever in need. Secondly, I would like to thank Mr. Alok Lohia and Mr. Andy Zhang from Texas Instruments for giving me a deeper insight and understanding about the experimental set-up and sample preparations. They made it very easy to contact them and always considered my input and ideas from the time this thesis began to grow up. I would sincerely like to mention my heartfelt thanks to Dr. Andrew Makeev and Dr.Ashfaq Adnan of the Mechanical and Aerospace Department at University of Texas at Arlington for permitting me to use their research and testing facilities in times of need even though they had a pretty tight schedule. My thanks to Mr. Kermit, who has played a major role in the fabrication process of the fixtures. He was patient with my corrections and always kept up his time schedule which made it easy to plan further. I would also like to thank Dr. Haji Sheik and Dr. Fahad Mirza for taking time out of their busy schedule to be a part of my Defense committee. Their interest and insightful comments during the review process gave few different perspectives to the objective of this research. A Special thanks to all the departmental staff especially Ms. Sally, Ms. Debi, Ms. Lanie, Ms. Flora who never failed to support in times of need. I also owe a lot of thanks to my EMNSPC team for the brainstorming sessions and discussions regarding research which helped me a lot during the initial stages of my research. I would like to acknowledge all my friends in UT Arlington for being my pillar of support. iii And above all I would like to thank my parents and my sister, for all the efforts and sacrifices they had to go through for my education. Without their immediate support at times of need it would have been impossible for me to focus completely on my studies. I am definitely indebt to my dog Kikki for all the sleepless nights where she never failed to give me company. Last but not least I would like to Mr.Nandakumar for inspiring me to take this journey and for being with me through every breakdowns, panic attacks and joy. November 12, 2015 iv Abstract THE RELATIONSHIP OF LIFE PREDICTION FOR QUAD FLAT NO-LEAD PACKAGE (QFN) PACKAGES USING 4 POINT CYCLIC BEND TETSING AND THERMAL CYCLE TESTING Monisha Mohan, MS The University of Texas at Arlington, 2015 Supervising Professor: Dereje Agonafer In the structural design of the Printed Circuit Boards, the stiffness modulus of the involved Fr4 and Cu layers play an important role. The 4 point bend test is one of the few test methods which is included in the JEDEC standard for the Monotonic Bend characterization for board level interconnects. The study in the past has shown that the damage mechanism of these two testing methods is similar. And also, correlation had been drawn by observation of failure mechanism through Scanning Electron Microscope (SEM). The purpose of this study is to create a methodology for co-relating 4 point bend test and thermal cycling and to understand the failure displacement on the solder joint. The printed circuit board assembly with the devices and solder joints aligned in the same direction was subjected to cyclic loading conditions and their behavior under the stress was analyzed. The test component contains daisy-chain connection to allow in-situ continuity monitoring of the device board level interconnects during the test. The daisy chain link in the outermost package is connected to a corresponding Printed Wiring Board(PWB) daisy chain link and electrically monitored. v The electrical resistance was monitored to realize the amount of resistance the board can withstand before the solder joint starts to fail. It has been noticed from the experiment that the increase in displacement leads to decrease in the fatigue life of the solder joint. Among the many environmental accelerated testing methodologies for assessing reliability of electronic systems, thermal cycling is the most commonly used for the characterization of devices as well as interconnections. Therefore, the assembly was subjected to thermal cycling simulations to estimate the number of cycles that would be needed for the accumulation of plastic work (energy density) in the critical solder joint. This will give us the methodology for correlating the 4 point bend test and thermal cycling. vi Table of Contents Acknowledgements ........................................................................................................ iii Abstract .......................................................................................................................... v List of Illustrations .......................................................................................................... ix List of Tables ................................................................................................................. xi Chapter 1 Introduction .................................................................................................... 1 Moore's Law .............................................................................................................. 2 Quad Flat No-Lead Package ...................................................................................... 3 Chapter 2 Reliability ....................................................................................................... 4 Chapter 3 Mechanical Fatigue Testing ........................................................................... 7 3 Point Bend Test Vs 4 Point Bend Test ....................................................................11 Chapter 4 Fatigue .........................................................................................................12 Fatigue as a Phenomenon in Materials .....................................................................12 Different Phases of Fatigue Life ................................................................................12 Crack initiation (Ni) ...............................................................................................14 Crack growth (Np) .................................................................................................14 Rapid fracture .......................................................................................................14 Fatigue Properties of Materials..............................................................................15 Chapter 5 Fixtures ........................................................................................................16 ASTM Test Standard ................................................................................................16 Designed 3 point and 4 point Test Fixtures................................................................17 Modified Fixture Head ...........................................................................................18 Fabricated Fixture .....................................................................................................19 Benchmarking Of Fabricated Fixtures .......................................................................20 Al Sample Specifications .......................................................................................21 vii Stress-Strain Relation ...........................................................................................22 Strain:- .............................................................................................................22 Stress:-.............................................................................................................22 Young's Modulus - Tensile Modulus, Modulus of Elasticity:- ..............................23 Chapter 6 Monotonic Bend Test Characterization ..........................................................25 QFN Test Sample .....................................................................................................26 Description:- .........................................................................................................26 Design Test Condition of Experiment ........................................................................27 Chapter 7 Strain Gauges ...............................................................................................29 Wheatstone Bridge ...................................................................................................31 Selected Strain Gauge ..............................................................................................32 Chapter 8 Event Detector ..............................................................................................33 Chapter 9 Experimental Test Setup ...............................................................................35
Load more

Recommended publications
  • The NASA Electronic Parts and Packaging (NEPP) '02 Workshop
    The NASA Electronic Parts and Packaging (NEPP) ‘02 Workshop 1 JPL 400-1015, 04/02 2 The NASA Electronic Parts and Packaging (NEPP) ‘02 Workshop April 30 - May 2, 2002 Hilton Nassau Bay & Marina Houston, TX Organized by: NEPP Information, Management and Dissemination Project 3 Message ________________________ from Chuck Barnes, NEPP Program Manager Welcome to the Annual NEPP Workshop on Electronic Parts, Packaging, and Radiation Characterization for Space Applications! We’re happy you are with us and look forward to talking with you. Let’s start off with a few words about the NASA Electronic Parts and Packaging (NEPP) Program. The NEPP objectives are to: Assess the reliability of newly available electronic parts and packaging technologies for usage on NASA projects through validations, assessments and characterizations and the development of test methods/tools. Expedite infusion paths for advanced (emerging) electronic parts and packaging technologies by evaluations of readiness for manufacturability and project usage considerations. Provide NASA Projects with technology selection, application, and validation guidelines for electronic parts and packaging hardware and processes. Retain and disseminate electronic parts and packaging assurance, reliability validations, tools and availability information to the NASA community. NEPP is organized around three technology concentrations and the Information Management and Dissemination effort. The technology concentrations are Electronic Parts (EPAR), Electronic Packaging (EPAC), and Electronic Radiation Characterization (ERC). The Information Management & Dissemination (IMD) project is responsible for making all NEPP products and deliverables accessible in a controlled manner and is coordinating this conference. The Electronic Parts Project is tied to satisfying the needs of NASA programs/projects for evaluation of newly available and advanced electronic parts and maximizing effectiveness and efficiency through leveraging by teaming and partnering with industry and other agencies.
    [Show full text]
  • Electronic Packaging Technologies 1
    ElectronicElectronic PackagingPackaging TechnologiesTechnologies Sergio Lopez-Buedo, Eduardo Boemo Universidad Autonoma de Madrid e-mail: [email protected] Electronic Packaging Technologies 1 Introduction to Electronic Packaging • Electronic Packaging is a multi-disciplinary subject – Mechanical, Electrical and Industrial Engineering, Chemistry, Physics and even Marketing • Electronic Packaging: Housing and interconnection of integrated circuits to form electronic systems • Electronic Packaging must provide – Circuit support and protection – Heat dissipation – Signal distribution – Manufacturability and serviceability – Power distribution Electronic Packaging Technologies 2 Issues in Electronic Packaging Electrical analysis and testing Mechanical analysis and Reliability, Chemistry, testing Physics, Mat. performance, cost, Eng.. market need/timing, manufacturability, yields…other Thermal Manufacturing analysis and and Industrial testing Eng.. Market analysis Electronic Packaging Technologies 3 Hierarchy of Interconnection Levels • Level 0 – Gate-to-gate interconnections on the silicon die • Level 1 – Connections from the chip to its package • Level 2 – PCB, from component to component or to external connector • Level 3 – Connections between PCBs, including backplanes or motherboards • Level 4 – Connections between subassemblies, for example a rack • Level 5 – Connections between physically separate systems, using for example an Ethernet LAN Electronic Packaging Technologies 4 Blue Gene: Example of Connection Hierarchy Electronic
    [Show full text]
  • 2005 Injection Molded & Micro Fabrication Electronic Packaging
    2005 INJECTION MOLDED & MICRO FABRICATION ELECTRONIC PACKAGING Dr. Ken Gilleo ET-Trends LLC Warwick, RI Dennis Jones Matrix, Inc. Providence, RI Abstract Thermoset epoxies, discovered nearly 80 years ago, remain the workhorse plastic for electronic packaging and printed circuit boards, but this could change with increasing technical, economic and regulatory demands. Modern halogen-free thermoplastics now boast superior properties and highly automated high-efficiency high-volume processes. Injection molding can readily produce intricate 3D structures suitable for electronic component packaging and 3D molded circuits. Although there is a well-established packaging infrastructure tied to thermoset epoxies there is a much larger world-wide manufacturing base that excels in thermoplastics. Nearly 16-billion pounds of thermoplastics are molded into various parts each year in the USA alone; 30 times higher than for epoxies. We believe that the time is right for adding thermoplastic packages, interconnects and circuitry to 21st century electronics. This paper will discuss concepts, novel designs, new processes and the advancements for injection molded packaging and highlight their impressive attributes; the lowest moisture uptake, the fastest processing and the highest stability in the world of polymers. While MEMS (Micro-Electro-Mechanical Systems) packaging will be a central theme, general component packaging will also be discussed including power packages and digital camera modules. The discussion will include the development of new BGA concepts that utilize automatic insert-molding of tiny metal balls to create the 1st (to chip) and 2nd level (to circuit board) interconnect system. Assembly topics will cover package sealing methods that include laser welding. New Multi-Chip Package (MCP) ideas based on insert-molded flexible circuitry will be described that could find use in stackable designs.
    [Show full text]
  • Book of Knowledge (BOK) for NASA Electronic Packaging Roadmap
    National Aeronautics and Space Administration Book of Knowledge (BOK) for NASA Electronic Packaging Roadmap Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Pasadena, California Jet Propulsion Laboratory California Institute of Technology Pasadena, California JPL Publication 15-4 2/15 National Aeronautics and Space Administration Book of Knowledge (BOK) for NASA Electronic Packaging Roadmap NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Pasadena, California NASA WBS: 724297.40.43 JPL Project Number: 104593 Task Number: 40.49.02.24 Jet Propulsion Laboratory 4800 Oak Grove Drive Pasadena, CA 91109 http://nepp.nasa.gov i This research was carried out at the Jet Propulsion Laboratory, California Institute of Technology, and was sponsored by the National Aeronautics and Space Administration Electronic Parts and Packaging (NEPP) Program. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, does not constitute or imply its endorsement by the United States Government or the Jet Propulsion Laboratory, California Institute of Technology. ©2015 California Institute of Technology. Government sponsorship acknowledged. Acknowledgments The author would like to acknowledge many people from industry and the Jet Propulsion Laboratory (JPL) who were critical to the progress of this activity. The author extends his appreciation to program managers of the National Aeronautics and Space Administration Electronics Parts and Packaging (NEPP) Program, including Michael Sampson, Ken LaBel, Dr. Charles Barnes, and Dr. Douglas Sheldon, for their continuous support and encouragement. ii OBJECTIVES AND PRODUCTS The objective of this document is to update the NASA roadmap on packaging technologies (initially released in 2007) and to present the current trends toward further reducing size and increasing functionality.
    [Show full text]
  • Quad Flat No-Lead (QFN) Evauation Test
    National Aeronautics and Space Administration Quad Flat No-Lead (QFN) Evaluation Testing Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Pasadena, California Jet Propulsion Laboratory California Institute of Technology Pasadena, California 6/17 National Aeronautics and Space Administration Quad Flat No-Lead (QFN) Evaluation Testing NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Success Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Pasadena, California NASA WBS: 724297.40.43 JPL Project Number: 104593 Task Number: 40.49.02.35 Jet Propulsion Laboratory 4800 Oak Grove Drive Pasadena, CA 91109 http://nepp.nasa.gov 6/17 This research was carried out at the Jet Propulsion Laboratory, California Institute of Technology, and was sponsored by the National Aeronautics and Space Administration Electronic Parts and Packaging (NEPP) Program. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, does not constitute or imply its endorsement by the United States Government or the Jet Propulsion Laboratory, California Institute of Technology. Copyright 2017. California Institute of Technology. Government sponsorship acknowledged. Acknowledgments The author would like to acknowledge many people from industry and the Jet Propulsion Laboratory (JPL) who were critical to the progress of this activity including the Rochester Institute of Technology (RIT). The author extends his appreciation to program managers of the National Aeronautics and Space
    [Show full text]
  • Advanced Electronic Packaging
    National Aeronautics and Space Administration Advanced Electronic Packaging The Assurance Challenges October 15, 2013 Michael J. Sampson [email protected] NASA Goddard Spaceflight Center (Greenbelt) Safety and Mission Assurance Directorate 301-614-6233 Co- Manager NEPP Program www.nasa.gov http://nepp.nasa.gov To be presented by Michael J. Sampson at the Trilateral NASA/Japan Aerospace Exploration Agency (JAXA)/European Space Agency (ESA) Safety and Mission Assurance Meeting, Washington, DC, October 15, 2013. 1 Acronyms, Abbreviations Etc. Appx Appendix BME Base Metal Electrodes CCGA Ceramic Column Grid Array CLGA Ceramic Land Grid Array DLA Defense Logistics Agency EEE Electrical, Electronic, and Electromechanical FOD Foreign Object FPGA Field Programmable Gate Array GSFC Goddard Space Flight Center HDI High Density Interconnect HST Hubble Space Telescope IC Integrated Circuit I/O Input Output LGA Land Grid Array MIL-PRF-38534 Performance Specification Hybrid Microcircuits General Specification For MIL-PRF-38535 Performance Specification Integrated Circuits (Microcircuits) Manufacturing General Specification For NASA National Aeronautics and Space Administration Pb Lead Metal PBGA Plastic Ball Grid Array RoHS Restriction of Hazardous Substances Sn/Pb Tin/Lead rev revision To be presented by Michael J. Sampson at the Trilateral NASA/Japan Aerospace Exploration Agency (JAXA)/European Space 2Agency (ESA) Safety and Mission Assurance Meeting, Washington, DC, October 15, 2013. 2 Outline • What is Electronic Packaging? • Why Package Electronic Parts? Passivation Wire Dielectric • Hermetic and Non-hermetic Etch Stop Layer Via Dielectric Capping Layer Copper Conductor with • Packaging Challenges Global Barrier/Nucleation Layer • Area Arrays • Advantages of Hermetic Intermediate Metal 1 Pre-Metal Dielectric • Increasing Complexity Tungsten Contact Plug • Class Y Concept and Update Metal 1 Pitch • Major Xilinx Package Change To be presented by Michael J.
    [Show full text]
  • Electronic Manufacturing and Packaging in Japan
    Japanese Technology Evaluation Center JTEC JTEC Panel Report on Electronic Manufacturing and Packaging in Japan Michael J. Kelly, Chair William R. Boulton John A. Kukowski Eugene S. Meieran Michael Pecht John W. Peeples Rao R. Tummala February 1995 International Technology Research Institute R.D. Shelton, Director Geoffrey M. Holdridge, WTEC Director Loyola College in Maryland 4501 North Charles Street Baltimore, Maryland 21210-2699 JTEC PANEL ON ELECTRONIC MANUFACTURING AND PACKAGING IN JAPAN Sponsored by the National Science Foundation, the Advanced Research Projects Agency, the National Aeronautics and Space Administration, and the Department of Commerce of the United States Government Dr. Michael J. Kelly (Chair) Dr. Michael Pecht Georgia Institute of Technology CALCE - EPRC Manufacturing Research Center University of Maryland 813 Ferst Drive College Park, MD 20742 Atlanta, GA 30332-0560 Dr. John Peeples Dr. William R. Boulton AT&T Center for International Commerce Global Information Solutions Auburn University West Columbia, SC Suite 109 Business Building 415 West Magnolia Ave. Dr. Rao Tummala Auburn, AL 36849 Georgia Institute of Technology Manufacturing Research Center Mr. John Kukowski 813 Ferst Drive Rochester Institute of Technology Atlanta, GA 30332-0560 Manufacturing Engineering Technology James E. Gleason Building - #9 78 Lom Memorial Drive Rochester, NY 14623-5604 Dr. Gene Meieran Intel Corporation 500 W. Chandler Boulevard MS - CH 2-23 Chandler, AZ 85226 INTERNATIONAL TECHNOLOGY RESEARCH INSTITUTE JTEC/WTEC PROGRAM The Japanese Technology Evaluation Center (JTEC) and its companion World Technology Evaluation Center (WTEC) at Loyola College provide assessments of foreign research and development in selected technologies under a cooperative agreement with the National Science Foundation (NSF).
    [Show full text]
  • System-In-Package: Electrical and Layout Perspectives Contents
    Foundations and TrendsR in Electronic Design Automation Vol. 4, No. 4 (2010) 223–306 c 2011 L. He, S. Elassaad, Y. Shi, Y. Hu and W. Yao DOI: 10.1561/1000000014 System-in-Package: Electrical and Layout Perspectives By Lei He, Shauki Elassaad, Yiyu Shi, Yu Hu and Wei Yao Contents 1 Introduction 225 2 IC Package Tutorial 227 2.1 Packaging Hierarchy 228 2.2 Die-to-package Interconnect 229 2.3 Package Substrate 234 2.4 Package-to-board Interconnect 238 2.5 Multi-chip Modules and SiP 244 3 System-in-Package Design Exploration 247 3.1 Introduction 247 3.2 Overview 249 3.3 On-chip Design Decisions 252 3.4 Package Design and Exploration 255 3.5 Voltage Domain Planning 257 3.6 Modeling and Analysis Decisions 257 3.7 SiP Design Problems 259 3.8 Parasitic Modeling for Design 262 3.9 In-package Power Integrity 270 3.10 Signal Integrity for Off-chip Signaling 278 4 Placement and Routing for SiP 285 4.1 I/O Placement 286 4.2 Redistribution Layer Routing 289 4.3 Escape Routing 289 4.4 Substrate Routing 296 References 300 Foundations and TrendsR in Electronic Design Automation Vol. 4, No. 4 (2010) 223–306 c 2011 L. He, S. Elassaad, Y. Shi, Y. Hu and W. Yao DOI: 10.1561/1000000014 System-in-Package: Electrical and Layout Perspectives Lei He1, Shauki Elassaad2, Yiyu Shi3, Yu Hu 4 and Wei Yao5 1 University of California, Los Angeles, CA 90095, USA, [email protected] 2 Stanford University, Stanford, CA 94305, USA, [email protected] 3 Missouri University of Science and Technology, Rolla, MO 65409, USA, [email protected] 4 University of Alberta, Edmonton, Alberta T6G 2R3, CANADA, [email protected] 5 University of California, Los Angeles, CA 90095, USA, [email protected] Abstract The unquenched thirst for higher levels of electronic systems integration and higher performance goals has produced a plethora of design and business challenges that are threatening the success enjoyed so far as modeled by Moore’s law.
    [Show full text]
  • 23. Packaging of Electronic Equipments (2)
    Part D: Packaging of Electronic Equipments 23. Packaging of Electronic Equipments (2) 23.1 Packaging and Interconnection Techniques Introduction Electronic packaging, which for many years was only an afterthought in the design and manufacture of electronic systems, increasingly is being recognized as the critical factor in both cost and performance. Current electronic systems employ a packaging technology which limits system performance because of a number of factors. As the circuit density on a chip goes up, the speed of functions it performs increases, Retention of signal integrity is another consideration, the power needed to run the chips generates significant amounts of heat which must necessarily be removed an important requirement. The selection of packaging and interconnection techniques is a very complex task for the designer and manufacturing engineer where the selection depends on a number of driving forces: mechanical, electrical, and thermal force. 23.1.1 Mechanical requirements The mechanical diving force strives to attain technology advancements to keep pace with the considerable improvements being made by the continued reduction (per function) in the integrated circuit package size. 23.1.2 Electrical requirements The electrical driving force is bringing new technology to the fabricator of conventional PWBs, with expressions such as controlled impedance, dielectric constant, insulation resistance. Improvements in dimensional stability and registration accuracy and use of new (more expensive) materials are the result of attempting to satisfy these needs. 23.1.3 Thermal requirements Thermal driving forces are threefold. In one case, it is giving credence to the use of materials and processes that can satisfy the higher assembly processing temperatures to which the PWBs must be subjected, that is, materials with a higher glass transition temperature (Tg).
    [Show full text]
  • Modern Electronic Packaging Technology
    M. G. BEVAN AND B. M. ROMENESKO Modern Electronic Packaging Technology Matthew G. Bevan and Bruce M. Romenesko A view of modern electronic packaging technology is presented along with its applications at APL. Although not always distinct, electronic packaging may be separated into three levels: component, board, and system. The manufacturing technologies and designs may vary at each level, but they all must provide electrical interconnection, thermal management, and mechanical and environmental protection. Each packaging level reflects a trade-off among many interrelated factors including design requirements, economics, and manufacturing infrastructure. (Keywords: Electronic components, Electronic packaging, Packaging design, Packaging levels.) INTRODUCTION Electronic packaging serves a fourfold function for Published information about electronic packaging the electronic circuit by providing it with power and technology is in abundance today. This article will signal interconnection, a path to dissipate heat, me- touch on the critical aspects of packaging technology chanical support, and a protected environment that and how they are applied at APL. For additional infor- prevents contamination, mechanical damage, and elec- mation, the reader may consult the selected bibliogra- tromagnetic interference. In some applications (e.g., phy at the end of this article, which lists several refereed biomedical), the packaging also protects the environ- journals, conference proceedings, and books that track ment from contamination by the electronics. progress in the packaging field. Proper packaging design requires identification of the critical issues involved such as performance needs, the application environment, manufacturing capabili- PACKAGING DESIGN ties, system heritage, testing, reliability, cost, and Over time, the trade-off in requirements has divided schedule. Electronic packaging technology uses a electronic packaging into three levels (Fig.
    [Show full text]
  • Sil-Pad® Design Guide
    Sil-Pad® Design Guide All statements, technical information and recommendations herein are based on tests we believe to be reliable, and THE FOLLOWING IS MADE IN LIEU OF ALL WARRANTIES, EXPRESSED OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MARKETABILITY AND FITNESS FOR PURPOSE. Sellers' and manufacturers' only obligation shall be to replace such quantity of the product proved to be defective. Before using, user shall determine the suitability of the product for its intended use, and the user assumes all risks and liability whatsoever in connection therewith. NEITHER SELLER NOR MANUFACTURER SHALL BE LIABLE EITHER IN TORT OF IN CONTRACT FOR ANY LOSS OR DAMAGE, DIRECT, INCIDENTAL, OR CONSEQUENTIAL, INCLUDING LOSS OF PROFITS OR REVENUE ARISING OUT OF THE USE OR THE INABILITY TO USE A PRODUCT. No statement, purchase order or recommendations by seller or purchaser not contained herein shall have any force or effect unless in an agreement signed by the officers of the seller and manufacturer. Registered Firm ISO 9001:1994 Certificate QSR-219 QS-9000 Third Edition Certificate Number, QSR-QS-017 2000-2001 Rev. 060100 © Copyright The Bergquist Company The Bergquist Company established the standard for contamination of elastomeric thermally conductive insulation material with the the solder. development of Sil-Pads® over 20 years ago. Sil-Pads were Cleaning baths developed as a clean, grease-free alternative to mica and grease. must also be Now, a complete family of materials is available to meet the avoided to prevent diverse and changing requirements of today’s design engineer. wash-out of the interface grease, MICA AND GREASE causing a dry joint Mica insulators have been in use for over 30 years and are still and contamination commonly used as an insulator.
    [Show full text]
  • 8 Evolutionary Advances in Conventional Packaging
    EVOLUTIONARY ADVANCES IN 8 CONVENTIONAL PACKAGING TECHNOLOGIES ÒEven if youÕre on the right track, youÕll get run over if you just sit there.Ó Ñ Will Rogers A very efficient design and manufacturing strategy has evolved in the past 50 years upon which virtually all electronic products are based. There may be significant differences in the outer form factors and other weighing factors of electronics-based products, but all such systems are based on integrated circuit chips, interconnected in a hierarchy of modules up to the complete system. Though there is often more than one ÒrightÓ way to design a system that results in a particular form factor and performance level, a well defined strategy has evolved over the years that stan- dardizes many aspects of the technology to reduce manufacturing costs and time to market. The various levels in this interconnection scheme are diagrammed in Figure 8-1. They consist of the following stages: level 1: from the die, typically into a single chip package level 1.5: from the die to a substrate that could be part of an MCM or wire bonded to a substrate as chip on board (COB) or flip chip attached to a substrate as direct chip attach (DCA) level 2: from the package to the substrate, or MCM to the substrate level 3: from the board to the backplane or from the daughter card to the motherboard level 4: from the backplane to other backplanes in a cabinet level 5: from one cabinet to others with cabling Every electrical system can be broken up into these interconnect levels with a distinct interface between each.
    [Show full text]