Reducing memory latency using MRAM

Suzanne Reed Lisa Trova Outline ● Problems with existing memory ○ DRAM ○ SRAM ● MRAM - Mechanics ● Read/Write Strategies ● Benefits/Cons of MRAM ● Alternatives to MRAM DRAM ● Created with a single transistor and capacitor ● Small area -> densely packed

http://fourier.eng.hmc.edu/e85_old/lectures/mem ory/node1.html DRAM ● Capacitor holds data, but needs to be refreshed as capacitance degrades (approx. 8 ms) ● High power consumption on refreshing SRAM ● Created with 6, 8, or 12 transistors ● Large area in layout ● Buffering on signals to prevent degradation due to large capacitances http://upload.wikimedia.org/wikipedia/commons/3 /31/SRAM_Cell_%286_Transistors%29.svg SRAM ● Used in cache ● Single clock cycle access, with addressing overhead ● Power hungry during switching ● Volatile Problems with DRAM/SRAM ● does not save state after power off ● Speed / layout size tradeoff ● Modern designs are limited by memory speed, size, and address computation Universal Memory

● Currently, DRAM, SRAM, and are combined to provide optimal performance ● The goal is to have one memory type that is cost-effective, high- speed, high-density, and low-

power. http://spectrum.ieee.org/img/unime m02r-1337284470946.jpg Origin of MRAM 1955 - Magnetic core memory 1988 - Albert Fert and Peter Gruenberg: discovered Giant Magnetoresistance 1995 - Motorola/Freescale started work on MRAM 2000 - IBM and Infineon started MRAM development together 2003 - first MRAM chip (128kbit) MRAM ● Data is stored as magnetic charges ● Reference layer holds fixed magnetic polarity ● Storage layer

changes polarity to http://www.crocus- store data. technology.com/images_crocus/tech-figure-mram.jpg Anatomy of MRAM

http://upload.wikimedia.org/wikipedia/commons/f/f9/MRAM-Cell-Simplified.svg MRAM Read Strategy ● Bit values are read by comparing the resistance value of a cell to midway reference value ● Resistance measurement is taken by measuring current

through the cell http://www.crocus- technology.com/pdf/MRAM_CR_v5 a.pdf MRAM Write Strategies ● Stoner-Wohlfarth theory of coherent rotation ● Toggling ● Current Line Cladding ● Thermally Assisted ● Precessional Switching ● Current Induced Magnetic Switching ● Spin Transfer Torque Toggle MRAM ● Freescale ● A pulse sequence to alternate data in memory ● Only bits at the intersection of two write lines will be written ● Uses Savtchenko switching for toggle Savtchenko Switching ● Savtchenko switching provides free synthetic antiferromagnet and a 45 degree orientation to prevent “half-disturb” problem ● Discs orient themselves to

be orthogonal Freescale Spin Transfer Torque MRAM

● Current is passed through the MTJ ● Current becomes polarized ● Conserves angular momentum by using http://www.eetimes.com/author.asp?section_id= 36&doc_id=1323466 first layer to exert spin on free layer Comparison http://www.crocus-technology.com/pdf/MRAM_CR_v5a.pdf

DRAM SRAM (6T) Flash MRAM

Cell Size [F2]8-1250-804-116-20

Non-Volatile No No Yes Yes

Endurance write/read ∞/∞∞/∞ 106/∞ >1015/∞

Non Destructive Read No Partial Yes Yes

Direct Overwrite Yes Yes No Yes

Signal Margin 100-200mV 100-200 mV Δ current 60-200% R

Write/Read 50 ns/50 ns 8 ns/8 ns 200 μs/60 ns 30 ns/30 ns

Erase 50 ns 8 ns 1-100 ms (blocks) 30 ns

Transistor Performance Low High High Voltage (HV) High

Scalability Limits Capacitor 6 Transistors Tunnel Oxide/HV Current Density Benefits of MRAM ● Very low power consumption ● Unlimited endurance ● Long data retention (non volatile) ● Compromise for speed and area Limitations of MRAM ● Slower than SRAM ● Lower cell density than DRAM ● No proven way to fabricate that is fast, reliable, and inexpensive D-MRAM ● Improved DRAM by adding MRAM e