Novel Methods for Improving Performance and Reliability of Flash
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Novel Methods for Improving Performance and Reliability of Flash- Based Solid State Storage System A dissertation submitted to the Graduate School of the University of Cincinnati in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the Department of Electrical Engineering and Computer Science of the College of Engineering and Applied Science by Jiayang Guo B.S. University of Cincinnati February 2018 Committee Chair: Yiming Hu, Ph.D. i Abstract Though SSDs outperform traditional magnetic-based storage devices, there is still potential for further performance improvements. In existing operating systems, the software I/O stack is designed considering the working mechanisms of the traditional magnetic-based hard drives. Therefore, it has been shown that the existing I/O software layer can cause additional operational overheads for flash-based SSDs [1]. To address this problem, we explore the influence factors which will lead to variation of the performance of SSD. Based on our observation, we proposed a SSD-based I/O scheduler called SBIOS that fully exploits the internal parallelism to improve the performance. It dispatches the read requests to different blocks to make full use of SSD internal parallelism. For write requests, it attempts to dispatch write requests to the same block to minimize the number of the block cross requests. Moreover, SBIOS introduces the conception of batch processing and separates read and write requests to avoid read-write interference. Besides, SSDs face reliability challenges due to the physical properties of flash memory. To fix the reliability issue of SSD, we propose a parallel and garbage collection aware I/O Scheduler called PGIS that identifies the hot data based on trace characteristics to exploit the channel level internal parallelism of flash-based storage systems. PGIS not only fully exploits abundant channel resource in the SSD, but also introduces a hot data identification mechanism to reduce the garbage collection overhead. By dispatching hot read data to the different channel, the channel level internal parallelism is fully exploited. ii By dispatching hot write data to the same physical block, the garbage collection overhead has been alleviated. The experiment results show that these methods significantly improve the reliability and performance of the SSD. In this research, the total number of erase operations is introduced to measure the reliability of SSD. Meanwhile, with the rapid development of non-violate technology, due to high read/write speed, high endurance, in-place updating of PCM, many hybrid storage structures which use PCM and SSD at the same storage level have been proposed to improve the performance of SSD. However, hybrid storage systems pose a new challenge to cache management algorithms. Existing DRAM-based cache management schemes are only optimized to reduce the miss rate. On a miss, the cache needs to access the PCM or the SSD. However there are major performance differences between the access times of the two different technologies. As a result, in such a hybrid system, a higher hit rate does not necessarily translate to higher performance. To address this issue, we propose a Miss Penalty Aware cache management scheme (short for MPA) which takes the asymmetry of cache miss penalty on PCM and SSD into consideration. Our MPA scheme not only uses the access locality to reduce the miss rate, but also assigns higher priorities to SSD requests located in the page cache to avoid the high miss penalty overhead. Our experimental results show that our MPA scheme can significantly improve the hybrid storage system performance by up to 30.5% compared with other cache management schemes. iii Copyright iv Acknowledgements The Ph.D. study is a long journey which is very interesting and challenging. In this journey, I meet challenge and fix it every day. Through this process, I know my strengths and weakness. Based on the knowledge of myself, I make myself better. Throughout this adventure, there are many brilliant, supportive people with me. First and foremost, I want to thank my advisor Dr. Yiming Hu. It has been an honor to be his Ph.D. student and to work with him. From my experience, he cares so much about his student that he always comes through for me when I need help. When I feel confused in my research, he always can provide insightful advices to improve my research in a few words. I cannot enumerate how many things I have learnt from him since there are too many. To me, the most important things I have learnt from him include doing work in a serious and responsible manner, hardworking, and paying attention to detail. I believe I will benefit from these skills in rest of my life. I really appreciate all his contributions of time, effort, ideas, trust, and funding to make my Ph.D. experience productive and stimulating. I would like to thank all the professors in my committee for their support and guidance. Dr. Jing Xiang gave me tremendous help especially in the first year of my Ph.D. life. He cares about me so much and always shares personal experience on research and life. I want to thank Dr. Wen-Ben Jone for his time, effort, and encouragement. I learnt from him the attitude of being more confident on my research and work. I also want to v thank Dr. Raj Bhatnagar for his guidance and rigor to research as well as pointing out my weakness for me to improve. Finally, I want to thank Dr. Carla Purdy for her approval and effort on my thesis in improving the quality of my work. I learnt from her the attitude of being serious and responsible for research and work. My gratefulness also goes to my friends and colleagues, Wentao Wang, Xining Li, Xiaobang Liu, Suyuan Chen, Minyang Wang, Vadambacheri Manian Karthik and his wife Balasubramanian Sanchayeni, and many others who have helped and supported me in any aspect. Lastly, I would like to thank my mother for her love, encouragement and funding. I am grateful to my mother because she has sacrificed a lot to raise me, educate me, and fund me in achieving my goal. My wholehearted gratitude is beyond any words. Thank you! vi Table of Contents 1. CHAPTER 1 INTRODUCTION ....................................................................................... 1 1.1 HDDS VS SSDS ................................................................................................................. 1 1.2 PROBLEM DESCRIPTION ..................................................................................................... 6 1.3 CONTRIBUTION .................................................................................................................. 8 1.4 ORGANIZATION OF DISSERTATION ................................................................................... 12 2. CHAPTER 2 BACKGROUND ........................................................................................ 15 2.1 NON-VIOLATE MEMORY .................................................................................................. 15 2.2 INTERNAL STRUCTURE OF SSD ....................................................................................... 18 2.3 FLASH TRANSLATION LAYER ........................................................................................... 21 2.4 HYBRID SSD STRUCTURE ................................................................................................ 26 3. CHAPTER 3 A SSD-BASED I/O SCHEDULER ........................................................... 28 3.1 ANALYZING THE CHARACTERISTICS OF SSD .................................................................. 28 3.2 BACKGROUND .................................................................................................................. 29 3.2.1 Request size ............................................................................................................................ 29 3.2.2 Read-write interference ........................................................................................................... 31 3.2.3 Internal parallelism ................................................................................................................. 33 3.3 SYSTEM DESIGN AND IMPLEMENTATION .......................................................................... 35 3.3.1 System overview .................................................................................................................. 35 3.3.2 Dispatching method ............................................................................................................. 36 3.3.3 Algorithm process ................................................................................................................ 38 3.4 EXPERIMENTAL EVALUATION AND ANALYSIS .................................................................. 39 3.4.1 Experiment setup .................................................................................................................. 40 3.4.2 Performance results and analysis ......................................................................................... 40 3.5 RELATED WORK ............................................................................................................... 42 3.6 SUMMARY ........................................................................................................................ 44 4. CHAPTER 4 A PARALLELISM AND GARBAGE COLLECTION AWARE I/O SCHEDULER .............................................................................................................................. 45 4.1 INTRODUCTION