Semiconductor Memory

Seong-Ook Jung 2011. 4. 1. [email protected]

VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering Contents

1. Current Memory 2. Future of NAND Flash 3. Universal memory 1. PRAM 2. STT-MRAM

2 YONSEI Univ. School of EEE Current Memory Memory Hierarchy

by Samsung electronics

4 YONSEI Univ. School of EEE Volatile vs. Non-Volatile

 Volatile memory  DRAM: fast speed, high density  Main memory  SRAM: very fast speed, very low density  Cache memory

 Non-volatile memory  NOR: very slow speed, low density  Program memory  Flash: very slow speed, very high density  Storage memory

5 YONSEI Univ. School of EEE Charge Based vs. Resistance Based

 Charge based device (Current memory)  DRAM  SRAM  Flash

 Resistance base memory (Future memory  Universal memory)  PRAM  RRAM

6 YONSEI Univ. School of EEE SRAM

Cache hierarchy in Lynnfield L1 ; 32KB (1core) L2 ; 256KB (1core) L3 ; 8MB (shared) Intel processor ; Lynnfield

Layout of Lynnfield SRAM cell 7 YONSEI Univ. School of EEE DRAM

SAMSUNG DDR3 4GB DRAM DRAM cell

8 YONSEI Univ. School of EEE DRAM Cell

9 YONSEI Univ. School of EEE Flash Memory

Samsung 256GB SSD

Flash memory cell

Samsung 32GB USB memory 10 YONSEI Univ. School of EEE Comparison

by Korea Institute of Science & Technology Information (KISTI) 11 YONSEI Univ. School of EEE DRAM and SRAM Trend

 Improve performance and capacity of DRAM and SRAM  Technology scaling  Design technique  Function and role of DRAM and SRAM are not changed.  SRAM ; cache memory in processor  DRAM ; main memory unit in system

NGM XDR DRAM diff?

DDR4

DDR3 DRDRAM Bandwidth DDR2

DDR

SDRAM 1996 2000 2004 2008 2012 Year by Intel Technology Journal 12 YONSEI Univ. School of EEE NAND Flash Trend

 Improve capacity and performance of NAND flash memory  Technology scaling  Design technique  Positioning of NAND flash have been changed.  Past ; digital camera, MP3, USB memory..  Recent ; solid state drive (SSD) for replacing HDD

100 SRAM

10 DRAM NOR

STT-MRAM Storage Class PRAM Memory (SCM)

Bit Cost 1 PRAM *IBM Universal Memory NAND 0.1 Endurance 3D ReRAM ~1015 ~105

101 102 103 104 105 106 Write Speed 13 YONSEI Univ. by Samsung electronics School of EEE Future of NAND Flash Invention of NAND Flash

by Toshiba, Flash handbook, 1992 by Toshiba, IEDM, 1988 15 YONSEI Univ. School of EEE Application I / Flash Cards

 Flash card is used for mobile devices with memory slot

Portable Video game PC Digital camera

Car navigation Cellular phone

16 YONSEI Univ. School of EEE Application II / Embedded Application

MP3 player

8GB Flash

E-Book

17 YONSEI Univ. School of EEE Application III / Contents Preloaded Media

18 YONSEI Univ. School of EEE Application IV / SSD

compatibility SATA interface

Samsung 256GB SSD

19 YONSEI Univ. School of EEE Evolution of NAND Flash Technology

by Samsung electronics 20 YONSEI Univ. School of EEE Limitation of NAND

 Beyond 30nm, Uncertainty of EUV Availability  Limit of Patterning  Beyond 20nm, Uncertainty of Conv. Linear Scaling  Limit of Device  Super-MLC (3-bit, 4-bit, etc.), High Speed I/F, 3D Technology 1000 G-line I-line KrF ArF DPT EUV ? 436nm 365nm 248nm 193nm 13.5 nm

100

Litho. Tool ?

Conventional Linear Scaling ? NAND Technology Node ( nm ) ) ( nm ( nm Node Node Technology Technology NAND NAND 1 1970 1980 1990 2000 2010 2020 2030 Year by Samsung electronics 21 YONSEI Univ. School of EEE High Speed Interface (DDR) NAND

 ONFI (Open NAND Flash Interface) 100MB/s 200MB/s : Intel, Micron, Hynix, etc.  Toggle-mode NAND : Samsung, Toshiba

10ns

20ns

22 by Micron-Intel, ISSSC, 2008 YONSEI Univ. School of EEE 3D NAND for Tera-bit Storage

 3D Vertical NAND  High Density Oriented, CTF, MLC

by Toshiba, IEDM, 2007 by Toshiba, VLSI, 2007

23 YONSEI Univ. School of EEE SDD vs. HDD

Low weight High performance Low power Low vibration

Low noise Low endurance

However, high cost per capacity, now by Samsung electronics 24 YONSEI Univ. School of EEE Component of SSD

 Performance = f(CPU, DRAM, Flash, Host Interface, HW automation)

by Samsung electronics 25 YONSEI Univ. School of EEE SSD / Solving the I/O Bottleneck

 Bridge Performance Gap between CPU and HDD

10GHz 2006: Quad Core 2006: Core Duo 2005: P4, 3.8GHz CPU 2003: P4, 3GHz DRAM 2010: Future, 1600 2000: P4, 1.5GHz 1GHz (12.8GB/s) HDD 2007: DDR3-1067 (8.5GB/s) 1999: PIII, 500MHz 2004: DDR2-533 (4.2GB/s) 1997: PII, 300MHz 2001: DDR266 100MHz (2.1GB/s) 1997: SDR, 133MHz 1993: P, 66MHz (1GB/s) SSD 1989: 486, 25MHz 1994: SDR, 66MHz (528MB/s)

Speed/Throughputs 1985: 386, 16MHz 10MHz 1993: EDO, 33MHz 2008: SATA6G (132MB/s) (100/600 MB/s) 2002: ATA6 1982: 286, 6MHz (30/100 MB/s) 2005: SATA3G (50/300 MB/s) (52MB/s) 1996: ATA2 1998: ATA4 1985: FP, 13MHz (10/33 MB/s) 2003: SATA1.5G (40/150 MB/s) (5/16 MB/s) 2000: ATA5 (20/66 MB/s) 1980 1985 1990 1995 2000 2005 2010

Year by Samsung electronics 26 YONSEI Univ. School of EEE SSD / Solving the Power Bottleneck

 HDD: Higher RPM = Higher Power + Generates more Heat  SSD: Less Power /No Heat saves lifetime Energy Costs…

Watts used in Operation Mode Watts used in Idle Mode

HDD RPM HDD RPM

by Samsung electronics 27 YONSEI Univ. School of EEE Wear-leveling for Optimization

4000 With wear-level W ithout wear-lev el 3500

3000 2500 Wear-leveling P/E 2000 Cycling by FTL (Flash Controller) 1500

1000

500

0 1 77 153 229 305 381 457 533 609 685 761 837 913 989 SSD Physical Block Address

Dynamic Wear-leveling Static Wear-leveling

MP3, USB, DSC etc. SSD 28 by Samsung electronics YONSEI Univ. School of EEE Sector Size for Optimization

 Existing OS is for HDD!  OS should be optimized for SSD!!!

29 YONSEI Univ. by K. Takeuchi, ISSCC Forum, 2008 School of EEE Self-monitoring, Analysis and Reporting Technology

 SMART (Self-Monitoring, Analysis and Reporting Technology)

YONSEI Univ. 30 by K. Takeuchi, ISSCC Forum, 2008 School of EEE Future Memory (Universal Memory) Universal Memory

 Universal memory is desired for next-generation memory.  Nonvolatile memory  High speed 100  High density SRAM  High endurability 10 DRAM  Low power NOR

STT-MRAM Storage Class PRAM Memory (SCM)

 Some candidates Bit Cost 1 PRAM *IBM  PRAM UniversalUniversal MemoryMemory  STT-MRAM NAND 0.1  FeRAM Endurance 3D ReRAM  ReRAM ~1015 ~105  ……. 101 102 103 104 105 106 Write Speed by Samsung electronics 32 YONSEI Univ. School of EEE Power Dissipation of IT Equipments

 In 2025, Power dissipation will reach 5 times larger.

by T. Kawahara, IEEE ED/SSC Mini-Colloquium, 2009 33 YONSEI Univ. School of EEE Normally OFF, Instant ON

 Read operation ; sensing resistance of GST

 Voltage biased to GST must to limited under Vth to prevent disturb.  Current sensing scheme  Appling read voltage to cell converts from resistance to current  Load device converts from current to voltage  Sense amplifier converts from analog voltage value to digital output by T. Kawahara, IEEE ED/SSC Mini-Colloquium, 2009

Instant ON

Normally OFF

34 YONSEI Univ. School of EEE Change Memory Configuration

 Nonvolatile RAM enhances user’s convenience.  Instant ON. Quickly software changing.

by T. Kawahara, IEEE ED/SSC Mini-Colloquium, 2009

35 YONSEI Univ. School of EEE Nonvolatile (NV) RAM Application

 Innovation for low power system including hardware, software, and architecture

by T. Kawahara, IEEE ED/SSC Mini-Colloquium, 2009 36 YONSEI Univ. School of EEE Impact on Performance

 Power ON time is improved to 1/9.  Nonvolatility achieves low power also.

by T. Kawahara, IEEE ED/SSC Mini-Colloquium, 2009 37 YONSEI Univ. School of EEE Impact on Power

 High-end cellular phone with large memory with low standby power (1/10).

by T. Kawahara, IEEE ED/SSC Mini-Colloquium, 2009 38 YONSEI Univ. School of EEE Universal Memory I PRAM Structure of PRAM Cell

40 by Samsung electronics YONSEI Univ. School of EEE Write Operation of PRAM

 Reset pulse (strong & short) ; Amorphous state (~100kΩ)  Set pulse (weak & long) ; Crystalline state (kΩ)

by KIST, 대한전자공학회, 2005

41 YONSEI Univ. School of EEE Read Operation of PRAM

 Read operation ; sensing resistance of GST

by KIST, 대한전자공학회, 2005

42 YONSEI Univ. School of EEE Recent Technical Issues Reducing Required RESET Current

 Reducing BEC

Increasing heat by increasing current density

→ reducing IRESET

 Confined contact

Increasing heat by increasing current density

→ reducing IRESET

by Samsung Electronics, Sym. VLSI Tech., 2007 43 YONSEI Univ. School of EEE Recent Technical Issues Reducing Required RESET Current

 Impurity doping Increasing GST resistance → increasing heat

→ reducing IRESET Reset Current Regime

Reducing

IRESET

by Samsung Electronics, Sym. VLSI Tech., 2007 44 YONSEI Univ. School of EEE Recent Technical Issues Obtaining Larger RESET Current

 Enhancing current driving capability  Vertical BJT

YONSEI Univ. 45 by Samsung Electronics School of EEE History of PRAM

by T. Kawahara, ASP-DAC Non-volatile Memory, 2011 46 YONSEI Univ. School of EEE Future of PRAM

 When ?? 2011 ?  Samsung and Micron expect to possess technology to mass-produce 512Mb~1Gb PRAM.  Absence of alternative market is obstacle of commercialization of PRAM.  Samsung or Micron may launch PRAM in 2011.

 Target !! NOR Flash !!  Recently, improvement of NOR flash disturbs commercialization of PRAM.  Main product of NOR flash is 256, 512Mb and uses for embedded system.

 Future !!  SSD drive  System that don’t need booting

47 YONSEI Univ. School of EEE Universal Memory II STT-MRAM MTJ Device Structure

 MTJ • Two magnetic layer(Free and pinned layer) • Insulating layer(Tunnel barrier)

 RMTJ ; depends on the state of free layer

State Effective resistance

Parallel 0 Low (R0)

Anti-Parallel 1 High (R1=R0*(1+MR))

(MR ; magnetoresistance)

Reading operation Reading resistance of MTJ

Writing operation Switching free layer of MTJ

49 YONSEI Univ. School of EEE Write Operation of Conventional MRAM  Applied Magnetic Fields Hy(word line) Selected BL Selected Cell Write 0 Write 1

Half- select Hx(bit line)

Selected WL (a) < Applied magnetic field > Selected BL  State Change 70 Selected WL 60 1 50

20 (b) Resistance change (%) change Resistance 10 0 0 < Half selection issue > -200 -100 0 100 200 Applied magnetic field (Oe) T. M. Maffitt, et al., IBM J., 2007 < State change > 50 YONSEI Univ. School of EEE Write Operation of STT-MRAM

 Spin-polarized electron

N writing 1 S N S

(a) “0” Write (Parallelizing)

S N N writing 0 S (b) “1” Write (Anti-Parallelizing) (c) R-I Characteristics

< Parallelizing and Anti-Parallelizing Current> by T. Kawahara, et al., ISSCC, 2007 51 YONSEI Univ. School of EEE Conventional MRAM vs. STT-MRAM STT-MRAM has good potential in scalability due to Write current.

Conventional MRAM STT-MRAM by Samsung electronics 52 YONSEI Univ. School of EEE Recent Technical Issues Reducing Required Critical Current Perpendicular MTJ . TMR element with perpendicular magnetic anisotropy (P-TMR) . Lower critical current than I-TMR

Research MTJ size Critical Switching Conference Group (diameter) current time 49uA (AP-P) Toshiba IEDM2008 55nm 4ns 100uA (P-AP)

Critical current (IC) of P-ST is dependent on MTJ size. (opposite result compared with page 2) IC=49uA 53 by T. Kishi, et al., IEDM, 2008 YONSEI Univ. School of EEE Recent Technical Issues Obtaining Larger Write Current 2 Transistor – 1 MTJ (2T1MTJ) cell structure

To minimize the cell area, the isolation area between a cell and an adjacent cell is replaced by the adjacent cell’s transistor; the “off” state of the channel region of the adjacent cell can insulate electrically among memory cells.

Larger write current with same area

by R. Takemura, et al., Symposium on VLSI circuits, 2009

54 YONSEI Univ. School of EEE NEW Application using MTJ Spintronics Logic  Recently, nonvolatile logic using MTJ had been studied.  Highly expected for LSI advancement and innovation.

Full adder with nonvolatile input B • Dynamic logic type • Dynamic power can reduced to 23%

by Shoun Matsunage, et al., Applied Physics Express, 2008

Nonvolatile Flip-flop • Cross-coupled inverter latch type • Standby power can reduced to 0%

by Noboru Sakimura, et al., CICC, 2008 55 YONSEI Univ. School of EEE Power Reduction by STT-MRAM and Spintronics Logic

 Keep normally the equipment turned off.  Power consumption adjusted to one third.

Conventional structure

with STT-MRAM with STT-MRAM and Spintronics logic

by T. Kawahara, IEEE ED/SSC Mini-Colloquium, 2009 56 YONSEI Univ. School of EEE History of STT-MRAM

by T. Kawahara, ASP-DAC Non-volatile Memory, 2011 57 YONSEI Univ. School of EEE Conclusion

 The density and performance of flash memory have been improved by improvement of process and design technology.  Solid state drive (SSD) is remarkable as alternate storage device. As cost per capacity decreases, SDD will replace HDD, gradually.  Advantage of SSD  Low power  High performance  No noise & vibration  Low heat  Next generation memory had been studied for overcoming current memory. (PRAM, STT-MRAM, …)  Requirement for universal memory  Nonvolatile  Low power  High performance  High density

58 YONSEI Univ. School of EEE