Magnetic Random Access Memory (MRAM)
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Universal Memory
BRIEFING No.4 ICT UNIVERSAL MEMORY Memory is an integral part of information processing devices and is needed for short‐term stor‐ age such as when computer programs are being executed or text documents are processed. Currently, three main types of memory exist: SRAM offers very high speed at a high cost, DRAM is average in terms of speed and cost, and Flash memory is a low cost, low speed solution for applications that need to retain the data even when power is disconnected. A group of emerg‐ ing memory devices called universal memory aim to combine all these features in a single de‐ vice.1 Developments in universal memory devices may eventually lead to the introduction of novel October 2010 October memory architectures that offer increased performance, enable smaller mobile devices, and offer novel features in traditional products such as cars or domestic appliances. Nanotechnol‐ ogy is an integral part of emerging memory research as it is becoming increasingly difficult to enhance the performance of current devices by scaling the technology further. It is unlikely that a single technology will emerge as the universal memory technology; however, the develop‐ ments in this sector will enhance the energy efficiency and performance of memory devices. Currently, the Integrated Circuit (IC) market is dominated by US and Asia based companies. Uni‐ versal memory and nanotechnology based solutions could provide an opportunity for Europe to gain ground in the sector. Background volatility. Its disadvantage compared to SRAM and DRAM is speed. None of the existing memory technologies provide all of the required properties. -
Nanotechnology ? Nram (Nano Random Access
International Journal Of Engineering Research and Technology (IJERT) IFET-2014 Conference Proceedings INTERFACE ECE T14 INTRACT – INNOVATE - INSPIRE NANOTECHNOLOGY – NRAM (NANO RANDOM ACCESS MEMORY) RANJITHA. T, SANDHYA. R GOVERNMENT COLLEGE OF TECHNOLOGY, COIMBATORE 13. containing elements, nanotubes, are so small, NRAM technology will Abstract— NRAM (Nano Random Access Memory), is one of achieve very high memory densities: at least 10-100 times our current the important applications of nanotechnology. This paper has best. NRAM will operate electromechanically rather than just been prepared to cull out answers for the following crucial electrically, setting it apart from other memory technologies as a questions: nonvolatile form of memory, meaning data will be retained even What is NRAM? when the power is turned off. The creators of the technology claim it What is the need of it? has the advantages of all the best memory technologies with none of How can it be made possible? the disadvantages, setting it up to be the universal medium for What is the principle and technology involved in NRAM? memory in the future. What are the advantages and features of NRAM? The world is longing for all the things it can use within its TECHNOLOGY palm. As a result nanotechnology is taking its head in the world. Nantero's technology is based on a well-known effect in carbon Much of the electronic gadgets are reduced in size and increased nanotubes where crossed nanotubes on a flat surface can either be in efficiency by the nanotechnology. The memory storage devices touching or slightly separated in the vertical direction (normal to the are somewhat large in size due to the materials used for their substrate) due to Van der Waal's interactions. -
AXP Internal 2-Apr-20 1
2-Apr-20 AXP Internal 1 2-Apr-20 AXP Internal 2 2-Apr-20 AXP Internal 3 2-Apr-20 AXP Internal 4 2-Apr-20 AXP Internal 5 2-Apr-20 AXP Internal 6 Class 6 Subject: Computer Science Title of the Book: IT Planet Petabyte Chapter 2: Computer Memory GENERAL INSTRUCTIONS: • Exercises to be written in the book. • Assignment questions to be done in ruled sheets. • You Tube link is for the explanation of Primary and Secondary Memory. YouTube Link: ➢ https://youtu.be/aOgvgHiazQA INTRODUCTION: ➢ Computer can store a large amount of data safely in their memory for future use. ➢ A computer’s memory is measured either in Bits or Bytes. ➢ The memory of a computer is divided into two categories: Primary Memory, Secondary Memory. ➢ There are two types of Primary Memory: ROM and RAM. ➢ Cache Memory is used to store program and instructions that are frequently used. EXPLANATION: Computer Memory: Memory plays a very important role in a computer. It is the basic unit where data and instructions are stored temporarily. Memory usually consists of one or more chips on the mother board, or you can say it consists of electronic components that store instructions waiting to be executed by the processor, data needed by those instructions, and the results of processing the data. Memory Units: Computer memory is measured in bits and bytes. A bit is the smallest unit of information that a computer can process and store. A group of 4 bits is known as nibble, and a group of 8 bits is called byte. -
Nanotechnology Trends in Nonvolatile Memory Devices
IBM Research Nanotechnology Trends in Nonvolatile Memory Devices Gian-Luca Bona [email protected] IBM Research, Almaden Research Center © 2008 IBM Corporation IBM Research The Elusive Universal Memory © 2008 IBM Corporation IBM Research Incumbent Semiconductor Memories SRAM Cost NOR FLASH DRAM NAND FLASH Attributes for universal memories: –Highest performance –Lowest active and standby power –Unlimited Read/Write endurance –Non-Volatility –Compatible to existing technologies –Continuously scalable –Lowest cost per bit Performance © 2008 IBM Corporation IBM Research Incumbent Semiconductor Memories SRAM Cost NOR FLASH DRAM NAND FLASH m+1 SLm SLm-1 WLn-1 WLn WLn+1 A new class of universal storage device : – a fast solid-state, nonvolatile RAM – enables compact, robust storage systems with solid state reliability and significantly improved cost- performance Performance © 2008 IBM Corporation IBM Research Non-volatile, universal semiconductor memory SL m+1 SL m SL m-1 WL n-1 WL n WL n+1 Everyone is looking for a dense (cheap) crosspoint memory. It is relatively easy to identify materials that show bistable hysteretic behavior (easily distinguishable, stable on/off states). IBM © 2006 IBM Corporation IBM Research The Memory Landscape © 2008 IBM Corporation IBM Research IBM Research Histogram of Memory Papers Papers presented at Symposium on VLSI Technology and IEDM; Ref.: G. Burr et al., IBM Journal of R&D, Vol.52, No.4/5, July 2008 © 2008 IBM Corporation IBM Research IBM Research Emerging Memory Technologies Memory technology remains an -
Parallel Computer Architecture and Programming CMU / 清华 大学
Lecture 20: Addressing the Memory Wall Parallel Computer Architecture and Programming CMU / 清华⼤学, Summer 2017 CMU / 清华⼤学, Summer 2017 Today’s topic: moving data is costly! Data movement limits performance Data movement has high energy cost Many processors in a parallel computer means… ~ 0.9 pJ for a 32-bit foating-point math op * - higher overall rate of memory requests ~ 5 pJ for a local SRAM (on chip) data access - need for more memory bandwidth to avoid ~ 640 pJ to load 32 bits from LPDDR memory being bandwidth bound Core Core Memory bus Memory Core Core CPU * Source: [Han, ICLR 2016], 45 nm CMOS assumption CMU / 清华⼤学, Summer 2017 Well written programs exploit locality to avoid redundant data transfers between CPU and memory (Key idea: place frequently accessed data in caches/buffers near processor) Core L1 Core L1 L2 Memory Core L1 Core L1 ▪ Modern processors have high-bandwidth (and low latency) access to on-chip local storage - Computations featuring data access locality can reuse data in this storage ▪ Common software optimization technique: reorder computation so that cached data is accessed many times before it is evicted (“blocking”, “loop fusion”, etc.) ▪ Performance-aware programmers go to great effort to improve the cache locality of programs - What are good examples from this class? CMU / 清华⼤学, Summer 2017 Example 1: restructuring loops for locality Program 1 void add(int n, float* A, float* B, float* C) { for (int i=0; i<n; i++) Two loads, one store per math op C[i] = A[i] + B[i]; } (arithmetic intensity = 1/3) void mul(int -
Process Variation Aware DRAM (Dynamic Random Access Memory) Design Using Block-Based Adaptive Body Biasing Algorithm
CORE Metadata, citation and similar papers at core.ac.uk Provided by DigitalCommons@USU Utah State University DigitalCommons@USU All Graduate Theses and Dissertations Graduate Studies 12-2012 Process Variation Aware DRAM (Dynamic Random Access Memory) Design Using Block-Based Adaptive Body Biasing Algorithm Satyajit Desai Utah State University Follow this and additional works at: https://digitalcommons.usu.edu/etd Part of the Computer Engineering Commons Recommended Citation Desai, Satyajit, "Process Variation Aware DRAM (Dynamic Random Access Memory) Design Using Block- Based Adaptive Body Biasing Algorithm" (2012). All Graduate Theses and Dissertations. 1419. https://digitalcommons.usu.edu/etd/1419 This Thesis is brought to you for free and open access by the Graduate Studies at DigitalCommons@USU. It has been accepted for inclusion in All Graduate Theses and Dissertations by an authorized administrator of DigitalCommons@USU. For more information, please contact [email protected]. PROCESS VARIATION AWARE DRAM (DYNAMIC RANDOM ACCESS MEMORY) DESIGN USING BLOCK-BASED ADAPTIVE BODY BIASING ALGORITHM by Satyajit Desai A thesis submitted in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE in Computer Engineering Approved: Dr. Sanghamitra Roy Dr. Koushik Chakraborty Major Professor Committee Member Dr. Reyhan Bhaktur Dr. Mark R. McLellan Committee Member Vice President for Research and Dean of the School of Graduate Studies UTAH STATE UNIVERSITY Logan, Utah 2012 ii Copyright c Satyajit Desai 2012 All Rights Reserved iii Abstract Process Variation Aware DRAM (Dynamic Random Access Memory) Design Using Block-Based Adaptive Body Biasing Algorithm by Satyajit Desai, Master of Science Utah State University, 2012 Major Professor: Dr. -
Unit 5: Memory Organizations
Memory Organizations Unit 5: Memory Organizations Introduction This unit considers the organization of a computer's memory system. The characteristics of the most important storage technologies are described in detail. Basically memories are classified as main memory and secondary memory. Main memory with many different categories are described in Lesson 1. Lesson 2 focuses the secondary memory including the details of floppy disks and hard disks. Lesson 1: Main Memory 1.1 Learning Objectives On completion of this lesson you will be able to : • describe the memory organization • distinguish between ROM, RAM, PROM, EEPROM and • other primary memory elements. 1.2 Organization Computer systems combine binary digits to form groups called words. The size of the word varies from system to system. Table 5.1 illustrates the current word sizes most commonly used with the various computer systems. Two decades ago, IBM introduced their 8-bit PC. This was Memory Organization followed a few years later by the 16-bit PC AT microcomputer, and already it has been replaced with 32- and 64-bit systems. The machine with increased word size is generally faster because it can process more bits of information in the same time span. The current trend is in the direction of the larger word size. Microcomputer main memories are generally made up of many individual chips and perform different functions. The ROM, RAM, Several types of semi- PROM, and EEPROM memories are used in connection with the conductor memories. primary memory of a microcomputers. The main memory generally store computer words as multiple of bytes; each byte consisting of eight bits. -
DRAM and Storage-Class Memory (SCM) Overview
Page 1 of 7 DRAM and Storage-Class Memory (SCM) Overview Introduction/Motivation Looking forward, volatile and non-volatile memory will play a much greater role in future infrastructure solutions. Figure 1 illustrates a typical processor with its DDR DRAM memory modules (e.g. DIMMs) connected to it. Notice that the integrated memory controller within the processor supports the DDR DRAM bus protocol and only DDR DRAM devices, or those that operate like DDR DRAM, are supported. The tight coupling of computing resources (CPUs, GPUs, FPGAs, etc.) with memory resources pose challenges to memory’s expanding importance. These challenges include: Memory capacity requirements are increasing, driven by in-memory workloads, server virtualization, etc. Compute capacity of CPUs are increasing, requiring more memory controllers and channels per socket Fewer high speed DIMMs per channel require more memory controllers and channels to maintain capacity Design/support lifecycles for compute and memory resources are tightly coupled making each dependent on the other Memory capacity is dependent on the number of CPUs, yielding over-provisioned compute for many workloads Gen-Z is a new data access technology that can significantly enhance memory solutions built with existing or emerging memory technologies. The following sections are designed to unveil the features and capabilities of the Gen-Z architecture by first describing the foundational features and building on these to illustrate the next generation components and system solutions that are made possible by Gen-Z technology. Note: many components require byte-addressable memory (e.g. CPU, SoC, GPUs, FPGAs, gateways, etc.), but, in this document, the term “processor” will be used to generically describe these roles. -
Open Poremba-Dissertation.Pdf
The Pennsylvania State University The Graduate School ARCHITECTING BYTE-ADDRESSABLE NON-VOLATILE MEMORIES FOR MAIN MEMORY A Dissertation in Computer Science and Engineering by Matthew Poremba c 2015 Matthew Poremba Submitted in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy May 2015 The dissertation of Matthew Poremba was reviewed and approved∗ by the following: Yuan Xie Professor of Computer Science and Engineering Dissertation Co-Advisor, Co-Chair of Committee John Sampson Assistant Professor of Computer Science and Engineering Dissertation Co-Advisor, Co-Chair of Committee Mary Jane Irwin Professor of Computer Science and Engineering Robert E. Noll Professor Evan Pugh Professor Vijaykrishnan Narayanan Professor of Computer Science and Engineering Kennith Jenkins Professor of Electrical Engineering Lee Coraor Associate Professor of Computer Science and Engineering Director of Academic Affairs ∗Signatures are on file in the Graduate School. Abstract New breakthroughs in memory technology in recent years has lead to increased research efforts in so-called byte-addressable non-volatile memories (NVM). As a result, questions of how and where these types of NVMs can be used have been raised. Simultaneously, semiconductor scaling has lead to an increased number of CPU cores on a processor die as a way to utilize the area. This has increased the pressure on the memory system and causing growth in the amount of main memory that is available in a computer system. This growth has escalated the amount of power consumed by the system by the de facto DRAM type memory. Moreover, DRAM memories have run into physical limitations on scalability due to the nature of their operation. -
Hard Disk Drive Specifications Models: 2R015H1 & 2R010H1
Hard Disk Drive Specifications Models: 2R015H1 & 2R010H1 P/N:1525/rev. A This publication could include technical inaccuracies or typographical errors. Changes are periodically made to the information herein – which will be incorporated in revised editions of the publication. Maxtor may make changes or improvements in the product(s) described in this publication at any time and without notice. Copyright © 2001 Maxtor Corporation. All rights reserved. Maxtor®, MaxFax® and No Quibble Service® are registered trademarks of Maxtor Corporation. Other brands or products are trademarks or registered trademarks of their respective holders. Corporate Headquarters 510 Cottonwood Drive Milpitas, California 95035 Tel: 408-432-1700 Fax: 408-432-4510 Research and Development Center 2190 Miller Drive Longmont, Colorado 80501 Tel: 303-651-6000 Fax: 303-678-2165 Before You Begin Thank you for your interest in Maxtor hard drives. This manual provides technical information for OEM engineers and systems integrators regarding the installation and use of Maxtor hard drives. Drive repair should be performed only at an authorized repair center. For repair information, contact the Maxtor Customer Service Center at 800- 2MAXTOR or 408-922-2085. Before unpacking the hard drive, please review Sections 1 through 4. CAUTION Maxtor hard drives are precision products. Failure to follow these precautions and guidelines outlined here may lead to product failure, damage and invalidation of all warranties. 1 BEFORE unpacking or handling a drive, take all proper electro-static discharge (ESD) precautions, including personnel and equipment grounding. Stand-alone drives are sensitive to ESD damage. 2 BEFORE removing drives from their packing material, allow them to reach room temperature. -
Semiconductor Memory
Semiconductor Memory Seong-Ook Jung 2011. 4. 1. [email protected] VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering Contents 1. Current Memory 2. Future of NAND Flash 3. Universal memory 1. PRAM 2. STT-MRAM 2 YONSEI Univ. School of EEE Current Memory Memory Hierarchy by Samsung electronics 4 YONSEI Univ. School of EEE Volatile vs. Non-Volatile Volatile memory DRAM: fast speed, high density Main memory SRAM: very fast speed, very low density Cache memory Non-volatile memory NOR: very slow speed, low density Program memory Flash: very slow speed, very high density Storage memory 5 YONSEI Univ. School of EEE Charge Based vs. Resistance Based Charge based device (Current memory) DRAM SRAM Flash Resistance base memory (Future memory Universal memory) PRAM RRAM 6 YONSEI Univ. School of EEE SRAM Cache hierarchy in Lynnfield L1 ; 32KB (1core) L2 ; 256KB (1core) L3 ; 8MB (shared) Intel processor ; Lynnfield Layout of Lynnfield SRAM cell 7 YONSEI Univ. School of EEE DRAM SAMSUNG DDR3 4GB DRAM DRAM cell 8 YONSEI Univ. School of EEE DRAM Cell 9 YONSEI Univ. School of EEE Flash Memory Samsung 256GB SSD Flash memory cell Samsung 32GB USB memory 10 YONSEI Univ. School of EEE Comparison by Korea Institute of Science & Technology Information (KISTI) 11 YONSEI Univ. School of EEE DRAM and SRAM Trend Improve performance and capacity of DRAM and SRAM Technology scaling Design technique Function and role of DRAM and SRAM are not changed. SRAM ; cache memory in processor DRAM ; main memory unit in system NGM XDR DRAM diff? DDR4 DDR3 DRDRAM Bandwidth DDR2 DDR SDRAM 1996 2000 2004 2008 2012 Year by Intel Technology Journal 12 YONSEI Univ. -
James A. Bain the Oracle at Delphi Outline • Logistics of the Advising and Mentoring Process
JamesJames A.A. BainBain Courses:Courses: Professor Department of ECE 18-202: Mathematical Foundations of EE Data Storage Systems Center 18-416: information Storage Systems http://www.ece.cmu.edu/~jbain 18-517: Information Storage Systems Design Probe Information Storage Device Physics V Recording Information Storage Device Physics Ti/A Field STM Cr-SrZrO3 Tip Emission • Energy localization SrRuO3 • Storage materials SrTiO3 Magnetic • Hysteretic phenomena Medium • High frequency switching 6 4 2 Magnetic 2 3 Marks Heat Assisted Magnetic Recording 0 -2 4 ∆R MFM -4 Perovskites Voltage (V)Voltage (V) 1 -6 -8 -1.0 -0.5 0.0 0.5 1.0 Current (mA) [email protected] ECE Advising: Getting Your Questions Answered James A. Bain The Oracle at Delphi Outline • Logistics of the advising and mentoring process • Objectives of the advising and mentoring process • Advising summary • Data storage technology overview ... Logistics of Advising Process • Fall Sophomore Year – Take 18-200: Emerging Trends in ECE – Receive advisor assignment – Complete advising preparation worksheet – Meet with advisor (possibly more than once) – Select classes for Spring 05 • Spring Sophomore Year – Meet with advisor (possibly more than once) – Request/select a faculty mentor – Meet with faculty mentor – Select classes for Fall 06 • Junior and Senior Years – Meet with faculty mentor as desired – Select classes for each semester – Plan for post-graduation: internships, jobs, fellowships, grad schools, etc. ECE Undergraduate Advising Committee Undergraduate Program Staff Susan Farrington - [email protected] HH 1118, 8-6955 Director of Alumni and Student Relations Structures relationships with students during and after ECE, student organizations, profession societies, alumni events Janet Peters- [email protected] HH 1110, 8-3666 Assistant for Undergraduate Education Monitors student academic progress, handles procedural and policy information and information on Co-op, IMB, Bruce Krogh Double Majors and Minors, Career Center, Health Center, etc.