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Computer Architecture Compendium for INF2270

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Computer Architecture Compendium for INF2270 UNIVERSITY OF OSLO Department of Informatics Computer architecture Compendium for INF2270 Philipp Häfliger Dag Langmyhr Spring 2010 Contents Contents1 List of Figures5 List of Tables7 1 Introduction9 I Basics of computer architecture 11 2 Introduction to Digital Electronics 13 3 Binary Numbers 15 3.1 Unsigned Binary Numbers......................... 15 3.2 Signed Binary Numbers.......................... 15 3.2.1 Sign and Magnitude........................ 15 3.2.2 Two’s Complement........................ 16 3.3 Addition and Subtraction......................... 16 3.4 Multiplication and Division......................... 18 3.5 Extending an n-bit binary to n+k-bits................... 19 4 Boolean Algebra 21 4.1 Karnaugh maps............................... 24 4.1.1 Karnaugh maps with 5 and 6 bit variables........... 26 4.1.2 Karnaugh map simplification based on zeros.......... 27 5 Combinational Logic Circuits 29 5.1 Standard Combinational Circuit Blocks................. 30 5.1.1 Encoder............................... 31 5.1.2 Decoder.............................. 32 5.1.3 Multiplexer............................. 33 5.1.4 Demultiplexer........................... 35 5.1.5 Adders............................... 35 6 Sequential Logic Circuits 39 6.1 Flip-Flops.................................. 39 6.1.1 Asynchronous Latches...................... 39 6.1.2 Synchronous Flip-Flops...................... 42 6.2 Finite State Machines............................ 45 6.2.1 State Transition Graphs...................... 45 6.3 Registers................................... 48 6.4 Standard Sequential Logic Circuits.................... 48 6.4.1 Counters.............................. 48 6.4.2 Shift Registers........................... 50 Page 1 CONTENTS 7 Von Neumann Architecture 53 7.1 Data Path and Memory Bus........................ 55 7.2 Arithmetic and Logic Unit (ALU)..................... 55 7.3 Memory................................... 56 7.3.1 Static Random Access Memory (SRAM)............ 60 7.3.2 Dynamic Random Access Memory (DRAM).......... 60 7.4 Control Unit (CU)............................. 62 7.4.1 Register Transfer Language.................... 62 7.4.2 Execution of Instructions..................... 62 7.4.3 Microarchitecture......................... 65 7.4.4 Complex and reduced instruction sets (CISC/RISC)..... 66 7.5 Input/Output................................ 66 8 Optimizing Hardware Performance 69 8.1 Memory Hierarchy............................. 69 8.1.1 Cache................................ 69 8.1.2 Virtual Memory.......................... 74 8.2 Pipelining................................... 75 8.2.1 Pipelining Hazards......................... 78 8.2.2 Conclusion............................. 81 8.3 Superscalar CPU.............................. 81 8.3.1 Brief Historical Detour into Supercomputing......... 81 8.3.2 Superscalar Principle....................... 83 II Low-level programming 85 9 Introduction to low-level programming 87 10 Programming in C 89 10.1 Data..................................... 89 10.1.1 Integer data............................ 89 10.1.2 Texts................................ 89 10.1.3 Floating-point data......................... 90 10.2 Statements.................................. 90 10.3 Expressions................................. 90 11 Character encodings 93 11.1 ASCII..................................... 93 11.2 Latin-1.................................... 93 11.3 Latin-9.................................... 93 11.4 Unicode................................... 93 11.4.1 UTF-8................................ 93 12 Assembly programming 97 12.1 Assembler notation............................. 97 12.1.1 Instruction lines.......................... 97 12.1.2 Specification lines......................... 97 12.1.3 Comments............................. 98 12.1.4 Alternative notation........................ 98 12.2 The assembler................................ 98 12.2.1 Assembling under Linux..................... 98 Page 2 CONTENTS 12.2.2 Assembling under Windows................... 99 12.3 Registers................................... 99 12.4 Instruction set................................ 100 Index 105 Page 3 Page 4 List of Figures 1.1 Abstraction levels in a computer.....................9 2.1 CMOSFET schematic symbols....................... 14 4.1 Boolean operators, truth tables and logic gates............. 23 4.2 3D Karnaugh map............................. 26 5.1 Example combinational logic circuit................... 30 5.2 Encoder Symbol............................... 31 5.3 Implementation 3-bit encoder....................... 31 5.4 Decoder symbol.............................. 33 5.5 3-bit decoder implementation....................... 33 5.6 Multiplexer symbol............................. 34 5.8 Demultiplexer symbol........................... 35 5.9 3-bit demultiplexer implementation................... 35 5.10 Schematics/circuit diagram of a 1-bit half adder............. 36 5.11 Full adder schematics............................ 37 6.1 Gated D-latch/transparent latch..................... 40 6.3 Clock signal................................. 42 6.5 T-flip-flop symbol.............................. 43 6.6 D-flip-flop symbol............................. 44 6.7 State transition graph for traffic light................... 45 6.8 Moore/Mealy finite state machine..................... 46 6.9 Traffic light controller schematics..................... 47 6.10 Register Symbol............................... 48 6.11 State transition graph of a 3-bit counter................. 48 6.12 3-bit counter Karnaugh maps....................... 48 6.13 3-bit synchronous counter......................... 49 6.14 3-bit ripple counter............................. 50 6.15 Shift register................................. 51 7.1 Von Neumann architecture........................ 54 7.2 1-bit ALU schematics............................ 55 7.3 1 bit ALU symbol.............................. 56 7.4 n-bit ALU schematics example...................... 57 7.5 n-bit ALU symbol.............................. 57 7.6 Static random access memory principle................. 59 7.7 DRAM principle............................... 61 7.8 Hardwired and Microprogrammed CU.................. 65 7.9 Simple I/O block diagram......................... 67 7.10 I/O controller principle.......................... 67 8.1 Memory hierarchy............................. 70 8.2 Associative cache.............................. 71 Page 5 LIST OF FIGURES 8.3 Directly mapped cache........................... 71 8.4 Set associative cache............................ 72 8.5 Look-through architecture......................... 73 8.6 Look-aside architecture.......................... 74 8.7 The principle of virtual memory..................... 75 8.8 Virtual memory paging........................... 75 8.10 4-stage pipeline simplified block diagram................. 76 8.11 4-stage pipeline execution......................... 77 8.12 Data hazard illustration.......................... 79 8.13 Control hazard illustration......................... 80 8.14 Cray-1.................................... 82 8.15 Principle of superscalar execution.................... 83 12.1 The most important x86/x87 registers.................. 99 Page 6 List of Tables 4.1 Basic Boolean functions.......................... 22 4.2 Boolean function table of rules...................... 22 4.3 Exercise to verify deMorgan........................ 22 5.1 Truth table of a 3-bit encoder....................... 31 5.2 Complete truth table of a 3-bit priority encoder............ 32 5.3 3-bit decoder truth table......................... 32 5.5 3-bit demultiplexer truth table...................... 34 5.6 Truth table for a 1-bit half adder..................... 36 5.7 Full Adder truth table........................... 36 6.1 SR-latch characteristic table, full..................... 41 6.2 SR-latch characteristic table, abbreviated................ 41 6.3 JK-flip-flop characteristic table, full.................... 43 6.4 JK-flip-flop characteristic table, abbreviated............... 43 6.5 T-flip-flop characteristic table, full..................... 44 6.6 T-flip-flop characteristic table, abbreviated................ 44 6.7 D-flip-flop characteristic table, full.................... 45 6.8 D-flip-flop characteristic table, abbreviated............... 45 6.9 Traffic light controller characteristic table................ 47 6.10 State transition table of a 3-bit counter................. 49 6.11 Shift register state transition table.................... 51 7.1 1-bit ALU truth table............................ 56 7.2 RAM characteristic table.......................... 58 7.3 Comparison of SRAM and DRAM.................... 62 7.4 RTL grammar................................ 62 7.7 Pros and Cons of hardwired and microarchitecture CU........ 66 8.1 Memory hierarchy summary table.................... 70 10.1 Integer data types in C........................... 90 10.2 Floating-point data types in C....................... 90 10.3 The statements in C............................ 91 10.4 The expression operators in C...................... 92 11.1 The ISO 8859-1 (Latin-1) encoding.................... 94 11.2 The difference between Latin-1 and Latin-9............... 95 11.3 UTF-8 representation of Unicode characters.............. 95 12.1 The major differences between AT&T and Intel assembler notation. 98 12.2 A subset of the x86 instructions (part 1)................ 101 12.3 A subset of the x86 instructions (part 2)................ 102 12.4 A subset of the x87 floating-point instructions............. 103
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