Sequential Logic – Each Circuit Element Used at Most Once Sequential Circuits

Home , Combinational logic, Processor register, Sequential logic

Review of Combinational Circuits Combinational circuits.  Basic abstraction = switch.  In principle, can build TOY computer with a combinational circuit. – 255  16 = 4,080 inputs  24080 rows in truth table! – no simple pattern Sequential Logic – each circuit element used at most once Sequential circuits. Reuse circuit elements Introduction to Computer by storing bits in "memory." ALU Yung-Yu Chuang combinational

with slides by Sedgewick & Wayne (introcs.cs.princeton.edu), Nisan & Schocken Memory state (www.nand2tetris.org) and Harris & Harris (DDCA) 2

Combinational vs. Sequential Circuits Flip-Flop Combinational circuits. Flip-flop  Output determined solely by inputs.  A small and useful sequential circuit  Can draw with no loops.  Abstraction that remembers one bit  Ex: majority, adder, ALU.  Basis of important computer components for – register – memory Sequential circuits. – counter  Output determined by inputs and  There are several flavors previous outputs.  Ex: memory, program counter, CPU.

3 4 S-R flip flop Relay-based flip-flop RSQ 00 Ex. Simplest feedback loop.  Two relays A and B, both connected 01 to power, each blocked by the other. 10  State determined by whichever switches first. The state is latched. 11  Stable.

Q=S+RQ output1

input2 input1

output2

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SR Flip Flop Flip-Flop SR flip flop. Two cross-coupled NOR gates. Flip-flop.  A way to control the feedback loop. Q=R(S+Q)  Abstraction that "remembers" one bit. R S  Basic building block for memory and registers.

RSQ Q 00 01 10 11 Caveat. Need to deal with switching delay.

7 8 Truth Table and Timing Diagram Clock SR Flip Flop Truth Table Truth table. S(t) R(t) Q(t) Q(t+) Clock.  Values vary over time. 0 0 0 0  Fundamental abstraction: regular on-off pulse. 0 0 1  S(t), R(t), Q(t) denote value at time t. 1 – on: fetch phase 0 1 0 0 – off: execute phase 0 1 1 0  External analog device. 1 0 0 1  Synchronizes operations of different circuit 1 0 1 1 elements. 1 1 0  Requirement: clock cycle longer than max 1 1 1 switching time. Sample timing diagram for SR flip-flop.   cycle time

Q 1 0 on 1 R 0 Clock off 1 S 0 time

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How much does it Hert? Clocked S-R flip-flop Frequency is inverse of cycle time.  Expressed in hertz.  Frequency of 1 Hz means that there is 1 cycle per second. – 1 kilohertz (kHz) means 1000 cycles/sec. – 1 megahertz (MHz) means 1 million cycles/sec. – 1 gigahertz (GHz) means 1 billion cycles/sec. – 1 terahertz (THz) means 1 trillion cycles/sec.

Heinrich Rudolf Hertz (1857-1894)

11 12 Clocked D flip-flop Stand-Alone Register

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15 16 Multiplexer S 4-to-1 multiplexer

When s=0, return x; otherwise, X mux Z return y. Y Example: (Y  S)  (X S) Two-input multiplexer

x1 4MUX z x2

s0 s1

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4-to-1 multiplexer 8-to-1 Multiplexer 2N-to-1 multiplexer N  N select inputs, 2 data inputs, 1 output  Copies “selected” data input x0 2MUX bit to output x0 x1 x1 4MUX z 2MUX z x2 x 3 x2 2MUX x3 s0 s1

s0 s1

19 20 8-to-1 Multiplexer 4-Wide 2-to-1 Multiplexer 2N-to-1 multiplexer Goal: select from one of two 4-bit buses N  N select inputs, 2 data inputs, 1 output  Copies “selected” data input bit to output

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4-Wide 2-to-1 Multiplexer k-Wide n-to-1 Multiplexer Goal: select from one of two 4-bit buses Goal: select from one of n k-bit buses  Implemented by layering 4 2-to-1 multiplexer  Implemented by layering k n-to-1 multiplexer

23 24 Register file implementation Memory Overview Computers and TOY have several memory components.  Program counter.  Registers.  Main memory. Implementation. Use one flip-flop for each bit of memory. Access. Memory components have different access mechanisms. TOY has 16 bit words, 8 bit memory addresses, and 4 bit register names. Organization. Need mechanism to manipulate groups of related bits.

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Register Bit Register Bit Register bit. Extend a flip-flop to allow easy Register bit. Extend a flip-flop to allow easy access to values. access to values.

D W

DW DW

27 28 Memory Bit: Interface Memory Bit: Switch Level Implementation Memory bit. Extend a flip-flop to allow easy Memory bit. Extend a flip-flop to allow easy access to values. access to values.

[ TOY PC, IR ] [ TOY main memory ] [ TOY registers ] [ TOY PC, IR ] [ TOY main memory ] [ TOY registers ]

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Processor Register Processor Register Processor register. Processor register.  Stores k bits.  Stores k bits.  Register contents always available on output bus.  Register contents always available on output bus.  If enable write is asserted, k input bits get copied  If enable write is asserted, k input bits get copied into register. into register.

Ex 1. TOY program counter (PC) holds 8-bit address. Ex 1. TOY program counter (PC) holds 8-bit address. Ex 2. TOY instruction register (IR) holds 16-bit Ex 2. TOY instruction register (IR) holds 16-bit current instruction. current instruction.

31 32 Processor Register Memory Bank Processor register. Memory bank.  Stores k bits.  Bank of n registers; each stores k bits.  Register contents always available on output bus.  Read and write information to one of n registers.

  If enable write is asserted, k input bits get copied Address inputs specify which one. log2n address bits needed into register.  Addressed bits always appear on output.  If write enabled, k input bits are copied into Ex 1. TOY program counter (PC) holds 8-bit address. addressed register. (four 6-bit words) Ex 2. TOY instruction register (IR) holds 16-bit 6-bit input bus current instruction. Ex 1. TOY main memory.  256-by-16 memory bank. Ex 2. TOY registers.  16-by-16 memory bank.  Two output buses.

2-bit address

6-bit output bus

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Memory: Interface Memory: Component Level Implementation

(four 6-bit words)

35 36 Memory: Switch Level Implementation Summary

(four 6-bit words) Sequential circuits add "state" to digital hardware.  Flip-flop. [represents 1 bit]  TOY word. [16 flip-flops]  TOY registers. [16 words]  TOY main memory. [256 words] Modern technologies for registers and main memory are different.  Few registers, easily accessible, high cost per bit.  Huge main memories, less accessible, low cost per bit.  Drastic evolution of technology over time. Next. Build a complete TOY computer.

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Flip-flop The Clock

in DFF out tock tock tock tock out(t) = in(t-1) clock tick tick tick tick signal A fundamental state-keeping device cycle cycle cycle cycle For now, let us not worry about the DFF implementation Memory devices are made from numerous flip-flops, all regulated by the same master clock signal Notational convention:  In our jargon, a clock cycle = tick-phase (low), followed by a tock-phase (high)

 In real hardware, the clock is implemented by an oscillator sequential sequential in out in chip = chip out  In our hardware simulator, clock cycles can be simulated either (notation)

 Manually, by the user, or clock  “Automatically,” by a test script. signal 1-bit register (we call it “Bit”) Bit register (cont.) load Objective: build a storage unit that can: (a) Change its state to a given input Interface Implementation (b) Maintain its state over time (until changed) in Bit out load if load(t-1) then out(t)=in(t-1) else out(t)=out(t-1) load in MUX out in Bit out DFF

if load(t-1) then out(t)=in(t-1) in out in out DFF DFF else out(t)=out(t-1)

out(t) = in(t-1)

Basic building block out(t) = out(t-1) ? o Load bit out(t) = in(t-1) ? o Read logic Won’t work o Write logic

Multi-bit register Aside: Hardware Simulation Relevant topics from the HW simulator tutorial: load load Clocked chips: When a clocked chip is loaded into the simulator, the clock icon is enabled, allowing clock in Bit out in Bit Bit . . . Bit out control w w Built-in chips: if load(t-1) then out(t)=in(t-1) if load(t-1) then out(t)=in(t-1)  feature a standard HDL interface yet a Java else out(t)=out(t-1) else out(t)=out(t-1) implementation  Provide behavioral simulation services 1-bit register w-bit register  May feature GUI effects (at the simulator level only).

o Register’s width: a trivial parameter o Read logic o Write logic Random Access Memory (RAM) RAM interface

load

(0 to n-1) log 2 n bits

o Read logic o Write logic.

RAM anatomy Counter Needed: a storage device that can: RAM 64 (a) set its state to some base value (b) increment the state in every clock cycle

RAM8 (c) maintain its state (stop incrementing) over clock cycles (d) reset its state inc load reset . RAM 8 . 8 in PC (counter) out register w bits w bits . . RAM8 If reset(t-1) then out(t)=0 Register 8 register else if load(t-1) then out(t)=in(t-1) else if inc(t-1) then out(t)=out(t-1)+1 Bit Bit .. . Bit register . . . else out(t)=out(t-1)

Typical function: program counter Recursive ascent Implementation: register chip + some combinational logic. Recap: Sequential VS combinational logic Time matters tock tock tock tock Combinational chip Sequential chip clock tick tick tick tick (optional) time delay (optional) signal cycle cycle cycle cycle comb. comb. DFF comb. in out in out logic logic gate(s) logic  During a tick-tock cycle, the internal states of all the clocked chips are allowed to change, but their outputs are “latched”  At the beginning of the next cycle, the outputs of all the clocked chips in the architecture commit to the new values. out = some function of (in) out(t) = some function of (in(t-1), out(t-1))

Implications: a Reg1

 Challenge: propagation delays

sel out 

+ Solution: clock synchronization

b Reg2

 Cycle length and processing speed.

Perspective

All the memory units described in this lecture are standard

Typical memory hierarchy Access time Cost

 SRAM (“static”), typically used for the cache

 DRAM (“dynamic”), typically used for main memory

 Disk

(Elaborate caching / paging algorithms)

A Flip-flop can be built from Nand gates

But ... real memory units are highly optimized, using a great variety of storage technologies.