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SEQUENTIAL LOGIC  Combinational:  Output Depends Only on Current Inputs  Sequential:  Output Depend on Current Inputs Plus Past History  Includes Memory Elements

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SEQUENTIAL LOGIC  Combinational:  Output Depends Only on Current Inputs  Sequential:  Output Depend on Current Inputs Plus Past History  Includes Memory Elements 10/10/2019 COMBINATIONAL VS. SEQUENTIAL DIGITAL ELECTRONICS LOGIC SYSTEM DESIGN Combinational Circuit Sequential Circuit inputs Combinational outputs inputs Combinational outputs FALL 2019 Logic Logic PROF. IRIS BAHAR (TAUGHT BY JIWON CHOE) OCTOBER 9, 2019 State LECTURE 11: SEQUENTIAL LOGIC Combinational: Output depends only on current inputs Sequential: Output depend on current inputs plus past history Includes memory elements BISTABLE MEMORY STORAGE SEQUENTIAL CIRCUITS ELEMENT Fundamental building block of other state elements Two outputs, Q, Q Outputs depend on inputs and state variables No inputs I1 Q The state variables embody the past Q Q I2 I1 Storage elements hold the state variables A clock periodically advances the circuit I2 Q What does the circuit do? 1 10/10/2019 BISTABLE MEMORY ELEMENT REVISIT NOR & NAND GATES Controlling inputs for NAND and NOR gates 0 • Consider the two possible cases: I1 Q 1 – Q = 0: then Q’ = 1 and Q = 0 (consistent) X X 0 1 1 0 I2 Q 0 1 1 – Q = 1: then Q’ = 0 and Q = 1 (consistent) I1 Q 0 Implementing NOT with NAND/NOR using non-controlling 1 0 I2 Q inputs – Bistable circuit stores 1 bit of state in the X X X’ X’ state variable, Q (or Q’ ) 1 0 • But there are no inputs to control the state S-R (SET/RESET) LATCH S-R LATCH ANALYSIS 0 R N1 Q – S = 1, R = 0: then Q = 1 and Q = 0 . Consider the four possible cases: 1 N2 Q . S = 1, R = 0 S . S = 0, R = 1 R N1 Q 1 R . S = 0, R = 0 N1 Q . S = 1, R = 1 – S = 0, R = 1: then Q = 0 and Q = 1 N2 Q 0 N2 Q S S 2 10/10/2019 S-R LATCH ANALYSIS S-R LATCH ANALYSIS 0 R 1 N1 Q – S = 0, R = 0: then Q = Q – S = 1, R = 0: then Q = 1 and Q = 0 prev Q prev = 0 Q prev = 1 0 0 0 R 0 R 1 N2 Q N1 Q N1 Q S 1 0 N2 Q 0 N2 Q R S S N1 0 Q – S = 0, R = 1: then Q = 0 and Q = 1 1 R 0 N2 1 Q N1 Q S – S = 1, R = 1: then Q = 0 and Q = 0 1 N2 Q S S-R LATCH AS MEMORY ELEMENT S-R LATCH OPERATION Boolean expression for S-R latch: S R R’ S R’ QQnext 0 0 0 Q Q S Q’ Q’ = (S + Q)’ 0 1 0 0 0 1 0 1 Q 1 1 1 0 0 0 Q Qnext = (R + Q’)’ R = (R + (S+Q)’)’ When S=0, R=0, latch holds its previous state = (R’ (S+Q) When S=1, R=1, latch may become unstable = R’S + R’Q What happens on a 11 00 transition? 3 10/10/2019 S-R LATCH SYMBOL THE D LATCH • SR stands for Set/Reset Latch D latch: builds on the S-R latch, where S and R cannot be both 1 – Stores one bit of state (Q) Output “follows” input • Control what value is being stored with S, R inputs D latch captures input data (what to set) when certain –Set:Make the output 1 (S = 1, R = 0, Q = 1) condition holds (when to set) – Reset: Make the output 0 (S = 0, R = 1, Q = 0) SR Latch D Latch Symbol Operates in 2 modes: Symbol 1. Open (transparent): input flows through to output CLK RQ 2. Closed (opaque): output does not change • Must do something to avoid invalid state DQ S Q (when S = R = 1) Q D LATCH D LATCH R S Clock enabled: Q output follows D input Clk D Q Q’ 1 1 0 1 1 0 Clock disabled: Q output retains last state 1 0 1 0 0 1 0 X 0 0 Qprev Q’prev D R (reset) D Q R (reset) Q D Q Q’ Clk Q’ Clk S (set) Clk Q’ S (set) Circuit guarantees R=S=1 will never occur 4 10/10/2019 MULTI-BIT LATCH CLOCK D1 D Q Q1 Q’ Clock: An input to a sequential circuit that changes output Simultaneously latch Clk and state value at a predetermined rate multiple bits positive negative D2 D Q Q2 (rising) (falling) edge A Latch may refer to a Q’ edge 1-bit latch or multi-bit Clk tH tL latch D3 D Q Q3 Triggering edge: Transition of the clock (LH or HL) Q’ Clk that captures input data positive-edge or negative-edge D4 D Q Q4 Clock period (cycle time): time between successive transitions in the Q’ same direction (LH or HL) Clk Clk Clock frequency = 1/clock period D LATCH TIMING FLIP-FLOP D Q Flip-flop: Samples input on triggering edge of clock Rising edge positive edge-triggered flip-flop Q’ Clk Falling edge negative edge-triggered flip-flop D flip-flop: Two D latches back-to-back Clk D Q D Q’ Q Clk 5 10/10/2019 FLIP-FLOP MADE FROM D-LATCHES D FLIP-FLOP TIMING D D Q D Q Q D Q Q’ Q’ Clk Clk Q’ Clk Clk DClkQ Clk 00 Copies D to Q 11on the rising edge D X0Qprev of the clock Q X1Qprev REGISTER FLIP-FLOPS VS. LATCHES D1 D Q Q1 Register: a collection of Q’ Clk FFs operating off a common clock D2 D Q Q2 Q’ Clk Why use a flip flop when it just takes twice as much logic? A single D flip-flop is a When would you want to use a flip-flop instead of a latch? 1-bit register D3 D Q Q3 Q’ Clk D4 D Q Q4 Q’ Clk Clk 6.
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