DOCSLIB.ORG

Sequential Logic .Sel(F[0]), .Out(Addmux Out));

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Sequential Logic .Sel(F[0]), .Out(Addmux Out)); Use Explicit Port Declarations module mux32two (input [31:0] i0,i1, input sel, output [31:0] out); assign out = sel ? i1 : i0; endmodule mux32two adder_mux(.i0(b), .i1(32'd1), Sequential Logic .sel(f[0]), .out(addmux_out)); • Digital state: the D-Register mux32two adder_mux(b, 32'd1, f[0], addmux_out); • Timing constraints for D-Registers 2 • Specifying registers in Verilog • Blocking and nonblocking assignments Order of the ports matters! • Examples Reminder: Lab #2 due Thursday 6.111 Fall 2016 Lecture 4 1 6.111 Fall 2015 Verilog Summary Examples • Verilog – Hardware description language – not software program. parameter MSB = 7; // defines msb as a constant value 7 • A convention: lowercase for variables, UPPERCASE for parameter E = 25, F = 9; // defines two constant numbers parameters module blob #(parameter WIDTH = 64, // default width: 64 pixels parameter BYTE_SIZE = 8, HEIGHT = 64, // default height: 64 pixels BYTE_MASK = BYTE_SIZE - 1; COLOR = 3'b111) // default color: white (input [10:0] x,hcount, input [9:0] y,vcount, output reg [2:0] pixel); endmodule parameter [31:0] DEC_CONST = 1’b1; // value converted to 32 bits • wires wire a,b,z; // three 1-bit wires wire [31:0] memdata; // a 32-bit bus parameter NEWCONST = 3’h4; // implied range of [2:0] wire [7:0] b1,b2,b3,b4; // four 8-bit buses wire [WIDTH-1:0] input; // parameterized bus parameter NEWCONS = 4; // implied range of at least [31:0] 6.111 Fall 2016 Lecture 4 3 6.111 Fall 2016 Lecture 4 4 Something We Can’t Build (Yet) Digital State One model of what we’d like to build What if you were given the following design specification: Next State Memory When the button is pushed: 1) Turn on the light if Device Current it is off State Combinational button 2) Turn off the light if light LOAD it is on Logic The light should change state within a second Input Output of the button press What makes this circuit so different Plan: Build a Sequential Circuit with stored digital STATE – from those we’ve discussed before? • Memory stores CURRENT state, produced at output 1. “State” – i.e. the circuit has memory • Combinational Logic computes 2. The output was changed by a input • NEXT state (from input, current state) When Output depends on input and current state, circuit is “event” (pushing a button) rather • OUTPUT bit (from input, current state) called a Mealy machine. If than an input “value” Output depends only on the • State changes on LOAD control input current state, circuit is called a Moore machine. 6.111 Fall 2016 Lecture 4 5 6.111 Fall 2016 Lecture 4 6 Our next building block: the D register D-Register Timing - I The edge-triggered D register: on ≤tPD the rising edge of CLK, the value of ≥t D is saved in the register and then CD shortly afterwards appears on Q. Q CLK D D ≥t ≥t CLK tPD: maximum propagation delay, CLK Q SETUP HOLD tCD: minimum contamination delay, CLK Q Q tSETUP: setup time How long D must be stable before the rising edge of CLK tHOLD: hold time How long D must be stable after the rising edge of CLK 6.111 Fall 2016 Lecture 4 7 6.111 Fall 2016 Lecture 4 8 D-Register Internals – 74LS74 D-Register Timing - II ≤tPD DQ logic DQ reg1 reg2 ≥tCD Q CLK tCLK CLK tPD,reg1 D CLK tPD,logic ≥tSETUP ≥tHOLD tCD,reg1 CLK tSETUP = 20ns tPD-HL = 40ns The good news: you can tCD,logic ≥ tSETUP,reg2 choose tCLK so that this tHOLD = 5ns tPD-LH = 25ns constraint is satisfied! tPD,reg1 + tPD,logic + tSETUP,reg2 ≤ tCLK The bad news: you have to change t + t ≥ t your design if this constraint isn’t CD,reg1 CD,logic HOLD,reg2 met. 6.111 Fall 2016 Lecture 4 9 6.111 Fall 2016 Lecture 4 10 Single-clock Synchronous Circuits Clocks are Not Perfect: Clock Skew CLout We’ll use Registers in a highly constrained way to build digital systems: In Combinational Does that D Q D Q symbol Logic register? Single-clock Synchronous Discipline • No combinational cycles Wire delay clk2 • Single clock signal shared among clk1 all clocked devices (one clock domain) clk1 • Only care about value of combinational circuits just before clk2 rising edge of clock • Clock period greater than every δ>0 combinational delay tskew = tclk2 –tclk1 • Change saved state after noise- inducing logic transitions have stopped! 6.111 Fall 2016 Lecture 4 11 6.111 Fall 2016 Lecture 4 12 Positive and Negative Skew D-Register Timing With Skew In the real world the clock signal arrives T R1 R2 R3 CLK at different registers at different times. In Combinational Combinational TCLK DQ DQ DQ ••• 1 3 DQ logic DQ Logic Logic CLK1 The difference in arrival times (pos or reg1 reg2 CLK tCLK1 tCLK2 tCLK3 neg) is called the clock skew tskew. CLK2 2 4 delay delay tskew = tRn,clk2 –tRn,clk1 th CLK ±skew (a) Positive skew We can update our two timing constraints to reflect the worst-case skew Launching edge arrives before the receiving edge CLKreg1 Setup time: t = t tPD,reg1+tPD,logic Rn,clk Rn+1,clk tRn,clk1+tPD,reg1+tPD,logic +tSETUP,reg2 ≤ tRn+1,clk2 R1 R2 R3 T + t +t + t ≤ t + t In Combinational Combinational CLK PD,reg1 PD,logic SETUP,reg2 CLK skew DQ DQ DQ ••• Logic Logic TCLK tCD,reg1+tCD,logic 1 3 CLK1 tCLK1 tCLK2 tCLK3 Hold time: tRn,clk1+tCD,reg1+tCD,logic ≥ tRn,clk2+tHOLD,reg2 delay delay CLK CLK2 2 4 ≥ tSETUP,reg2 (b) Negative skew tCD,reg1+tCD,logic ≥ tHOLD,reg2+ tskew CLKreg2 Receiving edge arrives before the launching edge Thus clock skew increases the minimum ≥ tHOLD,reg2 cycle time of our design and makes it harder to meet register hold times. Adapted from J. Rabaey, A. Chandrakasan, B. Nikolic, CLKreg2 rising edge might fall “Digital Integrated Circuits: A Design Perspective” Copyright 2003 Prentice Hall/Pearson. anywhere in this region. Which skew is tougher to deal with (pos or neg)? 6.111 Fall 2016 Lecture 4 13 6.111 Fall 2016 Lecture 4 14 Delay Estimation : Simple RC Networks RC Equation VDD Vin 50% Vs = 5 V t V = 5 V Vin Vout s tpHL tpLH C V Switch is closed t<0 L out R 90% Switch opens t>0 50% V DD V DD V = V + V 10% t + s R C tf tr V dVc (b) High-to-low c Vs = iR R+ Vc iR = C R on (a) Low-to-high dt - dV review R RC c V vout Vs = dt c V V out t out vin C V V 1 e RC C t c s L C L V 51 e RC R c on tp = ln (2) = 0.69 RC 6.111 Fall 2016 Lecture 4 15 6.111 Fall 2016 Lecture 4 16 Clocks are Not Perfect: Clock Jitter Sequential Circuit Timing New tCD,R = 1ns State tPD,R = 3ns t = 2ns S,R Current Combinational tH,R = 2ns State Logic Clock tCD,L = ? t = 5ns InputPD,L Output Questions: tpd, tsu, thold • Constraints on tCD for the logic? > 1 ns • Minimum clock period? > 10 ns (tPD,R+tPD,L+ tSETUP,R) Typical crystal oscillator • Setup, Hold times for Inputs? tSETUP,Input = tPD,L +tSETUP,R tclk –2tjitter > tpd + tsu + tlogic 100mhz (10ns) Jitter: 1ps tHOLD,Input = tHOLD,R -tCD,L This is a simple Finite State Machine … more on next time! 6.111 Fall 2016 Lecture 4 17 6.111 Fall 2016 Lecture 4 18 The Sequential always Block Importance of the Sensitivity List Edge-triggered circuits are described using a sequential always • The use of posedge and negedge makes an always block block sequential (edge-triggered) • Unlike a combinational always block, the sensitivity list does Combinational Sequential determine behavior for synthesis! D-Register with synchronous clear D-Register with asynchronous clear module comb(input a, b, sel, module seq(input a, b, sel, clk, module dff_sync_clear( module dff_sync_clear( output reg out); output reg out); input d, clearb, clock, input d, clearb, clock, output reg q output reg q always @(*) begin always @(posedge clk) begin ); ); if (sel) out = b; if (sel) out <= b; always @(posedge clock) always @(negedge clearb or posedge clock) else out = a; else out <= a; begin begin end end if (!clearb) q <= 1'b0; if (!clearb) q <= 1'b0; endmodule endmodule else q <= d; else q <= d; end end endmodule endmodule always always block entered only at block entered immediately when each positive clock edge (active-low) clearb is asserted Note: The following is incorrect syntax: always @(clear or negedge clock) If one signal in the sensitivity list uses posedge/negedge, then all signals must. Assign any signal or variable from only one always block. Be wary of race conditions: always blocks with same trigger execute concurrently… 6.111 Fall 2016 Lecture 4 19 6.111 Fall 2016 Lecture 4 20 Blocking vs. Nonblocking Assignments Blocking vs. Nonblocking Assignments • Verilog supports two types of assignments within always blocks, • Guaranteed question on job interviews with Verilog questions. with subtly different behaviors. • Blocking assignment (=): evaluation and assignment are immediate • Blocking assignment (=): evaluation and assignment are immediate; always @(*) begin subsequent statements affected. x = a | b; // 1. evaluate a|b, assign result to x y = a ^ b ^ c; // 2. evaluate a^b^c, assign result to y z = b & ~c; // 3. evaluate b&(~c), assign result to z • Nonblocking assignment (<=): all assignments deferred to end of end simulation time step after all right-hand sides have been evaluated (even those in other active always blocks) Nonblocking assignment (<=): all assignments deferred to end of simulation time step after all right-hand sides have been evaluated (even those in other active always blocks) Sometimes, as above, both produce the same result.
Load more

Recommended publications
  • Lecture 7: Synchronous Sequential Logic
    Systems I: Computer Organization and Architecture Lecture 7: Synchronous Sequential Logic Synchronous Sequential Logic • The digital circuits that we have looked at so far are combinational, depending only on the inputs. In practice, most systems have many components that contain memory elements, which require sequential logic. • A sequential circuit contains both a combinational circuit and memory elements, whose output also serves as an input for the combinational circuit. • The binary data stored in the memory elements define the state of the sequential circuit and help determine the conditions for changing the state in the memory elements. Inputs Combinational Outputs circuit Memory elements Sequential Circuits: Synchronous and Asynchronous • There are two types of sequential circuits, classified by their signal’s timing: – Synchronous sequential circuits have behavior that is defined from knowledge of its signal at discrete instants of time. – The behavior of asynchronous sequential circuits depends on the order in which input signals change and are affected at any instant of time. Synchronous Sequential Circuits • Synchronous sequential circuits need to use signal that affect memory elements at discrete time instants. • Synchronization is achieved by a timing device called a master-clock generator which generates a periodic train of clock pulses. Basic Flip-Flop Circuit Using NOR Gates 1 R(reset) Q 0 Set state Clear state 1 Q’ 0 S(set) S R Q Q’ 1 0 1 0 0 0 1 0 (after S = 1, R = 0) 0 1 0 1 0 0 0 1 (after S = 0, R = 1) 1 1 0 0 Basic
    [Show full text]
  • Performance Evaluation of a Signal Processing Algorithm with General-Purpose Computing on a Graphics Processing Unit
    DEGREE PROJECT IN TECHNOLOGY, FIRST CYCLE, 15 CREDITS STOCKHOLM, SWEDEN 2019 Performance Evaluation of a Signal Processing Algorithm with General-Purpose Computing on a Graphics Processing Unit FILIP APPELGREN MÅNS EKELUND KTH ROYAL INSTITUTE OF TECHNOLOGY SCHOOL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Performance Evaluation of a Signal Processing Algorithm with General-Purpose Computing on a Graphics Processing Unit Filip Appelgren and M˚ansEkelund June 5, 2019 2 Abstract Graphics Processing Units (GPU) are increasingly being used for general-purpose programming, instead of their traditional graphical tasks. This is because of their raw computational power, which in some cases give them an advantage over the traditionally used Central Processing Unit (CPU). This thesis therefore sets out to identify the performance of a GPU in a correlation algorithm, and what parameters have the greatest effect on GPU performance. The method used for determining performance was quantitative, utilizing a clock library in C++ to measure performance of the algorithm as problem size increased. Initial problem size was set to 28 and increased exponentially to 221. The results show that smaller sample sizes perform better on the serial CPU implementation but that the parallel GPU implementations start outperforming the CPU between problem sizes of 29 and 210. It became apparent that GPU's benefit from larger problem sizes, mainly because of the memory overhead costs involved with allocating and transferring data. Further, the algorithm that is under evaluation is not suited for a parallelized implementation due to a high amount of branching. Logic can lead to warp divergence, which can drastically lower performance.
    [Show full text]
  • Lecture 34: Bonus Topics
    Lecture 34: Bonus topics Philipp Koehn, David Hovemeyer December 7, 2020 601.229 Computer Systems Fundamentals Outline I GPU programming I Virtualization and containers I Digital circuits I Compilers Code examples on web page: bonus.zip GPU programming 3D graphics Rendering 3D graphics requires significant computation: I Geometry: determine visible surfaces based on geometry of 3D shapes and position of camera I Rasterization: determine pixel colors based on surface, texture, lighting A GPU is a specialized processor for doing these computations fast GPU computation: use the GPU for general-purpose computation Streaming multiprocessor I Fetches instruction (I-Cache) I Has to apply it over a vector of data I Each vector element is processed in one thread (MT Issue) I Thread is handled by scalar processor (SP) I Special function units (SFU) Flynn’s taxonomy I SISD (single instruction, single data) I uni-processors (most CPUs until 1990s) I MIMD (multi instruction, multiple data) I all modern CPUs I multiple cores on a chip I each core runs instructions that operate on their own data I SIMD (single instruction, multiple data) I Streaming Multi-Processors (e.g., GPUs) I multiple cores on a chip I same instruction executed on different data GPU architecture GPU programming I If you have an application where I Data is regular (e.g., arrays) I Computation is regular (e.g., same computation is performed on many array elements) then doing the computation on the GPU is likely to be much faster than doing the computation on the CPU I Issues: I GPU
    [Show full text]
  • SEQUENTIAL LOGIC  Combinational:  Output Depends Only on Current Inputs  Sequential:  Output Depend on Current Inputs Plus Past History  Includes Memory Elements
    10/10/2019 COMBINATIONAL VS. SEQUENTIAL DIGITAL ELECTRONICS LOGIC SYSTEM DESIGN Combinational Circuit Sequential Circuit inputs Combinational outputs inputs Combinational outputs FALL 2019 Logic Logic PROF. IRIS BAHAR (TAUGHT BY JIWON CHOE) OCTOBER 9, 2019 State LECTURE 11: SEQUENTIAL LOGIC Combinational: Output depends only on current inputs Sequential: Output depend on current inputs plus past history Includes memory elements BISTABLE MEMORY STORAGE SEQUENTIAL CIRCUITS ELEMENT Fundamental building block of other state elements Two outputs, Q, Q Outputs depend on inputs and state variables No inputs I1 Q The state variables embody the past Q Q I2 I1 Storage elements hold the state variables A clock periodically advances the circuit I2 Q What does the circuit do? 1 10/10/2019 BISTABLE MEMORY ELEMENT REVISIT NOR & NAND GATES Controlling inputs for NAND and NOR gates 0 • Consider the two possible cases: I1 Q 1 – Q = 0: then Q’ = 1 and Q = 0 (consistent) X X 0 1 1 0 I2 Q 0 1 1 – Q = 1: then Q’ = 0 and Q = 1 (consistent) I1 Q 0 Implementing NOT with NAND/NOR using non-controlling 1 0 I2 Q inputs – Bistable circuit stores 1 bit of state in the X X X’ X’ state variable, Q (or Q’ ) 1 0 • But there are no inputs to control the state S-R (SET/RESET) LATCH S-R LATCH ANALYSIS 0 R N1 Q – S = 1, R = 0: then Q = 1 and Q = 0 . Consider the four possible cases: 1 N2 Q . S = 1, R = 0 S . S = 0, R = 1 R N1 Q 1 R .
    [Show full text]
  • CPE 323 Introduction to Embedded Computer Systems: Introduction
    CPE 323 Introduction to Embedded Computer Systems: Introduction Instructor: Dr Aleksandar Milenkovic CPE 323 Administration Syllabus textbook & other references grading policy important dates course outline Prerequisites Number representation Digital design: combinational and sequential logic Computer systems: organization Embedded Systems Laboratory Located in EB 106 EB 106 Policies Introduction sessions Lab instructor CPE 323: Introduction to Embedded Computer Systems 2 CPE 323 Administration LAB Session on-line LAB manuals and tutorials Access cards Accounts Lab Assistant: Zahra Atashi Lab sessions (select 4 from the following list) Monday 8:00 - 9:30 AM Wednesday 8:00 - 9:30 AM Wednesday 5:30 - 7:00 PM Friday 8:00 - 9:30 AM Friday 9:30 – 11:00 AM Sign-up sheet will be available in the laboratory CPE 323: Introduction to Embedded Computer Systems 3 Outline Computer Engineering: Past, Present, Future Embedded systems What are they? Where do we find them? Structure and Organization Software Architectures CPE 323: Introduction to Embedded Computer Systems 4 What Is Computer Engineering? The creative application of engineering principles and methods to the design and development of hardware and software systems Discipline that combines elements of both electrical engineering and computer science Computer engineers are electrical engineers that have additional training in the areas of software design and hardware-software integration CPE 323: Introduction to Embedded Computer Systems 5 What Do Computer Engineers Do? Computer engineers are involved in all aspects of computing Design of computing devices (both Hardware and Software) Where are computing devices? Embedded computer systems (low-end – high-end) In: cars, aircrafts, home appliances, missiles, medical devices,..
    [Show full text]
  • Single-Cycle
    18-447 Computer Architecture Lecture 5: Intro to Microarchitecture: Single-Cycle Prof. Onur Mutlu Carnegie Mellon University Spring 2015, 1/26/2015 Agenda for Today & Next Few Lectures Start Microarchitecture Single-cycle Microarchitectures Multi-cycle Microarchitectures Microprogrammed Microarchitectures Pipelining Issues in Pipelining: Control & Data Dependence Handling, State Maintenance and Recovery, … 2 Recap of Two Weeks and Last Lecture Computer Architecture Today and Basics (Lectures 1 & 2) Fundamental Concepts (Lecture 3) ISA basics and tradeoffs (Lectures 3 & 4) Last Lecture: ISA tradeoffs continued + MIPS ISA Instruction length Uniform vs. non-uniform decode Number of registers Addressing modes Aligned vs. unaligned access RISC vs. CISC properties MIPS ISA Overview 3 Assignment for You Not to be turned in As you learn the MIPS ISA, think about what tradeoffs the designers have made in terms of the ISA properties we talked about And, think about the pros and cons of design choices In comparison to ARM, Alpha In comparison to x86, VAX And, think about the potential mistakes Branch delay slot? Look Backward Load delay slot? No FP, no multiply, MIPS (initial) 4 Food for Thought for You How would you design a new ISA? Where would you place it? What design choices would you make in terms of ISA properties? What would be the first question you ask in this process? “What is my design point?” Look Forward & Up 5 Review: Other Example ISA-level Tradeoffs Condition codes vs. not VLIW vs. single instruction SIMD (single instruction multiple data) vs. SISD Precise vs. imprecise exceptions Virtual memory vs. not Unaligned access vs.
    [Show full text]
  • Object-Oriented Development for Reconfigurable Architectures
    Object-Oriented Development for Reconfigurable Architectures Von der Fakultät für Mathematik und Informatik der Technischen Universität Bergakademie Freiberg genehmigte DISSERTATION zur Erlangung des akademischen Grades Doktor Ingenieur Dr.-Ing., vorgelegt von Dipl.-Inf. (FH) Dominik Fröhlich geboren am 19. Februar 1974 Gutachter: Prof. Dr.-Ing. habil. Bernd Steinbach (Freiberg) Prof. Dr.-Ing. Thomas Beierlein (Mittweida) PD Dr.-Ing. habil. Michael Ryba (Osnabrück) Tag der Verleihung: 20. Juni 2007 To my parents. ABSTRACT Reconfigurable hardware architectures have been available now for several years. Yet the application devel- opment for such architectures is still a challenging and error-prone task, since the methods, languages, and tools being used for development are inappropriate to handle the complexity of the problem. This hampers the widespread utilization, despite of the numerous advantages offered by this type of architecture in terms of computational power, flexibility, and cost. This thesis introduces a novel approach that tackles the complexity challenge by raising the level of ab- straction to system-level and increasing the degree of automation. The approach is centered around the paradigms of object-orientation, platforms, and modeling. An application and all platforms being used for its design, implementation, and deployment are modeled with objects using UML and an action language. The application model is then transformed into an implementation, whereby the transformation is steered by the platform models. In this thesis solutions for the relevant problems behind this approach are discussed. It is shown how UML can be used for complete and precise modeling of applications and platforms. Application development is done at the system-level using a set of well-defined, orthogonal platform models.
    [Show full text]
  • Exploring Applications in CUDA Michael Kubacki Computer Science and Engineering, University of South Florida
    Exploring Applications in CUDA Michael Kubacki Computer Science and Engineering, University of South Florida [email protected] Abstract—Modern Graphics Processing Units (GPUs) are or massive parallelization on the GPU. Of course, after such capable of much more than supporting GUIs and generating 3D analysis, an efficient implementation is necessary. This paper graphics. These devices are highly parallel, highly multithreaded explores two applications based on the CUDA programming multiprocessors harnessing a large amount of floating-point model and a sequential application demonstrating the processing power for non-graphics problems. This project is necessary preparation for a parallel implementation. based on experiments in CUDA C. These examples seek to demonstrate the potential speedups offered by CUDA and the II. BACKGROUND ease of which a new programmer can take advantage of such performance gains. A. NVIDIA CUDA Programming Model NVIDIA’s CUDA (Compute Unified Device Architecture) Keywords— CUDA, GPGPU, Parallel Programming, GPU is a scalable parallel programming model and software platform for the GPU and other parallel processors that allow I. INTRODUCTION the programmer to bypass the graphics API and graphics Traditionally, software applications have been written in a interfaces of the GPU and simply program in C or C++. sequential fashion, easily understood by a programmer CUDA uses a SPMD (single-program, multiple data) style, stepping through the code. Software developers have largely programs are written for one thread that is instanced and relied on increasing clock frequencies and advances in executed by many threads in parallel on the multiple hardware to simply speed up execution of these programs. processors of the GPU [7].
    [Show full text]
  • Sequential Code Parallelization for Multi-Core Embedded Systems: a Survey of Models, Algorithms and Tools
    Instituto Tecnol´ogicode Costa Rica Electronics Engineering School Master's Program in Electronics Engineering Sequential Code Parallelization for Multi-core Embedded Systems: A Survey of Models, Algorithms and Tools Master's Thesis in fulfillment of the requirements for the degree of Master of Science in Electronics Engineering Major on Embedded Systems Submitted by Jorge Alberto Castro God´ınez December 15, 2014 I declare that this thesis document has been made entirely by my person, using and applying literature on the subject, and introducing my own knowledge and experimental results. In the cases I have used literature, I proceeded to indicate the sources by the respective references. Accordingly, I assume full responsibility for this thesis work and the content of this document. Jorge Alberto Castro God´ınez B¨uhl,Germany. December 15, 2014 C´ed.:1 1236 0930 Instituto Tecnol´ogicode Costa Rica Electronics Engineering School Master's Thesis Evaluation Committee Master's Thesis presented to the Evaluation Committee as a requirement to obtain the Master of Science degree from the Instituto Tecnol´ogicode Costa Rica. Evaluation Committee Members The members of the Evaluation Committee certify that this Master's Thesis has been approved and that fulfills the requirements set by the Electronics Engineering School. B¨uhl,Germany. December 15, 2014 Abstract In recent years the industry experienced a shift in the design and manufacture of pro- cessors. Multiple-core processors in one single chip started replacing the common used single-core processors. This design trend reached the develop of System-on-Chip, widely used in embedded systems, and turned them into powerful Multiprocessor System-on- Chip.
    [Show full text]
  • Sequential Logic – Each Circuit Element Used at Most Once Sequential Circuits
    Review of Combinational Circuits Combinational circuits. Basic abstraction = switch. In principle, can build TOY computer with a combinational circuit. – 255 16 = 4,080 inputs 24080 rows in truth table! – no simple pattern Sequential Logic – each circuit element used at most once Sequential circuits. Reuse circuit elements Introduction to Computer by storing bits in "memory." ALU Yung-Yu Chuang combinational with slides by Sedgewick & Wayne (introcs.cs.princeton.edu), Nisan & Schocken Memory state (www.nand2tetris.org) and Harris & Harris (DDCA) 2 Combinational vs. Sequential Circuits Flip-Flop Combinational circuits. Flip-flop Output determined solely by inputs. A small and useful sequential circuit Can draw with no loops. Abstraction that remembers one bit Ex: majority, adder, ALU. Basis of important computer components for – register – memory Sequential circuits. – counter Output determined by inputs and There are several flavors previous outputs. Ex: memory, program counter, CPU. 3 4 S-R flip flop Relay-based flip-flop RSQ 00 Ex. Simplest feedback loop. Two relays A and B, both connected 01 to power, each blocked by the other. 10 State determined by whichever switches first. The state is latched. 11 Stable. Q=S+RQ output1 input2 input1 output2 5 6 SR Flip Flop Flip-Flop SR flip flop. Two cross-coupled NOR gates. Flip-flop. A way to control the feedback loop. Q=R(S+Q) Abstraction that "remembers" one bit. R S Basic building block for memory and registers. RSQ Q 00 01 10 11 Caveat. Need to deal with switching delay. 7 8 Truth Table and Timing Diagram Clock SR Flip Flop Truth Table Truth table.
    [Show full text]
  • Designing Sequential Logic Circuits
    chapter7_pub.fm Page 270 Wednesday, November 22, 2000 8:41 AM CHAPTER 7 DESIGNING SEQUENTIAL LOGIC CIRCUITS Implementation techniques for flip-flops, latches, oscillators, pulse generators, and Schmitt triggers n Static versus dynamic realization n Choosing clocking strategies 7.1 Introduction 7.5.1 Dynamic Transmission-Gate Based Edge-triggred Registers 7.2 Timing Metrics for Sequential Circuits 7.5.2 C2MOS Dynamic Register: A Clock 7.3 Classification of Memory Elements Skew Insensitive Approach 7.4 Static Latches and Registers 7.5.3 True Single-Phase Clocked Register (TSPCR) 7.4.1The Bistability Principle 7.6 Pulse Registers 7.4.2SR Flip-Flops 6.4.2 The C2MOS Latch 7.4.3Multiplexer Based Latches 7.8.2 NORA-CMOS—A Logic Style for 7.4.4Master-Slave Based Edge Triggered Pipelined Structures Register 7.5.3 True Single-Phase Clocked Register 7.4.5Non-ideal clock signals (TSPCR) 7.7 Sense-Amplifier Based Registers 7.4.6Low-Voltage Static Latches 7.8 Pipelining: An approach to optimize sequential 7.5 Dynamic Latches and Registers circuits 270 chapter7_pub.fm Page 271 Wednesday, November 22, 2000 8:41 AM Section 271 7.8.1Latch- vs. Register-Based Pipelines 7.8.2NORA-CMOS—A Logic Style for Pipelined Structures 7.9 Non-Bistable Sequential Circuits 7.9.1The Schmitt Trigger 7.9.2Monostable Sequential Circuits 7.9.3Astable Circuits 7.10 Perspective: Choosing a Clocking Strategy 7.11 Summary 7.12 To Probe Further 7.13 Exercises and Design Problems chapter7_pub.fm Page 272 Wednesday, November 22, 2000 8:41 AM 272 DESIGNING SEQUENTIAL LOGIC CIRCUITS Chapter 7 7.1 Introduction Combinational logic circuits that were described earlier have the property that the output of a logic block is only a function of the current input values, assuming that enough time has elapsed for the logic gates to settle.
    [Show full text]
  • Floating Point Exception Tracking and NAN Propagation
    Floating point exception tracking and NAN propagation By Agner Fog. Technical University of Denmark. © 2018-2020 CC-BY. Last updated 2020-04-27. Abstract The most common methods for detecting floating point errors are based on exception trapping or a global status register. These methods are inefficient in modern systems that use out-of-order parallelism and single-instruction-multiple-data (SIMD) parallelism for improving performance. It is argued that a method based on NAN propagation is more efficient and deterministic. Problems with NAN propagation in current systems are discussed. Examples of implementation in the C++ vector class library and in an experimental instruction set named ForwardCom are presented. The IEEE-754 standard for floating point arithmetic may need adjustment to accommodate the needs of modern forms of parallelism. Contents 1 Introduction ....................................................................................................................... 1 2 Exception trapping ............................................................................................................. 2 3 Using a status register ....................................................................................................... 3 4 Using errno ........................................................................................................................ 3 5 Parallel error detection ...................................................................................................... 3 6 Propagation of INF and NAN
    [Show full text]