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Am572x Sitara™ Processors Silicon Revision 2.0 Datasheet

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Am572x Sitara™ Processors Silicon Revision 2.0 Datasheet Product Order Technical Tools & Support & Folder Now Documents Software Community AM5729, AM5728, AM5726 SPRS953G –DECEMBER 2015–REVISED NOVEMBER 2019 AM572x Sitara™ Processors Silicon Revision 2.0 1 Device Overview 1.1 Features 1 • Dual Arm® Cortex®-A15 microprocessor subsystem • General-Purpose Memory Controller (GPMC) • Up to 2 C66x floating-point VLIW DSP • Enhanced Direct Memory Access (EDMA) – Fully object-code compatible with C67x and controller C64x+ • 2-port gigabit ethernet (GMAC) – Up to thirty-two 16 × 16-bit fixed-point multiplies • Sixteen 32-bit general-purpose timers per cycle • 32-bit MPU watchdog timer • Up to 2.5MB of on-chip L3 RAM • Five Inter-Integrated Circuit ( I2C™) ports • Two DDR3/DDR3L memory interface (EMIF) • HDQ™/ 1-Wire® interface modules • Ten configurable UART/IrDA/CIR modules – Supports up to DDR3-1066 • Four Multichannel Serial Peripheral Interfaces – Up to 2GB supported per EMIF (McSPI) • 2x dual Arm® Cortex®-M4 co-processors (IPU1 and • Quad SPI interface (QSPI) IPU2) • SATA gen2 interface • Up to four Embedded Vision Engines (EVEs) • Eight Multichannel Audio Serial Port (McASP) • IVA-HD subsystem modules – 4K @ 15fps encode and decode support for • SuperSpeed USB 3.0 dual-role device H.264 CODEC • High-speed USB 2.0 dual-role device – Other CODECs are up to 1080p60 • Four Multimedia Card/Secure Digital/Secure Digital • Display subsystem Input Output interfaces ( MMC™/ SD®/SDIO) – Full-HD video (1920 × 1080p, 60 fps) • PCI-Express® 3.0 subsystems with two 5-Gbps – Multiple video input and video output lanes – 2D and 3D graphics – One 2-lane gen2-compliant port – Display controller with DMA engine and up to – or two 1-lane gen2-compliant ports three pipelines • Dual Controller Area Network (DCAN) modules – HDMI® encoder: HDMI 1.4a and DVI 1.0 – CAN 2.0B protocol compliant • Up to 247 General-Purpose I/O (GPIO) pins • 2x dual-core Programmable Real-Time Unit and • Power, Reset, and Clock Management (PRCM) Industrial Communication SubSystem (PRU-ICSS) • On-chip debug with CTools technology • 2D-graphics accelerator (BB2D) subsystem • 28-nm CMOS technology – Vivante® GC320 core • 23 mm × 23 mm, 0.8-mm pitch, 760-pin BGA • Video Processing Engine (VPE) (ABC) • Dual-core PowerVR® SGX544™ 3D GPU • Crypto hardware accelerators – AES, SHA, RNG, DES and 3DES • Three video Input Port (VIP) modules 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. AM5729, AM5728, AM5726 SPRS953G –DECEMBER 2015–REVISED NOVEMBER 2019 www.ti.com 1.2 Applications • Industrial communication • High performance applications • Human Machine Interface (HMI) • Analytics • Automation and control • Other general use 1.3 Description AM572x Sitara™ processors are Arm applications processors built to meet the intense processing needs of modern embedded products. AM572x devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set. Cryptographic acceleration is available in every AM572x device. Programmability is provided by dual-core Arm® Cortex®-A15 RISC CPUs with Arm® Neon™ extension, and two TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with 4x EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSPs and coprocessors, thus reducing the complexity of the system software. Additionally, TI provides a complete set of development tools for the Arm and C66x DSP, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution. Device Information(1) PART NUMBER PACKAGE BODY SIZE AM5729ABC FCBGA (760) 23.0 mm × 23.0 mm AM5728ABC FCBGA (760) 23.0 mm × 23.0 mm AM5726ABC FCBGA (760) 23.0 mm × 23.0 mm (1) For more information, see Section 10, Mechanical, Packaging, and Orderable Information. 2 Device Overview Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 AM5729, AM5728, AM5726 www.ti.com SPRS953G –DECEMBER 2015–REVISED NOVEMBER 2019 1.4 Functional Block Diagram Figure 1-1 is functional block diagram for the device. AM572x MPU IVA HD Display Subsystem (2x Arm 1080p Video Cortex–A15) Co-Processor 1x GFX Pipeline LCD1 LCD2 GPU BB2D 3x Video Pipeline LCD3 (2x SGX544 3D) (GC320 2D) Blend / Scale HDMI 1.4a DSP IPU1 (Dual Cortex–M4) (2x C66x Vision Acceleration Pac Co-Processor) IPU2 4x EVE Analytic Processors (Dual Cortex–M4) EDMA sDMA MMU x2 VIP x3 Crypto VPE High-Speed Interconnect System Connectivity Spinlock Timers x16 PWM SS x3 USB 3.0 PCIe SS x2 Dual Role FS/HS/SS Mailbox x13 WDT HDQ w/ PHYs PRU-ICSS x2 GPIO x8 RTC SS KBD USB 2.0 Dual Role FS/HS GMAC_SW w/ PHY Serial Interfaces Program/Data Storage UART x10 QSPI MMC / SD x4 SATA DMM McSPI x4 McASP x8 Up to 2.5 MB GPMC / ELM EMIF x2 OCMC_RAM (NAND/NOR/ 2x 32-bit DCAN x2 I2C x5 w/ ECC Async) DDR3(L) intro-001 Figure 1-1. AM572x Block Diagram Copyright © 2015–2019, Texas Instruments Incorporated Device Overview 3 Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 AM5729, AM5728, AM5726 SPRS953G –DECEMBER 2015–REVISED NOVEMBER 2019 www.ti.com Table of Contents 1 Device Overview ......................................... 1 7.11 Timers.............................................. 269 1.1 Features .............................................. 1 7.12 Inter-Integrated Circuit Interface (I2C) ............. 270 1.2 Applications........................................... 2 7.13 HDQ / 1-Wire Interface (HDQ1W) ................. 273 1.3 Description............................................ 2 7.14 Universal Asynchronous Receiver Transmitter 1.4 Functional Block Diagram ........................... 3 (UART) ............................................. 275 2 Revision History ......................................... 5 7.15 Multichannel Serial Peripheral Interface (McSPI) . 276 3 Device Comparison ..................................... 6 7.16 Quad Serial Peripheral Interface (QSPI) .......... 282 3.1 Related Products ..................................... 8 7.17 Multichannel Audio Serial Port (McASP) .......... 287 4 Terminal Configuration and Functions.............. 9 7.18 Universal Serial Bus (USB) ........................ 306 4.1 Terminal Assignment ................................. 9 7.19 Serial Advanced Technology Attachment (SATA). 306 7.20 Peripheral Component Interconnect Express 4.2 Ball Characteristics.................................. 10 (PCIe) .............................................. 306 4.3 Multiplexing Characteristics ......................... 90 7.21 Controller Area Network Interface (DCAN) ........ 307 4.4 Signal Descriptions ................................ 110 7.22 Ethernet Interface (GMAC_SW) ................... 308 5 Specifications ......................................... 158 7.23 eMMC/SD/SDIO ................................... 319 5.1 Absolute Maximum Ratings........................ 158 7.24 General-Purpose Interface (GPIO) ................ 345 5.2 ESD Ratings 159 ....................................... 7.25 Programmable Real-Time Unit Subsystem and 5.3 Power on Hours (POH) Limits ..................... 160 Industrial Communication Subsystem (PRU-ICSS) 346 5.4 Recommended Operating Conditions ............. 161 7.26 System and Miscellaneous interfaces ............. 372 5.5 Operating Performance Points..................... 164 7.27 Test Interfaces ..................................... 372 5.6 Power Consumption Summary .................... 183 8 Applications, Implementation, and Layout ...... 376 5.7 Electrical Characteristics........................... 183 8.1 Power Supply Mapping ............................ 376 5.8 Thermal Characteristics............................ 191 8.2 DDR3 Board Design and Layout Guidelines....... 377 5.9 Power Supply Sequences ......................... 193 8.3 High Speed Differential Signal Routing Guidance. 400 6 Clock Specifications ................................. 198 8.4 Power Distribution Network Implementation 6.1 Input Clock Specifications ......................... 199 Guidance........................................... 400 6.2 RC On-die Oscillator Clock ........................ 207 8.5 Thermal Solution Guidance........................ 400 6.3 DPLLs, DLLs Specifications ....................... 208 8.6 Single-Ended Interfaces ........................... 400 7 Timing Requirements and Switching 8.7 LJCB_REFN/P Connections....................... 402 Characteristics ........................................ 212 8.8 Clock Routing Guidelines .......................... 403 7.1 Timing Test Conditions ............................ 212 9 Device and Documentation Support.............. 405 7.2 Interface Clock Specifications ..................... 212 9.1 Device Nomenclature .............................. 405 7.3 Timing Parameters and Information ............... 212 9.2 Tools and Software ................................ 407 7.4 Recommended Clock and Control Signal Transition 9.3 Documentation Support............................ 408 Behavior............................................ 214 9.4 Related Links ...................................... 408 7.5 Virtual and Manual I/O Timing Modes ............. 214 9.5 Support Resources ................................ 408 7.6 Video Input Ports
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