CSPI 2000 Series Datasheet

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Find the CSPI 2741 at our website: Click HERE 2000 SERIES

Rugged High Performance Scalable Embedded Clusters

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Innovative Solutions from CSPI Cluster computing is rapidly becoming the preferred technology for Embedded High Performance Computing (HPC). Early adopt- ers are now turning to proven commercial turnkey solutions to capitalize upon the open source Linux environment and MPI as the preferred message passing paradigm making GASS improves real-time target, ocean & it possible to go from research to deployment sensor modeling capabilities of Navy ASW without any software changes accelerating the trainers. development cycles.

A large class of DOD applications require HPC systems to run simulations based upon complex models demanding the processing power of 100's to 1000's of processing nodes. Memory requirements also increase propor- tionally with the complexity of these problems.

Complex real-time signal processing and analysis applications require scalable platforms to meet the requirements of large radar and sonar systems, trainers and simulators. Meeting the challenge of the future, clustering solutions using standard COTS technologies and open Hydra Sonar Systems are incorporated into source software are the best path to offer the Swedish Navy’s Visby class ships hardware and software technology insertion, support and affordable development costs.

Rugged Platforms The FastCluster 2000 SERIES features the compute processing density, rugged packaging, low power, high availability, outstanding performance, scalable open architecture and clustering technology required to support sonar, radar, Command, Control, Communications, Computers, Intelligence, Surveillance and Reconnaissance (C4ISR) applications intended for deployment in the harsh and confined environments of shipboard, airborne, and land- mobile platforms.

SAPPS will be used by the Royal Swedish Navy to analyze active and passive sonar records

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Variants of Mk92 fire control systems are installed on FFG-7 frigates world- Experience wide CSPI was founded in 1968 and has over 30 years of experience specifying, designing, and manufacturing commercial and rugged

COTS products that deliver architectural peak Some CSPI Program Wins: performance in compliance with standards. Sonar Signal Processing CSPI hardware expertise includes ASIC design for memory controllers and I/O for The Hydra Program RISC and DSP architectures ranging from Computing Devices Canada Ltd. the early i860 and SHARC to the more current PowerPC and AltiVec. In addition, most Stimulation / AWS Trainers CSPI product designs involve the integration Generic Acoustic Stimulation System of the Myrinet chipset switches and network (GASS) Program processors. With a focus on delivering ultra Northrop Grumman Norden Systems, Inc. dense COTS systems CSPI has extensive DSP COTS technology upgrade experience with multi-layer PC boards, back- Mk92 Fire Control System planes, systems packaging, ASIC and FPGA designs. Lockheed Martin / Indra Sistemas S.A.

CSPI software expertise includes optimizing Surveillance Radar signal processing libraries and O/S support Advanced Hawkeye Program (E2-C) for Linux, VxWorks, SuperKit, and PSOS. Lockheed Martin CSPI has been selected for a wide variety of DOD programs because our product offerings Test and Evaluation RSG Program (Aegis Combat System) include several options to afford the customer Lockheed Martin for the U.S. Navy's flexibility in selecting the best modules to Combat System Engineering configure a system that meets their applica- Development Site (CSEDS) tion specific needs. A partnership with CSPI provides the customer access to Single Sonar Board Computers, Blades, MultiComputers, Sonar Acoustic Post Processing System

I/O components, disk drives, cabling and (SAPPS) enclosures designed with adherence to stan- Array Systems Computing / Royal dards, integrated and supported by a single Swedish Navy vendor.

CSPI has always provided product solutions Rugged 2000 SERIES that are complete systems, integrating both MultiComputers are used hardware and software. CSPI provides all of in the next generation radar the tools and support necessary for the user for the E--2C Hawkeye to develop, deploy and maintain the product that they themselves have created.

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ECC SDRAM Cache Open Standards Single Processing Node

All FastCluster hardware and software (MPC74xx with AltiVec) ASIC PowerPC Memory Controller is based on open technology, com- Flash The nucleus of the FastCluster system is the MPC74xx modity components and industry stan- Network Interface processing node. FastCluster is a Myrinet Controller dards. This makes it easy for engineers based product that utilizes a two-level architecture for the processing node, thus optimiz- Myrinet Switch to develop and maintain their applica- ing the strengths of each part of the system. tions. The result is reduced costs and The first level is the compute processor. The second level of the architecture is the Myrinet High Speed Packet increased customer satisfaction. It also LANai RISC processor. Specifically the LANai Switched Interconnect offloads communication tasks from the com- SRAM Buffer means that the user, if need be, can pute processor. This unique two-level archi- Address Data draw upon other tools developed to the tecture allows the commodity processor to do Processor Bus what it is best at, namely computation, and LANai allows the LANai processor to do what it is Network same standards to aide in their appli- Processor best at by performing the I/O. Backplane cation development. 500 MB/sec P0 Connector SAN Cable 16 Port SAN Myrinet Converter SAN/ SAN/ Switch Fault Tolerant Features Fiber Fiber LAN Connector Each FastCluster embedded blade Fibre Connector Fiber Optic SAN Connector has built-in self-test features and safe- guards to monitor and protect against power and thermal events that would Commodity Processor data between processors at full duplex interrupt normal system operation. The first level is the compute proces- speeds up to 250 MB per second in sor, which is a commodity processor each direction for a total of 500 MB Live Insertion that has its strengths in its ability to per second per port.The LANai is used All modules support live insertion. perform multiple gigaflops as well as in conjunction with a 16 port Myrinet being a very good general processor. switch to interconnect every proces- Modularity The current processor is the Motorola sor to every other processor within the Small Line Replaceable Units (LRUs) 7457 at 1 GHz with 2MB of L3 cache. system. are used to implement the system reducing the cost of spares and facili- LANai FLASH tating quick maintenance and deploy- The current LANai, Myrinet-2000 Every processing node in the system ment. LANai 9, is capable of transferring has a large flash memory [32MB] where the operating system resides. This means that each processor can Product and Technology Roadmap boot from flash greatly increasing the speed of the system booting. Each IndustryIndustry Standards,Standards, OpenOpen Technologies,Technologies, CommodityCommodity ComponentsComponents node can boot stand-alone instead of

6U x 160mm VME VME64x with PO VME64x, 9U, CPCI, PMC I/O having to compete with other nodes Myrinet on VME (ANSI/VITA 26-1998 Myrinet-2000 (Standard reaffirmed 2003) Myrinet-2000 for a single I/O resource and/or disk Level I & II Environmental Air Cooled, Rugged Level III - Conduction Cooled MIL SPEC resource to boot from. VxWorks (RTOS) VxWorks and/or Linux VxWorks and/or Linux FPDP FPDP, PCI/PMC FPDP, PCI/PMC, Fiber The user also has access to the

11 GHz+GHz+ PowerPCPowerPC 74xx74xx FLASH on each node, such that the 29422942 MultiComputerMultiComputer // BladeBlade StarGateStarGate 29232923 withwith PMCPMC I/OI/O user application can reside in flash as 400-500400-500 MHzMHz PowerPCPowerPC 74xx74xx 2814,2814, 2840.2840. 2841,2841, 28422842 MultiComputersMultiComputers well. This translates to a fast cold start JumpGate 2823 with PMC I/O JumpGate 2823 with PMC I/O to run-time mode. 300-400300-400 MHzMHz PowerPCPowerPC 7xx7xx 2711,2711, 2740,2740, 2741,2741, 27422742 MultiComputersMultiComputers

200-300200-300 MHzMHz PowerPCPowerPC 603603 2610,2610, 2640,2640, 26412641 MultiComputersMultiComputers 1998 1999 2000 2001 2002 2003 2004 2005

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ECC SDRAM Myrinet-2000 cesses for low-latency communica- Each node has up to 1 GByte of error- Myrinet-2000 is a third generation prod- tion, and directly with the network correcting SDRAM. uct based on the American National to send, receive, and buffer packets. Standard, ANSI/VITA 26-1998. All The hardware computes and checks Switched Fabric Network components are implemented with a CRC for each packet on each link. CSPI was an early adopter of Myrinet, full-custom-VLSI CMOS chips. These The interfaces provide parity checking a high-speed packet-communication CMOS-based Myrinet components are both in memory and on the PCI bus. and switching technology, and has extremely reliable. The MTBF of cur- Moreover, Myrinet continuously maps over seven years of experience inte- rent-production Myrinet switches and itself to find alternate routes, creat- grating this interconnect into multipro- interfaces exceeds 5 million hours per ing a dynamic topology to circumvent cessing systems targeted at defense port. Myrinet exhibits a very low bit- faults. This approach enhances data applications. The continued use of the error rate, and is highly robust with integrity and security by creating a low power consumption Myrinet com- respect to host, switch, and cable high availability network. The network ponents for the interconnect interface faultTransmitting information in data itself remains available because it can on FastCluster products contributes to packets routed as point to point com- detect and isolate points of failure and the viability of the product for defense munications between sender and will re-route information to other hosts applications such as C4ISR programs. receiver Myrinet attains a maximum to maintain an operational state. The benefits of this switched fab- bandwidth of full-duplex 2+2 Gigabit/ ric architecture are many: reliability second data rate on each link to con- Leading Technology (robustness), scalability (performance verge with industry-standard 2.5GBaud Myrinet is now the market leader in HPC increases in a linear manner as the 8b/10b-encoded serial links. This pro- Clusters with 187 systems in the Jun- network grows), modularity, interoper- tocol permits standard services across 04 TOP500 (500 fastest clusters) utiliz- ability and seamless operation regard- heterogeneous processors. Myrinet ing Myrinet technology. Some of these less of whether the packet contains host interfaces execute a control pro- systems are implemented with 1000's voice, video or a data transmission. gram to interact directly with host pro- of nodes. CSPI’s scalable FastCluster systems leverage the Myrinet clustering technology, the chipset (network processor and switch) and the Myrinet well proven software stack (MPI, GM) for DOD embedded systems. Every compute node is interconnected to every other compute node with the same interconnect (Myrinet-2000) so the user can predict I/O performance as well.

A Clos network architecture is implemented to ensure the best bisection bandwidth for the system. In addition to high-speed transmission Myrinet delivers flexibility with a clustering technology that can switch many different protocols, including Gigabit Ethernet,

The Myrinet environment provides the capability to monitor, analyze, and simulate network activ- providing a seamless migration path ity. The Merlin 1.2 tool creates a visualization of the current network topology showing all nodes, for the future. switches, and the interconnect paths between them. This graphical representation employs a color-coding scheme to display network traffic intensity, offering a quick overview of the communication patterns and data volume transferred between nodes and systems.

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Blower Assembly

6U VME Card Cage Power Supply

3 slots for 9U x 220 Line Cards

Extended Backplane Adapter Switch 20 Slot Rugged Chassis such that all connections to external is used to implement the network Partnering with Elma, CSPI is able equipment are available in the rear of interconnect. Message packets flow to offer a 20 Slot Rugged Chassis the unit. The system power supply is through switches which automatically designed to meet the harsh environ- mounted on a shock isolated platform select link data rates according to the ment of shipboard and airborne appli- near the rear of the chassis and all type of cabling used. These switches cations. The chassis has been suc- cooling air is pulled through an EMI are physically small, low-power, self- cessfully tested numerous times to filtered rear panel. initializing devices that can be placed environment levels of MIL-STD-810E in any location for convenient cabling and MIL-STD-167 and to the EMC Extended Backplane Adapter Switch of the network. Several types of switch requirements of MIL-STD-461E. (EBAS) modules are available to accommo- The latest CSPI ruggeded chassis uti- date configuration differences. The system, packaged in a standard lizes an acitve backplane 19" rack configuration has a height of switch module to inter- 35" and a depth of 25". The front of the face between the VME unit contains power and reset switches 6U backplane and the 9U and voltage indicators along with fan line cards. fail and overtemp indicators. Other CSPI chas- All plug-in circuit boards are removable sis employ Backplane from the front. All fiber optic signals are Overlay Switch Modules connected to the front of the cards and or Adapters to provide Backplane Overlay Switch Module are cabled to the rear interface panel cut-through routing that

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FastCluster 2942 Blade 6U Board The 6U card cage is designed Designed with four 1 GHz Motorola for processor or I/O boards. It might 7457 high performance, low power, 32- feature the new FastCluster 2942 bit PowerPC microprocessors directly blade incorporating a host processor on the motherboard, the FastCluster that provides increased performance 2942 6U VME blade eliminates the use and efficient power consumption to of mezzanines to optimize compute satisfy the most stringent demands of density, airflow and cooling our defense customers.

Clos Network The Clos network, first described by Charles Clos in a paper published in 1954, has several properties that

high utilization of specific network links that can result from single-route map- pings.. This same dispersive routing technique provides fault tolerance as it creates redundant paths between hosts allowing for a message to be

Myrinet 9U Line Card (8 Fiber Connections) resend along another route if a failure is encountered. between hosts. This topology creates make it an ideal topology for a cluster so many paths between hosts that the Myrinet 9U Line Card network: the ability to scale to a large minimum bisection of this network -- its The 9U Line Card is designed with a size, modularity, multiple redundant traffic handling capacity -- is as large VME PO backplane connector on the paths, and full bisection bandwidth. as possible. rear of the card, a 16-port crossbar switch and eight external connectors Clos networks require a lot of switch- The Clos topology providing multiple on the front panel. es, and a lot of switch-to-switch com- routes between hosts ensures all the munication links. The basic building shortest routes are deadlock-free. block of the Myrinet Clos Network is a Each host interface can send suc- 16-port crossbar switch implemented cessive packets to another host along on a single chip. This crossbar switch multiple routes, thus the traffic is dis- is used to create communication links persed in a way that statistically avoids

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VxWorks / Tornado II VxWorksVxWorks / Tornado II Linux / LinuxGNU Tool Suite VxWorks, including the WIND AltiVec Compiler Microkernel, is a POSIX compliant AltiVec Compiler real-time operating system environ- C / C++ ment providing fast multi-tasking, inter- C / C++ ISSPL rupt support, and both preemptive and ISSPL round robin scheduling for determinis- VSIPL Core Lite, VSI/Pro Core tic response to external events. VSIPL Core Lite, VSI/Pro Core CORBA / GM CORBA / GM This efficient RTOS incorporates such MPI /BDMP MPIch/GM features as a scalable run-time kernel MPI 1.2/BDMP MPIch/GM to conserve code space and sup- JAVA FTLib/BDMPFTLib/BDMP JAVA port for many different Application GEDAE Fortran Programming Interfaces (API's). Inter GEDAE Fortran task communication can be accom- DDD/GDBDDD/GDB symbolic symbolic debugger debugger plished using shared memory, message queues, semaphores, events and XX Windows Windows pipes, sockets and remote procedure calls, and signals allowing the developer design flexibility to best meet the written on a few processing nodes for print statements dumping the contents needs of an application. The integrated simplicity, and then easily expanded of variables or buffers to the screen or networking offers data transmission to invoke additional nodes for faster a file for later analysis, and by symbolic over the Myrinet fabric. Industry-stan- execution. MPI is the preferred mul- debugging. dard protocols such as TCP/IP, UDP, tiprocessing API for high-performance NFS, FTP, SLIP, BOOTP and Berkley computing. More sophisticated debugging and sockets are supported throughout the development tools are available from network as well. This protocol per- MPI, ISSPL and VSIPL are designed CSPI and our partners upon request. mits interoperability between heteroge- to enhance the portability of embedded neous processors. applications, allowing development on Linux / GNU Tool Suite a workstation and ease of migration The CSPI Linux software environment CSPI is currently shipping systems for implementation in an embedded consists of the kernel, libraries, utilities, with VxWorks 5.4 and Tornado II sup- environment. and development tools. It is based on porting an application layer that uses a POSIX implementation including true C, C++, ISSPL or VSIPL, and MPI to Compilers and Debugging Tools multitasking, virtual memory, shared facilitate portability and software reuse The FastCluster development environ- libraries, demand loading, work load ment supports the C and C++ compil- balancing, and support for TCP/IP net- Message Passing Interface (MPI) ers optimized for a PowerPC target. working. The Linux operating system This parallel programming library pro- Other compilers are available from is easily integrated with clustering soft- vides multiprocessor control and inter- third party vendors and are easily inte- ware such as MPI and includes a full processor communication. This library grated into the open source, standards suite of GNU compiler tools to facilitate provides a simplified way for the pro- based FastCluster platform. development. grammer to associate specific data with specific processes. The MPI Simple debugging on FastCluster sys- Applications developed with Linux and library provides the functions neces- tems can be accomplished using stan- MPI are processor independent and sary to create dynamically scalable dard “C” assertions to confirm assump- vendor independent. Using standard applications. An application may be tions, by instrumenting applications with API's and an open source approach

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built on a layered architecture enables are callable from C and C++ compiled cessing applications. The function collaborative development whereby programs to achieve rapid and effi- calls are organized into four primary engineers may work concurrently with- cient program development. The C categories: support functions, basic out destroying each other’s contribu- emulations of all standard ISSPL-ALT scalar operations, basic vector operations. Linux also provides a common functions are available for initial devel- tions and signal processing. Support software environment permitting the opment work. functions facilitate object creation and same technology to exist on both the interaction as well as memory man- developers desktop (host system) As a convenience, there are func- agement. The scalar and vector opera- and the deployment platform (target). tions included in the library to pro- tions allow the programmer to per- Available on most processor architec- vide backward compatibility with ear- form numerical computation on dense tures, Linux promotes the creation of lier versions of ISSPL. These func- rectangular arrays. Signal processing an integrated hardware and software tions assist in converting older pro- functions include FFT operations, filter- solution. Application code developed grams and help protect the user's ing, correlation and convolution. on a PC or cluster of workstations is software investment. The ISSPL-ALT binary compatible with the embedded includes routines from the Floating The object-oriented design of the VSIPL platform. Linux is of general interest Point System, Inc. FPS Math™ Library, API employs the concept of blocks and to the modern developer due to these Quantitative Technology Corporation's views to provide a level of abstraction advantages. Math Advantage™ and the Society of from the memory and processor archi- Exploration Geophysicists standard. tecture of the underlying machine. A Two well-known patches (the pre- block is a contiguous area of memory emptive kernel patch and the latency Vector Signal and Image Processing used for data storage. Views are a patch) supplement the Linux operat- Library (VSIPL) method for classifying the data as vec- ing system to drastically improve the The VSIPL is the result of a DARPA tors or matrices. Blocks and views are real-time characteristics of the kernel. sponsored effort to define an open, created, accessed and destroyed via CSPI is shipping these patches with industry standard API for vector, sig- library functions. Manipulating blocks its FastCluster Linux 2.4 release to nal, and image processing primitives and views via library functions assists address the "hard" real-requirements targeted at embedded real-time signal the application programmer in writing of embedded applications. processing systems. code that is truly portable and compat- Implemented according to the "Core ible. Industry Standard Signal Processing Lite" profile, VSIPL is a library of 125 Library (ISSPL) functions for vector-based signal pro- The ISSPL-ALT is a highly optimized library of over 250 functions for 32-bit Optimized ISSPL-ALT Library signal and image processing programs Measured Performance Data - Complex FFT for the PowerPC™ 745x series. 1200

The ISSPL-ALT reduces programming 1000 complexity by providing a single call- 800 ing function for complex mathematical μSec 2641 (300 MHz 603) 2741 (400 MHz 750) 600 and signal processing routines. Both 2841 (400 MHz 7410) development and execution times are 2923 (1 GHz 7457) 400 significantly improved. The ISSPL-ALT provides a full compliment of rou- 200 tines to take advantage of both the 0 AltiVec™ and Floating-Point units of 256 512 1024 2048 the PowerPC 745x series. All routines Size (in points)

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test. POST must run in less than CSPI I/O processing solutions are five seconds. If a failure is detected, based on PMC modular designs. This A typical CSPI FastCluster 6U blade POST saves a diagnostic code in approach of a node having a PCI inter- incorporates: non-volatile memory, then reads two face and a Myrinet network interface parameters from non-volatile mem- allows flexible I/O operations. 1. The latest processor, currently ory. If either OVERRIDE or POST_ the AltiVec PowerPC, offering the best OVERRIDE is set, POST transfers Several mass storage options are also available general purpose GLOPS/Watt control back to the product's boot possible using the PCI/PMC interface: microprocessor. procedure. Otherwise, POST reports PMC FLASH, PMC Fiber Channel, a a failure code. PMC RAID Disk, and/or PMC SCSI 2. The latest memory technology, disk drives. PMC FLASH memory of 2 error-correcting, 64-bit 100 MHz ECC POST begins with verification of GBytes per PMC provides a significant SDRAM that performs reads at 640 MB/s the CRC-32 checksum of the POST RAM disk capability supported under and writes at 800 MB/s, in configurations itself. This confirms that the POST Linux. This is ideal to configure and at up to 1 GB per processor program itself is not corrupted. download the Linux OS, applications POST then proceeds to verify the and system tests, and to support the 3. High-speed interconnect technol- correct operation of a small region of complete stand alone operation of a ogy, Myrinet-2000, delivering interoper- low memory. This region is used for FastCluster system. This FLASH disk ability with previous generation products, stack, interrupt vectors, and global capability is independent of the dedi- low power consumption, and a large variables.This is followed by tests cated FLASH memory available on endorsement from the HPC community to verify correct operation of data each processing node (32 MB). with clusters of 1,000’s of nodes already and address signals for the DRAM, implemented. CACHE, and LANai SRAM. POST concludes with tests to verify the 4. High Availability features includ- correct operation of DMA to and ing fast booting from a cold start, hot- from main memory and the LANai swappable hardware and power on self memory as well as checking the test. operation of all external interrupt signals.

In the unlikely Power On Self Test (POST) event that a prob- Each Fastcluster node has firmware, lem is encountered residing in the node’s flash memo- once a system is ry, that consists of a bootloader, a up and running, all Power On Self Test (POST), a com- CSPI systems sup- pressed kernel, and a ROM file system port live insertion (ROMFS). The ROMFS contains the for replacement of libraries, kernel modules, and execut- 6U Blades and line The StarGate 2923 delivers an open and scalable programs that allow the node able system solution for applications, such as cards. signal processing, that are compute intensive to get hooked into the network fabric and require high speed data streaming (sup- and to begin executing applications. ported by 2 PMC slots). The StarGate 2923 utilizes the Motorola 7457 microprocessor with AltiVec™ at 1 GHz and Upon power-up or following a hard has 1 GByte of ECC SDRAM per processing node and a network interface based on the reset, the bootloader is the first piece 250/250 MB/s Myrinet-2000 network fabric. of code to execute, followed by POST, I/O Solutions if the system is configured to run this

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Environmental Specifications Another important goal in designing CSPI provides conformal coating on All CSPI boards are designed to meet circuit boards for an extreme struc- some board products to meet aggres- the severe environmental specifications tural environment is to increase the sive humidity and salt spray specifi- encountered in airborne and shipboard natural frequency of vibration above or cations. CSPI has studied various programs. During the board design between the frequencies at which large types of coatings including Parylene, phase, care is taken in the physical forces occur in an airborne environ- acrylic, and urethane to determine layout to optimize airflow paths. A ment. CSPI uses printed circuit boards both their ability to protect compo- detailed thermal analysis is also per- designed with a thermal/stiffener rib to nents from moisture and the ease in formed using the Harvard Thermal Inc. increase structural integrity for shock which the coatings can be removed TAS Temperature Modeling System. and vibration. The weight of the board to facilitate board repair. In addi- Several iterations of thermal model- is reduced wherever possible, such as tion, tests were performed to analyze ing result in an improved board layout in the choice of heat sink material, to the effect various conformal coatings and heat sink design and an optimized benefit airborne systems where weight would have in the case-to-air thermal thermal profile. From this analysis, is at a premium. resistance, and hence the cooling abil- along with actual test data, the airflow ity, of board components. Analysis requirements and operating tempera- In the hardware design effort, CSPI of the ability of coatings to protect ture range is defined. had a finite element model developed SMT devices was also done, as those where simulated shock and vibration devices are more difficult to protect. CSPI uses a rigorous worst-case forces were applied to determine the design approach, which results in wide FastCluster blade design's ability to voltage, temperature and clock fre- survive various levels of stress. quency margins. Shock and Vibration Conformal Coating

Level I Level II Level III Environmental Commercial Extended Rugged Parameters Industrial Temperature

Ambient Air Temperature 0º C to 40º C 0º C to 55º C @ -10º C to 55º C Range @ 12 cfm 12 cfm @ 12 cfm

Ambient Air Relative up to 95% up to 95% up to 95%* Humidity non-condensing non-condensing 10 cycles @ 240 hrs.

Maximum 10,000 ft. ** 10,000 ft. ** 10,000 ft. ** Altitude

Shock 15gs @ 15 gs @ 20 gs @ 11 ms half sine 11 ms half sine 11 ms half sine

2 2 Vibration 0.002 g2/Hz 0.002 g /Hz 0.04 g /Hz (random) 10 - 2000 Hz 10 - 2000 Hz 10 - 2000 Hz

Storage -40º C to 85º C Temperature -40º C to 85º C -40º C to 85º C * Requires Conformal Coating. **Ambient Temperature, Airflow and Altitude parameters can be traded off among each other .

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CSPI Chassis mize system airflow. Cabling wireways, modules to achieve the scalable pro- All CSPI chassis products are designed cessing and I/O performance required with the customer in mind. Adherence by a broad class of High Performance To address these diverse operating and to standard connections and rack- storage environments at the lowest cost Computing applications. mountable dimensions make it easy to to the customer, CSPI offers its products in three classes: integrate components in our chassis. The CSPI 21 Slot Chassis is another Level 1: Commercial/Industrial used for development, installation in alternative for systems requiring Level CSPI chassis products are intended benign environments I and Level II compliance.

to operate in a variety of environments Level II: Extended Temperature used for systems that operate in an while maintaining form, fit and func- extended temperature environment The CSPI 21 Slot Chassis uses a tion compatibility across the product thermal management scheme that opti- Level III: Rugged line. These environments can range used in environments with high levels of mizes forced air cooling to house a shock, vibration, humidity, and extended from trucks exposed to the desert temperature. full compliment of 21 multiprocessor heat to shipboard installations, from a boards. Maintaining a high value of air developers desktop to a helicopter or flow allows CSPI’s Level I and Level II fixed wing aircraft. Each environment 21 slot chassis products to operate at has unique characteristics with distinct and peripheral device mounting elevated attitudes for non-pressurized requirements. airborne requirements. capability make the most efficient use 5 Slot Chassis of the compact space available in the Judicious placement of structural and chassis. support members in the CSPI 21 Slot Chassis enhances the ability of the The CSPI 5 Slot Chassis uses tem- chassis to endure the shock and vibra- perature controlled high output axial tion encountered in normal transporta- fans. Since this chassis may be used tion and exceed those levels for use in in an office environment, the speed many airborne applications. of the fans is temperature controlled, keeping audible noise to a minimum. Additionally, all cables, in both the 5 Slot and 21 Slot Chassis, are routed and The CSPI 5 Slot Chassis has been restrained to prevent failure and all con- designed to endure the shock and nectors contain lockdowns to prevent vibration encountered in normal trans signal interruption. portation.

21 Slot Chassis The CSPI 21 Slot Chassis provides a The CSPI 5 Slot Chassis is an ideal 9U high, front choice for systems requiring a loaded chas- small footprint and Level I and Level sis designed to II compliance. Removable front panels, accommodate a rear I/O interface panels, and optional variety of 2000 slides facilitate the servicing of compo- SERIES boards nents. The chassis is designed to opti- and transition

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Level I Level II Level III perform under the most stringent condi- Environmental Commercial Extended Rugged tions required by your defense applica- Parameters Industrial Temperature tion.

Inlet Air The power supplies in all CSPI chassis 0º C to 40º C 0º C to 55º C -10º C to 60º C Temperature products have the highest possible effi- Range ciency, consistent with the voltage and Ambient Air current specifications, to reduce inter- Relative up to 95%* up to 95%* up to 95%* nal power supply heat dissipation. Humidity non-condensing non-condensing non-condensing Each chassis product is further equipped Maximum Altitude 10,000 ft. ** 10,000 ft. ** 10,000 ft. ** with a temperature warning system and shutdown feature in the event that 10 G’s 20 G’s Shock 10 G’s overheating were to occur because of a 11 ms half sine 11 ms half sine 11 ms half sine board, fan or power supply failure. Vibration 0.002 G2/Hz 0.002 G2/Hz 0.04 G2/Hz 10 to 2000 Hz 10 to 2000 Hz 10 to 2000 Hz Additionally, CSPI employs development and production techniques that Storage reduce conducted and radiated emana- Temperature -50° C to 100° C -50° C to 100° C -50° C to 100° C tions and that limit suspectibility to out- * Conformal Coating is available as an option for 100% humidity. **Ambient Temperature, Airflow and Altitude parameters can be traded off among each other side electrical and magnetic fields. . a protective chemical conversion coat 20 Slot Rugged Chassis The CSPI 20 Slot Rugged Chassis ing per MIL-C-5541E, Class C for cor uses a thermal management scheme rosion resistance. that maximizes forced air cooling to house a full compliment of 20 6U VME From the initial design phase through to boards. Special card guides that sta- final qualification test- bilize the circuit boards to withstand ing the CSPI 20 Slot higher levels of shock and vibration Rugged Chassis prod- have been selected to provide the wid- uct maintains a focus est possible openings and to ensure all on delivering a system available inlet air is productively used to package that will cool component and heatsink surfaces.

For structural integrity the CSPI 20 Slot Rugged Chassis uses 3mm thick aluminum side plates with spot wielded front, rear, top and bottom extruded aluminum profiles to endure the shock and vibration conditions encountered in The CSPI 20 Slot Rugged Chassis is an ideal choice to meet the needs of military applications and was manufactured to comply with the following tactical airborne and shipboard equip- MIL specs: ment. MIL-STD-167 Sinusoidal Vibration MIL-STD-810E Shock, Acceleration & Random Vibration MIL-STD-461D EMC/EMI All aluminum parts are enhanced with

Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com CSP Inc. was founded in The Company's MODCOMP, The MultiComputer Division 1968 and is based in Billerica, Inc. subsidiary, founded in 1970 designs and builds high-per- Massachusetts. To meet the which includes the 2003 acqui- formance cluster computing diverse requirements of its sition of Technisource, is a lead- systems for the defense mar- industrial, commercial, scien- ing provider of IT solutions and ket. These systems are dense tific and defense customers systems integration services. and rugged with powerful real- worldwide, CSPI and its sub- MODCOMP works with third time I/O and require minimum sidiaries develop and market parties to develop customized physical space or power. These cutting edge integration solu- solutions in the global IT mar- systems are used on land, air- tions for complex IT environ- kets and has offices in the U.S., borne and shipboard platforms ments and high-performance U.K. and Germany. for high speed digital signal cluster computer systems processing in radar, sonar and for military applications. The surveillance applications. Company’s wholly owned sub- sidiaries include MODCOMP, Inc. (“MODCOMP”), and CSPI MultiComputer Division (“MultiComputer Division”).

Among Our Customers

Alliant Tech Systems - AP Labs -- Applied Physics Lab, John Hopkins University Array Systems Computing, Inc. -- Australian Defense Science & Technology Organization BAE -- CTI/Siemens -- DY4 -- Elscint -- ESL -- General Electric -- Harris -- Hitachi Hughes -- IBM -- IM Systems -- IonSpec -- Landmark Graphics -- Lockheed Martin Los Almos National Laboratories -- Oki -- Phillips Medical -- Marconi -- MELCO NCCSC -- NEC -- Northrop Grumman -- NRAD -- NRL -- NUWC -- Raytheon Sanders -- Sandia -- Schlumberger -- Sismos -- Thompson --Varian

CSP Inc. 43 Manning Road Billerica, MA 01821-3901

Tel: 978-663-7598 Fax: 978-663-0150 www.cspi.com

The information contained herein is subject to change without prior notice. For the latest information contact your company representative. 2050-01 09/05

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