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Vi Xử Lý,Nguyễn Hoàng Dũng,Dhbkhn © DHBK 2005 Nội dung môn học 1. Giới thiệu chung về hệ vi xử lý 2. Bộ vi xử lý Intel 8088/8086 3. Lập trình hợp ngữ cho 8086 4. Tổ chức vào ra dữ liệu 5. Ngắt và xử lý ngắt 6. Truy cập bộ nhớ trực tiếp DMA 7. Các bộ vi xử lý trên thực tế cuu duong than cong . com 1 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 Chương 7: Các bộ vi xử lý trên thực tế 7.1 General purpose microprocessors 7.1.1 Intel 80x86 7.1.2 Xu hướng phát triển 7.2 Microcontrollers 7.2.1 Vi điều khiển của Microchip và Motorola 7.2.2 Họ vi điều khiển 8051 7.2.3 Họ vi điều khiển AVR 7.2.4 PSOC 7.2.5 Xu hướng phát triển 7.3 Digital signal processors 7.3.1 Texas Instrumentscuu duong than cong . com 7.3.2 Motorola 7.3.3 Philips 7.3.4 Xu hướng phát triển 2 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 Chương 7: Các bộ vi xử lý trên thực tế 7.1 General purpose microprocessors 7.1.1 Intel 80x86 7.1.2 Xu hướng phát triển 7.2 Microcontrollers 7.2.1 Vi điều khiển của Microchip và Motorola 7.2.2 Họ vi điều khiển 8051 7.2.3 Họ vi điều khiển AVR 7.2.4 PSOC 7.2.5 Xu hướng phát triển 7.3 Digital signal processors 7.3.1 Texas Instrumentscuu duong than cong . com 7.3.2 Motorola 7.3.3 Philips 7.3.4 Xu hướng phát triển 3 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 7.1.1 Vi xử lý của Intel cuu duong than cong . com 4 CuuDuongThanCong.comNguồn Intel https://fb.com/tailieudientucntt © DHBK 2005 7.1.1 Vi xử lý của Intel cuu duong than cong . com Nguồn Intel 5 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 7.1.1 Vi xử lý của Intel cuu duong than cong . com 6 CuuDuongThanCong.com https://fb.com/tailieudientucnttNguồn Intel © DHBK 2005 7.1.1 Vi xử lý của Intel cuu duong than cong . com 7 CuuDuongThanCong.com https://fb.com/tailieudientucnttNguồn Intel © DHBK 2005 7.1.1 Intel 4004 • First microprocessor (1971) • 4-bit processor • 2300 Transistors (P- MOS), 10 mm • 0.06 MIPS, 108 KHz, 640 bytes addressable memory • -15V power supply cuu duong than cong . com 8 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 7.1.1 Intel 8008 • First 8-bit processor (1972) • Cost $500; at this time, a 4- bit processor costed $50 • Complete system had 2 Kbyte RAM • 200 KHz clock frequency, 10 mm, 3500 TOR, 0.06 MIPS, 16 Kbyte addressable memory • 18 pin package, multiplexed address and data bus cuu duong than cong . com 9 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 7.1.1 Intel 8080 • Second gen. 8-bit processor, introduced in 1974 • 40 pin package, NMOS, 500K instructions/s, 6 mm, 2 MHz, ±5V & +12V power supply, 6 KTOR, 0.64 MIPS • 64 Kbyte address space (“as large as designers want”, EDN cuu duong than cong . com1974) 10 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 7.1.1 Intel 8088 • 16-bit processor • introduced in 1979 • 3 mm, 5 a 8 MHz, 29 KTOR, 0.33 a 0.66 MIPS, 1 Mbyte addressable memory cuu duong than cong . com 11 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 7.1.1 Intel 8086 16 bit integer CPU 16 data 20 address • Introduced: 1978 • Clock frequency: 8 - 10 MHz cuu duong than cong . com 12 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 7.1.1 Intel 80286 MMU 16 bit integer CPU 16 data 24 address • Introduced: 1983 • 1.5 mm, 134 KTOR, 0.9 to 2.6 MIPS • Clock frequency: 6 -cuu25 MHz duong than cong . com 13 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 7.1.1 Intel 80386sx MMU 32 bit integer CPU 16 data 24 address • Introduced: 1986 • 1 mm, 275 KTOR, 16 to 33 MHz, 5 to 11 MIPS • Clock frequency: 16 cuu- 25 MHz duong than cong . com • Software support and hardware protection for multitasking 14 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 7.1.1 Intel 80386dx MMU 32 bit integer CPU 32 data 32 address • Introduced: 1988 • Clock frequency: 16 - 40 MHz • Software support andcuu hardware duong protection than cong for multitasking . com 15 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 7.1.1 Intel 80486dx 8 Kbyte cache 32 bit integer CPU 32 data MMU 64 bit FPU 32 address • Introduced: 1989 • Clock frequency: 25 - 50 MHz • Software support andcuu hardware duong protection than cong for multitasking . com • Support for parallel processing • Cache required: external memory is not fast enough 16 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 7.1.1 Intel 80486sx 8 Kbyte cache 32 bit integer CPU 32 data MMU 32 address • Introduced: 1989 • 0.8 mm, 1.2 MTOR, 20 to 41 MIPS • Clock frequency: 25 cuu- 50 MHz duong than cong . com • Software support and hardware protection for multitasking • Support for parallel processing • Cache required: external memory is not fast enough 17 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 7.1.1 Intel 80486dx2 8 Kbyte cache 32 bit integer CPU 32 data MMU 64 bit FPU 32 address • Introduced: 1992 • Clock frequency: internal: 50 - 66 MHz, external: 25 - 33 MHz • Software support andcuu hardware duong protection than cong for multitasking . com • Support for parallel processing • Cache required: external memory is not fast enough 18 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 7.1.1 Intel Pentium 8 Kbyte 32 bit integer 64 program cache pipelined CPU data 8 Kbyte 32 bit integer 32 data cache pipelined CPU address Static branch 64 bit FPU prediction unit MMU • Introduced: 1993 • (.8 mm, 3.1 MTOR) up to (.35 mm, 4.5 MTOR incl. MMX) • Clock frequency: internal:cuu duong 60 - 166 MHz,than external: cong . 66com MHz • Support for parallel processing: cache coherence protocol • Super scalar 19 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 7.1.1 Intel Pentium Pro 8 Kbyte L1 32 bit integer 64+ECC program cache pipelined CPU data 8 Kbyte L1 32 bit integer 36 data cache pipelined CPU address Dynamic branch 32 bit integer prediction unit pipelined CPU 64 bit MMU pipelined FPU to L2 cache Instruction Address dispatch unit generation unit • Introduced: 1995, 0.35 mm, 3.3 V, 5.5 MTOR, 35W, 387 pin • Clock frequency: 150 - 200 MHz Internal, 60 - >100 MHz External • Super scalar (4 Instr./cycle),cuu duong super pipelinedthan cong (12 stages). com • Support for symmetrical multiprocessing (4 CPU) • MCM: 256-1024 Kbyte L2 4-way set associative cache 20 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 7.1.1 Intel Pentium II 16 Kbyte L1 32 bit integer 64+ECC program cache pipelined CPU data 16 Kbyte L1 32 bit integer 36 data cache pipelined CPU address Dynamic branch 64 bit prediction unit pipelined FPU 64 bit ECC MMU pipelined FPU to L2 cache Instruction Address dispatch unit generation unit • Introduced: 1997, 0.25 mm, 2.0 V, 9 MTOR, 43 W, 242 pin • Clock frequency: 200 - 550 MHz Internal, 100 - 225 MHz L2 cache, 66 - 100 MHz External cuu duong than cong . com • Super scalar (4 Instr./cycle), super pipelined (12 stages) • Support for symmetrical multiprocessing (8 CPU) • Single Edge Contact Cartridge with Thermal Sensor: 256-1024 Kbyte L2 4-way set associative cache 21 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 7.1.1 Intel Pentium III 16 Kbyte L1 program cache 16 Kbyte L1 32 bit integer 64+ECC data cache pipelined CPU data 256 Kbyte L2 unified 32 bit integer 36 cache pipelined CPU address Dynamic branch 64 bit prediction unit pipelined FPU 64 bit MMU pipelined FPU Instruction Address dispatch unit generation unit • Introduced: 1999, 0.18 mm , 6LM, 1.8 V, 28 MTOR, 370 pin • Clock frequency: 450 - 1130 MHz Internal, 100-133 MHz External • Super scalar (4 Instr./cycle),cuu duong super pipelinedthan cong (12 stages). com • Support for symmetrical multiprocessing (2 CPU) 22 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 7.1.1 Intel Pentium IV 16 Kbyte L1 program cache 16 Kbyte L1 32 bit integer 64+ECC data cache pipelined CPU data 32 bit integer 256/512/1024 Kbyte L2 36 pipelined CPU address Dynamic branch 64 bit prediction unit pipelined FPU 64 bit MMU pipelined FPU Instruction Address dispatch unit generation unit • Introduced: 2002, 0.13 mm or 90nm , 1.8 V, 55 MTOR • Clock frequency: 1,4 to 3.8 GHz Internal, 400 to 800 MHz External • Super scalar (4 Instr./cycle),cuu duong super pipelinedthan cong (12 stages). com • Newer versions: Hyper threading, 3.8 MHz 23 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 7.1.1 Intel Pentium IV • Available at 3.80F GHz, 3.60F GHz, 3.40F GHz and 3.20F GHz • • Supports Hyper-Threading Technology1 (HT Technology) for all frequencies with 800 MHz front side bus (FSB) • • Supports Intel® Extended Memory 64Technology2 (Intel® EM64T) • Supports Execute Disable Bit capability • Binary compatible with applications running on previous members of the Intel microprocessor line • Intel NetBurst® microarchitecture • FSB frequency at 800 MHz • Hyper-Pipelined Technology • Advance Dynamic Execution • Very deep out-of-ordercuu execution duong than cong . com • Enhanced branch prediction • 775-land Package 24 CuuDuongThanCong.com https://fb.com/tailieudientucntt © DHBK 2005 7.1.1 Intel Pentium IV • 16-KB Level 1 data cache • 1-MB Advanced Transfer Cache (on-die, fullspeed Level 2 (L2) cache) with 8-way associativity and Error Correcting Code (ECC) • 144 Streaming SIMD Extensions 2 (SSE2) instructions • 13 Streaming SIMD Extensions 3 (SSE3) instructions • Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance • Power Management capabilities • System Management mode • Multiple low-power states • 8-way cache associativity provides improved cache hit rate on load/store operations cuu duong than cong .
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