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Intel Technology Journal
Intel® Technology Journal | Volume 14, Issue 1, 2010 Intel Technology Journal Publisher Managing Editor Content Architect Richard Bowles Andrew Binstock Herman D’Hooge Esther Baldwin Program Manager Technical Editor Technical Illustrators Stuart Douglas Marian Lacey InfoPros Technical and Strategic Reviewers Maria Bezaitis Ashley McCorkle Xing Su John Gustafson Milan Milenkovic Rahul Sukthankar Horst Haussecker David O‘Hallaron Allison Woodruff Badarinah Kommandur Trevor Pering Jianping Zhou Anthony LaMarca Matthai Philipose Scott Mainwaring Uttam Sengupta Intel® Technology Journal | 1 Intel® Technology Journal | Volume 14, Issue 1, 2010 Intel Technology Journal Copyright © 2010 Intel Corporation. All rights reserved. ISBN 978-1-934053-28-7, ISSN 1535-864X Intel Technology Journal Volume 14, Issue 1 No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except as permitted under Sections 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 750-4744. Requests to the Publisher for permission should be addressed to the Publisher, Intel Press, Intel Corporation, 2111 NE 25th Avenue, JF3-330, Hillsboro, OR 97124-5961. E mail: [email protected]. This publication is designed to provide accurate and authoritative information in regard to the subject matter covered. It is sold with the understanding that the publisher is not engaged in professional services. If professional advice or other expert assistance is required, the services of a competent professional person should be sought. -
Trends in Electrical Efficiency in Computer Performance
ASSESSING TRENDS IN THE ELECTRICAL EFFICIENCY OF COMPUTATION OVER TIME Jonathan G. Koomey*, Stephen Berard†, Marla Sanchez††, Henry Wong** * Lawrence Berkeley National Laboratory and Stanford University †Microsoft Corporation ††Lawrence Berkeley National Laboratory **Intel Corporation Contact: [email protected], http://www.koomey.com Final report to Microsoft Corporation and Intel Corporation Submitted to IEEE Annals of the History of Computing: August 5, 2009 Released on the web: August 17, 2009 EXECUTIVE SUMMARY Information technology (IT) has captured the popular imagination, in part because of the tangible benefits IT brings, but also because the underlying technological trends proceed at easily measurable, remarkably predictable, and unusually rapid rates. The number of transistors on a chip has doubled more or less every two years for decades, a trend that is popularly (but often imprecisely) encapsulated as “Moore’s law”. This article explores the relationship between the performance of computers and the electricity needed to deliver that performance. As shown in Figure ES-1, computations per kWh grew about as fast as performance for desktop computers starting in 1981, doubling every 1.5 years, a pace of change in computational efficiency comparable to that from 1946 to the present. Computations per kWh grew even more rapidly during the vacuum tube computing era and during the transition from tubes to transistors but more slowly during the era of discrete transistors. As expected, the transition from tubes to transistors shows a large jump in computations per kWh. In 1985, the physicist Richard Feynman identified a factor of one hundred billion (1011) possible theoretical improvement in the electricity used per computation. -
Sperry Rand's Third-Generation Computers 1964–1980
Sperry Rand’s Third-Generation Computers 1964–1980 George T. Gray and Ronald Q. Smith The change from transistors to integrated circuits in the mid-1960s marked the beginning of third-generation computers. A late entrant (1962) in the general-purpose, transistor computer market, Sperry Rand Corporation moved quickly to produce computers using ICs. The Univac 1108’s success (1965) reversed the company’s declining fortunes in the large-scale arena, while the 9000 series upheld its market share in smaller computers. Sperry Rand failed to develop a successful minicomputer and, faced with IBM’s dominant market position by the end of the 1970s, struggled to maintain its position in the computer industry. A latecomer to the general-purpose, transistor would be suitable for all types of processing. computer market, Sperry Rand first shipped its With its top management having accepted the large-scale Univac 1107 and Univac III comput- recommendation, IBM began work on the ers to customers in the second half of 1962, System/360, so named because of the intention more than two years later than such key com- to cover the full range of computing tasks. petitors as IBM and Control Data. While this The IBM 360 did not rely exclusively on lateness enabled Sperry Rand to produce rela- integrated circuitry but instead employed a tively sophisticated products in the 1107 and combination of separate transistors and chips, III, it also meant that they did not attain signif- called Solid Logic Technology (SLT). IBM made icant market shares. Fortunately, Sperry’s mili- a big event of the System/360 announcement tary computers and the smaller Univac 1004, on 7 April 1964, holding press conferences in 1005, and 1050 computers developed early in 62 US cities and 14 foreign countries. -
Sperry Corporation, UNIVAC Division Photographs and Audiovisual Materials 1985.261
Sperry Corporation, UNIVAC Division photographs and audiovisual materials 1985.261 This finding aid was produced using ArchivesSpace on September 14, 2021. Description is written in: English. Describing Archives: A Content Standard Audiovisual Collections PO Box 3630 Wilmington, Delaware 19807 [email protected] URL: http://www.hagley.org/library Sperry Corporation, UNIVAC Division photographs and audiovisual materials 1985.261 Table of Contents Summary Information .................................................................................................................................... 3 Historical Note ............................................................................................................................................... 4 Scope and Content ......................................................................................................................................... 5 Arrangement ................................................................................................................................................... 6 Administrative Information ............................................................................................................................ 6 Related Materials ........................................................................................................................................... 7 Controlled Access Headings .......................................................................................................................... 8 Bibliography -
Prozessorenliste
Fach Bezeichnung Stepping Taktfrequenz Anmerkung 1A Intel C4001 7347 0,74 MHz ROM Intel P4002-1 0488D RAM Intel D4002-2 X1191128 RAM Intel P4003 F8956 Shift Register Intel P4004 5199W Prozessor Intel P1101A 7485 MOS SRAM 1B Intel D8008 I1220098 Intel P4040 5869W 1C Intel D3001 I3320035 Intel D3002 I3370036 1D Intel P8259A-2 L8360894 10 MHz PIC Intel P8254-2 L0421586 10 MHz PIT 1E Intel P8080A 2194B 2 MHz Intel P8086-2 L4151756B 5 MHz 1F Intel P8088 L5500345 5 MHz Intel C8087 L5380043 Math. CP 1G Intel P8031 L61100346 12 MHz Intel P8085 L5500055 3 MHz 1H Intel 8237A L0311554 5 MHz DMA Contr. Intel P8274 L7440107 MPSC Intel D8742 U2420277 12 MHz 8 Bit SMC 2A AMD N80186, N80186 91939DFE7 10 MHz, 12 MHz 335BCWD AMD 80286, Intel 80188 918KPSC L5322539 2B Intel 80286, 80286 L8500401 6, 12 MHz L9080860 2C Intel 80287 L9190444 10 MHz Math. CP 2D Intel 80286 L2140286 6 MHz Harris 80286 F3360 16MHz 2E Intel NG80386SX L1121576 16 MHz 2F Intel A82596SX SZ649 20 MHz 2G Intel 80486SX SX676 25 MHz 2H Intel A80501 SX835 60 MHz FDIV Bug 3A Intel Pentium II SL357 400 MHz Deschutes 3B Intel 80386DX SX366 33 MHz IIT 3C87 KY9220 40 MHz Math. CP 3C IT´s ST 80486DX4 100 MHz 3D UMC GREEN CPU U5S 9439K 33 MHz Not for US Sale 3E Intel 80386DX/DXL SX218 25 MHz IIT 3C87 ID9143.8 33MHz Math. CP 3F M27128AFI 88723S EPROM 3G Intel Pentium 4 SL79L 3,0 GHz Prescott Intel Pentium 4 SL6RZ 2,4 GHz Nortwood 3H Intel Celeron SL2WM 300 MHz Mendocino 4A Intel Pentium II SL357 400 MHz Deschutes 4B Intel i80960 L8373305B0 33 MHz RISC 4C Intel i80860XR SX438 40 MHz RISC 4D Intel -
Sperry Corporation, Univac Division Records 1825.I
Sperry Corporation, Univac Division records 1825.I This finding aid was produced using ArchivesSpace on September 14, 2021. Description is written in: English. Describing Archives: A Content Standard Manuscripts and Archives PO Box 3630 Wilmington, Delaware 19807 [email protected] URL: http://www.hagley.org/library Sperry Corporation, Univac Division records 1825.I Table of Contents Summary Information .................................................................................................................................... 4 Historical Note ............................................................................................................................................... 4 Scope and Content ......................................................................................................................................... 5 Administrative Information ............................................................................................................................ 7 Related Materials ........................................................................................................................................... 8 Controlled Access Headings .......................................................................................................................... 9 Appendices ..................................................................................................................................................... 9 Bibliography ................................................................................................................................................ -
Sperry Rand Third-Generation Computers
UNISYS: HISTORY: • 1873 E. Remington & Sons introduces first commercially viable typewriter. • 1886 American Arithmometer Co. founded to manufacture and sell first commercially viable adding and listing machine, invented by William Seward Burroughs. • 1905 American Arithmometer renamed Burroughs Adding Machine Co. • 1909 Remington Typewriter Co. introduces first "noiseless" typewriter. • 1910 Sperry Gyroscope Co. founded to manufacture and sell navigational equipment. • 1911 Burroughs introduces first adding-subtracting machine. • 1923 Burroughs introduces direct multiplication billing machine. • 1925 Burroughs introduces first portable adding machine, weighing 20 pounds. Remington Typewriter introduces America's first electric typewriter. • 1927 Remington Typewriter and Rand Kardex merge to form Remington Rand. • 1928 Burroughs ships its one millionth adding machine. • 1930 Working closely with Lt. James Doolittle, Sperry Gyroscope engineers developed the artificial horizon and the aircraft directional gyro – which quickly found their way aboard airmail planes and the aircraft of the fledgling commercial airlines. TWA was the first commercial buyer of these two products. • 1933 Sperry Corp. formed. • 1946 ENIAC, the world's first large-scale, general-purpose digital computer, developed at the University of Pennsylvania by J. Presper Eckert and John Mauchly. • 1949 Remington Rand produces 409, the worlds first business computer. The 409 was later sold as the Univac 60 and 120 and was the first computer used by the Internal Revenue Service and the first computer installed in Japan. • 1950 Remington Rand acquires Eckert-Mauchly Computer Corp. 1951 Remington Rand delivers UNIVAC computer to the U.S. Census Bureau. • 1952 UNIVAC makes history by predicting the election of Dwight D. Eisenhower as U.S. president before polls close. -
R00456--FM Getting up to Speed
GETTING UP TO SPEED THE FUTURE OF SUPERCOMPUTING Susan L. Graham, Marc Snir, and Cynthia A. Patterson, Editors Committee on the Future of Supercomputing Computer Science and Telecommunications Board Division on Engineering and Physical Sciences THE NATIONAL ACADEMIES PRESS Washington, D.C. www.nap.edu THE NATIONAL ACADEMIES PRESS 500 Fifth Street, N.W. Washington, DC 20001 NOTICE: The project that is the subject of this report was approved by the Gov- erning Board of the National Research Council, whose members are drawn from the councils of the National Academy of Sciences, the National Academy of Engi- neering, and the Institute of Medicine. The members of the committee responsible for the report were chosen for their special competences and with regard for ap- propriate balance. Support for this project was provided by the Department of Energy under Spon- sor Award No. DE-AT01-03NA00106. Any opinions, findings, conclusions, or recommendations expressed in this publication are those of the authors and do not necessarily reflect the views of the organizations that provided support for the project. International Standard Book Number 0-309-09502-6 (Book) International Standard Book Number 0-309-54679-6 (PDF) Library of Congress Catalog Card Number 2004118086 Cover designed by Jennifer Bishop. Cover images (clockwise from top right, front to back) 1. Exploding star. Scientific Discovery through Advanced Computing (SciDAC) Center for Supernova Research, U.S. Department of Energy, Office of Science. 2. Hurricane Frances, September 5, 2004, taken by GOES-12 satellite, 1 km visible imagery. U.S. National Oceanographic and Atmospheric Administration. 3. Large-eddy simulation of a Rayleigh-Taylor instability run on the Lawrence Livermore National Laboratory MCR Linux cluster in July 2003. -
MICROPROCESSOR EVALUATIONS for SAFETY-CRITICAL, REAL-TIME February 2009 APPLICATIONS: AUTHORITY for EXPENDITURE NO
DOT/FAA/AR-08/55 Microprocessor Evaluations for Air Traffic Organization Operations Planning Safety-Critical, Real-Time Office of Aviation Research and Development Applications: Authority for Washington, DC 20591 Expenditure No. 43 Phase 3 Report February 2009 Final Report This document is available to the U.S. public through the National Technical Information Services (NTIS), Springfield, Virginia 22161. U.S. Department of Transportation Federal Aviation Administration NOTICE This document is disseminated under the sponsorship of the U.S. Department of Transportation in the interest of information exchange. The United States Government assumes no liability for the contents or use thereof. The United States Government does not endorse products or manufacturers. Trade or manufacturer's names appear herein solely because they are considered essential to the objective of this report. This document does not constitute FAA certification policy. Consult your local FAA aircraft certification office as to its use. This report is available at the Federal Aviation Administration William J. Hughes Technical Center’s Full-Text Technical Reports page: actlibrary.act.faa.gov in Adobe Acrobat portable document format (PDF). Technical Report Documentation Page 1. Report No. 2. Government Accession No. 3. Recipient's Catalog No. DOT/FAA/AR-08/55 4. Title and Subtitle 5. Report Date MICROPROCESSOR EVALUATIONS FOR SAFETY-CRITICAL, REAL-TIME February 2009 APPLICATIONS: AUTHORITY FOR EXPENDITURE NO. 43 PHASE 3 REPORT 6. Performing Organization Code 7. Author(s) 8. Performing Organization Report No. TAMU-CS-AVSI-72005 Rabi N. Mahapatra, Praveen Bhojwani, Jason Lee, and Yoonjin Kim 9. Performing Organization Name and Address 10. Work Unit No. -
Osnovi Računarstva
OSNOVI RAČUNARSTVA - laboratorijske vježbe - Literatura: Scott Mueller, Nadogradnja i popravka PC-ja 1 Preteče savremenih računara Abakus – nalik današnjoj računaljki – naprava koja ima pokretne djelove – pokretni djelovi nisu međusobno povezani – sve operacije izvodi sam korisnik 2 Preteče savremenih računara Kalkulatori: Prva mašina za računanje - 1623. godine, Vilhelm Šikard (Wilhelm Schickard), Njemačka Paskalina: Blez Paskal (Blaise Pascal) – 1642. počeo da konstruiše prvu računsku mašinu koja je mogla da sabira i oduzima Mašina je završena poslije tri godine rada i dobila je ime Paskalina Do 1652. je proizvedeno pedeset mašina Korisnici su upotrebu smatrali komplikovanom, pa je proizvodnja obustavljena 3 Preteče savremenih računara 1820. godine, Čarls Havijer Tomas (Charles Xavier Thomas) je napravio prvi mehanički kalkulator Kalkulator je mogao da sabira, oduzima, množi i dijeli 4 Preteče savremenih računara ANALITIČKA MAŠINA: Engleski matematičar Čarls Bebidž (Charles Babbage) automatizovao je proces dugačkih računanja Napravio je prvi automatski mehanički digitalni računar, tj. računar koji radi na osnovu programa (1822. god.) Podaci su se unosili pomoću bušenih kartica Trebalo je da mašina ima mogućnost da radi sa pedesetocifrenim brojevima i da ima kapacitet memorije za 1000 takvih 5 brojeva Elektronski računari 4 generacije Prva generacija: izrađeni od elektronskih cijevi bez tastature, monitora i memorije velikih dimenzija, spori, skupi 6 ENIAC “ENIAC” (Electronic Numerical Integrator and Computer ) – 1946. god. prvi uspješan elektronski računar opšte namjene 30 tona 18.000 elektronskih cijevi Imao je sposobnost da proračuna 100.000 kalkulacija u jednoj sekundi. 7 EDVAC Ova mašina je trebalo da ima samo desetinu komponenata od kojih je bio sastavljen ENIAC, i 100 puta veću memoriju Završen je 1949. -
Annotations of First Generation Systems Development in Sweden
Annotations of First Generation Systems Development in Sweden Janis Bubenko, Jr. Department of Computer and Systems Science, Royal Institute of Technology and Stockholm University, Forum 100, SE-16440, Kista, Sweden, [email protected] Abstract: This work presents episodes of first generation information systems development in Sweden using two particular computers, ALWAC IIIE, during the period 1957–1961, and Univac III during 1963–1964. The ALWAC IIIE at ADB Institute, Gothenburg, was used for technical as well as for administrative applications. Another episode concerns re- engineering of an inventory management application; it used the ALWAC IIIE for the Swedish Defence Material Administration in 1960. The next episode concerns the computer Univac III. A sales contract between Götaverken AB and Univac included a guarantee by Univac to transfer one of Götaverken’s punched card routines to a magnetic tape oriented routine on Univac III. The development work was carried out on a Univac III at Kantonalbank in Bern, Switzerland. They did the work in night shifts during a period of five months. Only one Univac III was installed in Sweden. Keywords: First generation, information system development, Alwac IIIE, Univac III, Gothenburg 1. Introduction Information systems development is today a complex activity encompassing many types of activities and involving different kinds of stakeholders. It uses many different methods, techniques, and supporting tools. The development process deals with issues of many kinds such as organisational, economic, administrative, technical, social, as well as political. During the 1950-1960 decade, called the first generation of systems development, the development process was much simpler. In the 1950s, heavy emphasis was on primarily two types of activities: programming and testing. -
DEPARTMENT of COMPUTER SCIENCE Carneg=E-Iellon Un=Vers=Ty
CMU-CS-84-122 Error Detection with Memory Tags Richard H. Gumpertz Computer Science Department Carnegie-Mellon University Pittsburgh, Pennsylvania December, 1981 DEPARTMENT of COMPUTER SCIENCE Carneg=e-iellon Un=vers=ty CMU-CS-84-122 Error Detection with Memory Tags Richard H. Gumpertz Computer Science Department Carnegie-Mellon University Pittsburgh, Pennsylvania December, 1981 Submitted to Carnegie-Mellon University in partial fulfillment of the requirements for the degree of Doctor of Philosophy. Copyright © 1981 Richard H. Gumpertz This research was sponsored by the Defense Advanced Research Projects Agency (DOD), ARPA Order No. 3597, monitored by the Air Force Avionics Laboratory tinder Contract F33615-78-C-1551. The views and conclusions contained in this document are those of the author and should not be interpreted as representing the official policies, either expressed or implied, of the Defense Advanced Research Projects Agency, the United States Government, or Carnegie-Mellon University. Richard H. Gumpertz i Error I)ctection with Memory Tags Abstract The ability to achieve and maintain system reliability is an important problem that has become more critical as the use of computers has become more common. Fundamental to improved reliability is the ability to detect errors promptly, before their effects can be propagated. This dissertation proposes methods for using storage tags to detect a broad class of hardware and software errors that might otherwise go undetected. Moreover, the suggested schemes require minimal extensions to the hardware of typical computers. In fact, it is shown that in many situations tags can be added to words of storage without using any extra bits at all.