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Intel® Server Board S5500BC Intel® Server Board S5500BC Technical Product Specification Intel order number: E42249-009 Revision 1.8 June 2011 Enterprise Platforms and Services Division – Marketing Revision History Intel® Server Board S5500BC TPS Revision History Date Revision Modifications Number January 2009 1.0 Initial Release. February, 2009 1.1 Replaced RRL MIC Mark with RRL KCC Mark Removed lock step description from BIOS RAS April, 2009 1.2 Updated Table ―POST Error Beep Codes‖ according to BIOS EPS Added Chapter 5 – BIOS screen shots Updated Table ―Diagnostic LED POST Code Decoder‖ Updated section 3.2.1~3.2.3 Updated Table ―Integrated BMC Core Sensors‖ Removed ―wake from S4‖ support from section 3.11 Wake-up Control May, 2009 1.3 Modified Table ―NIC Status LED‖ Modified description of ―Serial Port Connectors‖ June, 2009 1.4 Updated section 9.2 Baseboard Power Requirements. July, 2009 1.5 Updated section 3.2.1 supported memory. November, 2009 1.6 Corrected Post Code Diagnose LED color information. March 2010 1.7 Added support for new board and Intel® Xeon® processors 5600 series June 2011 1.8 Update section 10.3.6 RRL KCC(Korea) ii Intel order number: E42249-009 Revision 1.8 Intel® Server Board S5500BC TPS Disclaimers Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Server Board S5500BC may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel Corporation server baseboards support peripheral components and contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel‘s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together. It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions. Intel Corporation can not be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits. Intel, Pentium, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation. *Other brands and names may be claimed as the property of others. Copyright © Intel Corporation 2009-2010. Revision 1.8 Intel order number: E42249-009 iii Table of Contents Intel® Server Board S5500BC TPS Table of Contents 1. Introduction .......................................................................................................................... 1 1.1 Server Board Use Disclaimer .................................................................................. 1 2. Product Overview ................................................................................................................. 2 2.1 Feature Set .............................................................................................................. 2 2.2 Server Board Layout ................................................................................................ 4 2.2.1 Server Board Connector and Component Layout .................................................... 4 2.2.2 Server Board Mechanical Drawing .......................................................................... 6 2.2.3 Intel® Light-Guided Diagnostic LED Locations ....................................................... 13 2.2.4 External I/O Connector Locations .......................................................................... 14 3. Functional Architecture ..................................................................................................... 15 3.1 Processor Subsystem ............................................................................................ 15 3.1.1 Intel® QuickPath Interconnect (QPI) ...................................................................... 16 3.1.2 Processor Population Rules .................................................................................. 17 3.1.3 Multiple Processor Initialization ............................................................................. 19 3.1.4 Turbo Mode ........................................................................................................... 20 3.1.5 Intel® Hyper-Threading Technology (Intel® HT) ..................................................... 20 3.1.6 Enhanced Intel® SpeedStep® Technology (EIST) .................................................. 20 3.1.7 Core Multi-Processing ........................................................................................... 20 3.1.8 Independent Loading Mechanism (ILM) Back Plate Design Support .................... 21 3.2 Memory Subsystem ............................................................................................... 22 3.2.1 Supported Memory ................................................................................................ 22 3.2.2 DIMM Population Requirements ............................................................................ 26 3.2.3 Memory Upgrade Guidelines ................................................................................. 27 3.2.4 Memory RAS Features .......................................................................................... 28 3.2.5 Channel Mirroring Mode ........................................................................................ 29 3.2.6 Demand and Patrol Scrub ..................................................................................... 29 3.3 Intel® I/O Hub (IOH) 5500 chipset .......................................................................... 29 3.3.1 PCI Express* Gen 2 ............................................................................................... 30 3.3.2 Enterprise South Bridge Interface (ESI) Features ................................................. 30 3.3.3 Controller Link (M-Link) ......................................................................................... 30 3.3.4 Management Engine (ME) ..................................................................................... 30 iv Intel order number: E42249-009 Revision 1.8 Intel® Server Board S5500BC TPS Table of Contents 3.3.5 Intel® Virtualization Technology for Directed I/O (Intel® VT-d) (rev. 2) ................... 32 3.4 Intel® 82801Jx I/O Controller Hub (ICH10R) .......................................................... 33 3.4.1 PCI and PCI Express* Interfaces ........................................................................... 33 3.4.2 Serial ATA II Interface ............................................................................................ 33 3.4.3 Software RAID Support ......................................................................................... 34 3.4.4 Low Pin Count Interface (LPC) .............................................................................. 34 3.4.5 Serial Bus (USB) Controller ................................................................................... 34 3.4.6 Serial Peripheral Interface (SPI) ............................................................................ 35 3.4.7 General Purpose Input/Output (GPIO) .................................................................. 35 3.4.8 Enhanced Power Management ............................................................................. 35 3.4.9 System Management Interface .............................................................................. 35 3.4.10 Real Time Clock (RTC) .......................................................................................... 35 3.4.11 Manageability ......................................................................................................... 36 3.4.12 Unsupported Intel® ICH10R Interfaces .................................................................. 36 3.5 Network Interface Controller (NIC) ........................................................................ 36 3.5.1 Intel® 82574L GbE PCI-E Network Controller ........................................................ 37 3.5.2 Intel® 82567 Gigabit Network Connection Physical Layer Transceiver (PHY) ....... 38 3.5.3 MAC Address Definition ......................................................................................... 38 3.6 Integrated Baseboard Management Controller ...................................................... 38 3.6.1
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