A Simple Picosecond Pulse Generator Based on a Pair of Step Recovery Diodes Lianfeng Zou, Shulabh Gupta, Christophe Caloz

1 A Simple Picosecond Pulse Generator Based on a Pair of Step Recovery Diodes Lianfeng Zou, Shulabh Gupta, Christophe Caloz Abstract—A picosecond pulse generator based on a pair of storage phase, the junction maintains low resistance, and step recovery diodes (SRD), leveraging the transient response almost constant junction voltage, i.e. vj VT. Near the end of the SRD PN junction and controlling the pulse width by a of the storage phase, the raising junction« barrier increases the resistor, is proposed. We first explain the operation principle resistance, finally switching off the junction for a decay time τ2 of the device, decomposing the pulse generation into different (decay phase), which is extremely short (in picosecond range) phases, and then demonstrate an experimental prototype with for an SRD [8]. Assuming constant and constant , two different resistance, and hence pulse width, values. iF iR,transient the storage phase time is given by [8] Keywords—UWB pulse generator, real-time analog signal processing (R-ASP), step recovery diode (SRD) iF τ τL ln 1 ; (1) 1 “ ` i ˆ R,tran ˙ I. INTRODUCTION where τL is the minority carrier lifetime. We shall next present The emerging Real-time Analog Signal Processing (R-ASP) our pulse generator based on this SRD transient physics. technology [1], using dispersion-engineered structures (analog signal processors) providing specified group delays versus storage τ1 decay τ2 frequency responses for processing high-frequency and wide- bandwidth signals in real time, may lead to novel low-cost and low-complexity radio systems [2] for future millimeter wave v Votalges ( and terahertz wireless communications. vi i o Analog signal processors usually deal with ultra-short pulses iF with very rich spectral contents. Such pulses may be generated vi RL ) VT i by different techniques [3]. Among them, the step recovery v i diode (SRD) approach [4]–[6] features simple circuit design, vj vo vi , 0 “ ´ 0 v while providing picosecond pulse generation capability. Con- j i “ ventional SRD-based pulse generators usually employ an SRD R,steady v Current ( to generate a pulse with picosecond rising edge, which de- i o structively interferes with its opposite-polarity delayed replica ´ v i produced by a short-circuited stub, which results in a short ) pulse whose width is equal to the round trip time along the i stub. However, the stub configuration suffers from spurious R,transient reflections in both forward and backward directions, whose 0 τ τ τ suppression requires pulse shaping networks [6], and requires 1 1 ` 2 complicated tuning schemes [7]. time In this paper, we propose a stub-less pulse generator based on a pair of SRDs, which is immune of spurious reflections Fig. 1: PN junction transient current i (solid blue) and junction and which provides flexible control of the pulse width via a voltage vj (dash red) in response to a step voltage vi (dot red) simple resistance. from the forward to the reverse bias regimes. II. PRINCIPLE Figure 2 shows the schematic of the proposed SRD-pair The transient behaviour of a PN junction in response to a pulse generator. The generator is triggered by the rising edge step voltage from the forward to the reverse bias regimes is of the input voltage through PIN diode D1, that is always shown in Fig. 1. Initially, the PN junction is forward biased ON for blocking possible negative input voltages. Its core is arXiv:1610.07115v1 [physics.ins-det] 23 Oct 2016 with current iF. When the voltage vi reverses polarity, the the parallel connection of SRDs D2 and D3, biased at their junction is not switched off immediately, but rather takes cathode by DC Vs 0 through R1 current limiter, with R2 time τ1 (storage phase), with current iR,transient, to neutralize controlling the pulseă width, as will be shown later. Finally, the charges stored in the depletion region and progressively Schottky diode D4, operates as a pulse formation switch. The raise the junction barrier [8]. Note that during the whole resistor R 50 Ω ensures input matching during the pulse 0 “ L. Zou ([email protected]) and C. Caloz are with Polytechnique production. Assuming square-wave (0-2.5 V) excitation v1, the Montreal,´ Montreal,´ Quebec,´ Canada. operation may be decomposed into 5 phases, shown in Fig. 3. S. Gupta is with Carleton University, Ottawa, Ontario, Canada. Phase 1 (t t ): D2 and D3 are forward biased, and ‚ ă 1 2 DC Vs 0 ă TABLE I: Diodes used in the generator with reference R1 to Fig. 2. D1 D3 D4 v1 v2 v3 v4 Notation Model i iD3 iL D2 t D1 Avago Tech. HMPS-2822 R0 D2 R2 RL D2 Aeroflex MMDB30-0805 D3 Aeroflex MMDB30-0805 D4 Skyworks SMS7630-061-0201 pulse generator Fig. 2: Proposed SRD-pair pulse generator. R2 from the ground to node 3, so that D4 is off and v4 0. Phase 2 (t t t ): D2 is in storage regime,“ D3 ‚ 1 ă ă 2 is still forward biased, and D4 is still off. The excitation v1 t1 t2 t3 t4 40 200 starts rising, driving D2 (iR,D2 0) into storage regime before D3 due to the smaller resistance¡ in the D2 current loop than iD2 30 150 that in the D3 one and hence faster current changing rate iD3 ( iD2 t iD3 t) in response to the rising edge of v . B {B ¡B {B 1 iL According to Fig. 1, vj,D2 v varies only slightly in storage 20 100 “ ´ 2 regime, and v3 0 because D3 is still forward biased, and hence keeping D4ă off. 10 50 Phase 3 (t t t ): D2 and D3 are both in storage ‚ 2 ă ă 3 Current (mA) regime, D4 is still off. The voltage v1 eventually also drives D3 0 0 into storage regime (iR,D3 0). Since iF,D2 iR,D2 iF,D3 iR,D3, ¡ { ! { we have τ ;D2 τ ;D3 according to (1), and therefore D2 will 1 ă 1 −10 −50 switch off before D3. In the meanwhile, v3 follows v2, with -1.5 -1 -0.5 0 0.5 1 1.5 insufficient variation to switch D4 on. time (ns) Phase 4 (t t t ): D2 is off, D3 is still in storage ‚ 3 ă ă 4 (a) regime, D4 is on. The SRD D2 abruptly switches off at t3, while D3 remains in storage regime. Consequently, v2, t t t t and following v3, abruptly increase, which switches D4 on, 3 1 2 3 4 and therefore generates at the output the rising edge of v4. v1 Moreover, the off-switching of D2, and the on-switching of D4, v2 which makes RL parallel to R2, together boost iR,D3, starting to 2 v3 shorten the D3 storage time, which would otherwise be longer v4 as expected in Phase 3. Phase 5 (t t ): D2, D3, D4 are all off. The D3 storage 1 ‚ ¡ 4 phase suddenly ends at t4, nullifying iR,D3 and v3, and hence switching D4 off, which results in the falling edge of v4. Voltage (V) 0 When the input level goes back to zero, the generator returns to the regime of Phase 1, waiting for the next voltage step to resume the aforementioned pulse formation cycle. −1 Let us now examine the factors determining the pulse width. -1.5 -1 -0.5 0 0.5 1 1.5 Equation (1) assumes constant iR,transient over the entire storage iL time (ns) phase τ1. As explained above, the storage phase for D3 is from (b) t2 to t4. However, since iR,D3 t2 t t3 iR,D3 t3 t t , the storage time essentiallyp reducesă ă to theq ! intervalp tă; t ă, 4q r 3 4s Fig. 3: Circuit simulated (a) currents (polarities referred to and iR,transient in (1) should be replaced by iR,D3 t3 t p ă ă current directions indicated in Fig. 2) and (b) voltages, with t4 for the effective storage time of D3. Since this interval q V 3:5 V, R 25 Ω , R 50 Ω, and Spice models for ( t3; t4 ) corresponds to the pulse duration, this duration can s 1 2 r s the“ diodes ´ in Table.“ I. “ be approximated as iF,D3 T τL ln 1 : (2) « ` iR,D3 t t t „ p 3 ă ă 4q D4 is off. The excitation v is close to 0 V, so the D2 and D3 with an accuracy that is proportional to iR,D3 t t t and 1 p 2 ă ă 3q forward currents are such that iF,D2 iF,D3 due to the existence hence inversely proportional to R , i.e. the closer iR,D3 to zero " 2 of R in the D3 loop. The junction voltages vj,D2 v and in the interval t ; t (associated with larger R ), the better 2 “ ´ 2 r 2 3s 2 vj,D3 v v , where v 0 due to the current flowing in the accuracy, as will be shown later in Fig. 4(a). Using Ohm “ 3 ´ 2 3 ă 3 to DC law, one may further write (2) in the form Vs R2 RL RL T τL ln 1 r || τL ln 1 r ; (3) R1 « ` R “ ` R RL ˆ 2 ˙ ˆ 2 ` ˙ where r is the ratio of v3 in the forward bias regime to v3 in D1 D3 D4 the t ; t interval. Equation (3) reveals that, for given RL, one r 3 4s may adjust R2 to control the pulse width. This is confirmed by the simulation result in Fig. 4(a), which also show the result D2 for the approximation in (2).

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