Nonlinear Modeling of Step Recovery Diodes Using Verilog-A

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www.agilent.com/ﬁ nd/eesof Eagleware App Note 22

describes the terminal behavior of the device. In many cases the temperature and parasitic dependencies are also modeled and a table of parameters is established, enabling users of the model to enter additional parametric characteristics. Once the text file is complete, the file is stored in the “My Models” directory with a va name extension. When GENESYS is started, any va files are automatically compiled and linked into the GENESYS engine. The new model can then be used in the same manner as any other model in the design environment.

Introduction Modeling a Step Recovery Diode The Advanced Modeling Kit (AMK) in GENESYS contains an innovative Verilog-A A model of a step recovery diode was compiler. This nonlinear modeling tool enables implemented to illustrate the use of the AMK. both the semiconductor modeling industry and The step recovery diode (SRD), or “snap diode,” design engineers to create and implement new has an unusual operating characteristic whenever complex linear and non-linear models that cover forward biased charge is stored in the depletion a wide range of behavioral characteristics. region. During the reverse cycle, when the stored charge is removed, the conduction abruptly halts. Verilog-A Compiler This abrupt halt explains the diode’s name: “snap diode”. The abrupt current change is Based on the IEEE Verilog-A standard, utilized to produce sampling devices and extensive libraries of functions and an intuitive frequency multipliers. language help modelers and design engineers develop and deploy new functionality in To develop the SRD model we start with the minimum time. Illustrating the flexibility and Verilog-A description of a SPICE-like non-linear utility available with the AMK, GENESYS diode. From this starting point we add offers VBIC, HiSIM, MEXTRAM and other parameters describing the diode’s capacitance, models in Verilog-A source code and compiled lead inductance, reverse recovery time, series models. Verilog-A source code is easier to read, resistance and other diode parameters. Next, the requires less lines of code, and - after section that describes the capacitance/charge compilation - runs nearly as fast as a model characteristics is modified to mimic the charge written in C-code. The AMK does not limit the characteristics vs. voltage of a step recovery designer to pre-established models, although new diode (See Appendix). When completed, the file models or features can be developed by using an is saved in the ‘My Models’ directory and when existing model as a foundation. With the AMK GENESYS is next started it automatically checks you can develop models to describe and simulate for new file revisions, compiles and loads the the behavior of transistors, FETs, diodes, laser model for use. The only additional feature to add diodes, PIN receivers, non-linear magnetic is a custom symbol, if desired. The process devices and more. completed, the SRD model is now available for

simulation via the parts library manager or pull- The design procedure starts with a text editor. down menus. Either from scratch or from one of the many Verilog-A examples, a text file is developed that

 May 2004 Eagleware Corporation 1

AN-22 Nonlinear Modeling of Step Recovery Diodes Using Verilog-A

Comb Generator of L1, L2, and C1. Note that the impulse has not been totally filtered at this point. Figure 3 shows Figure 1 shows the design of a comb generator the impulse generated into the 50 ohm load. using the AMK-created model. Simulation was Pulse width is approximately 180 ps. completed with GENESYS HARBEC using 30 Output Voltage Pulse harmonics with an input frequency of 200 MHz 6 and power of +26 dBm. 5.2 2.96667 ns, 4.90684 PK 4.4 Vm 3.6 VDC= Vpuls e 2.8 C2 C=100 pF 2 1 1 7 7 3 2 (1) (2) Vpulse L2 L1 1.2 L=?22 nH L=?10 nH C3 C1 A_1 0.4 C=?40 pF C=?12 pF CR=2 pF -0.4 0 0 0 -1.2 -2 0 2 4 6 8 10 Tim e (ns) Figure 1 Figure 3

The topology in Figure 1 uses the typical series By varying parameters such as junction inductance L1 to provide the impulse shape. As capacitance, reverse recovery time, and parasitic stated previously, when the diode current inductance, different pulse shapes optimized for abruptly shuts off as a result of the forward bias the task required can be manipulated based upon charge being depleted, a voltage spike is manufacturer’s data sheets. Figure 4 illustrates a generated as a result of L di/dt. The pulse width non-optimized comb. Note that power drops by th is usually designed either to produce a rich set of only 10db up to the 15 harmonic. harmonics—such as in the comb generator example for broadband mixing, Figure 1, or shaped to enhance a particular multiple of the Power Output Comb 10 input frequency as illustrated in the X10 200 MHz, 3.50901 0 2000 MHz, -2.14682 multiplier in Figure 5. The additional lumped Po dbm components, L2 and C3, provide a match to the -10 1 source impedance at the driven frequency . -20 Node Waveforms -30 10 5 -40 Po dbm 8 Test Pt 4 -50

6 V input 3 -60

4 2 -70

2 1 -80 Test Pt Test

0 0 -90

V input V 0 1200 2400 3600 4800 6000 -2 -1 Freq (MHz)

-4 -2

-6 -3 Figure 4

-8 -4

-10 -5 0 2 4 6 8 10 Tim e (ns)

Figure 2

Figure 2 notes the voltage waveforms at the input of the comb generator and at the junction

1 Hewlett Packard Application Note 920

 May 2004 Eagleware Corporation 2 AN-22 Nonlinear Modeling of Step Recovery Diodes Using Verilog-A

10X Multiplier Example Output Waveform 1.5 To further illustrate the potential gain in using 1.2 Vout the AMK, a 10X multiplier was simulated. 0.9 Starting with the basic comb generator design, a 0.6 frequency selective output resonator, consisting 0.3

of a length of transmission line and coupling 0 Vout

capacitor, was added. Figure 5 illustrates the -0.3

final schematic configuration. -0.6

-0.9

Vm -1.2 VDC= TL1 Z=100 Ω -1.5 L=?70.41979° C2 0 2 4 6 8 10 F=2000 MHz C=?0.30003 pF 1 1 7 7 3 5 2 Tim e (ns) (1) (2) L2 L1 L=22 nH L=10 nH Figure 7 C3 C1 A_1 C=40 pF C=12 pF CR=2 pF

0 0 0 Figure 7 illustrates the ringing waveform at the 50 load. The electrical length, line impedance, and coupling capacitor all affect the shape and frequency response of the final signal. The goal Figure 5 of varying these component values is to maximize the power available in Nth comb.2 Once a final design is realized, the Advanced Finally, Figure 8 provides a look at the output T/LINE feature in GENESYS converts the spectrum centered around 2 GHz (X10 of input transmission topologies into their final form (i.e. frequency). Typically, additional filtering is microstrip) without further effort by the designer. required if the multiplier has more stringent The node voltages for the completed multiplier harmonic content requirements. This may be are shown in Figures 6 and 7. implemented with lumped or distributed filters that are dictated by the operating frequency. Fortunately GENESYS offers synthesis tools Node Waveforms 10 5 that cover the range with M/FILTER and

3.125 ns, 3.94254 8 4 FILTER.

6 3 Power Output Spectrum 10 4 2 2000 MHz, 5.06729 3 Diode Impulse 2 1 Power Output -4 0 0 -11

Input Voltage Input -2 -1 -18 -4 -2 Input Voltage -25 200 MHz, -30.64815 -6 Diode Impulse -3

Power Output -32

-8 -4 -39

-10 -5 -46 0 2 4 6 8 10 Tim e (ns) -53

-60 Figure 6 0 800 1600 2400 3200 4000 Freq (MHz) Figure 6 shows the input waveform and that of Figure 8 the impulse at the diode/transmission line node.

2 Hewlett Packard Application Note 918

 May 2004 Eagleware Corporation 3 Appendix

/* Eagleware 2003 Bill Clausen Implementation of a step recovery diode as defined by Zhang and Raissanen in "A New Model of Step Recovery Diode for CAD" MTT-S 1995 p 1459-1462 */ `include "constants.vams" `include "disciplines.vams"

`define SPICE_GMIN 1.0e-12 `define LARGE_REAL 1.0e99 `define DEFAULT_TNOM 27 module diode_srd(anode,cathode);

// %%DEVICE_CLASS=DIODE%%

inout anode, cathode; electrical anode, cathode, internal;

parameter real Area = 1.0 from (0:inf]; //Area scaling factor parameter real Is = 1e-14 from [0:inf]; //Saturation current [A] parameter real Tnom = `DEFAULT_TNOM from (-`P_CELSIUS0:inf); //Measurement temp[C] parameter real Rs = 0.0 from [0:inf]; //Ohmic res [Ohm] parameter real Rf = 0.1 from [0:inf]; // Forward biased resistance[Ohm] parameter real Tt = 0.0 from [0:inf]; //Transit time [s] parameter real Tau = 2e-9 from [0:inf]; // Reverse recovery time[s] parameter real Cr = 0.0 from [0:inf]; //Junction capacitance [F] parameter real Lpk = 1e-9 from [0:inf]; //Package Inductance [H] parameter real Cpk = 2e-12 from [0:inf]; // Package Capacitance[F] parameter real Vj = 1.0 exclude 0; //Junction potential [V] parameter real N = 1.0 from [0:inf]; //Emission coef parameter real M = 0.5 from [0:inf]; //Grading coef parameter real Eg = 1.11 from (0:inf]; //Activation energy [eV] parameter real Xti = 3.0 from [0:inf]; //IS temp exp. parameter real Kf = 0.0; //Flicker noise coef parameter real Af = 1.0 from (0:inf); //Flicker noise exponent parameter real Fc = 0.5 from [0:1]; //Forward bias junct parm parameter real Bv = 60.0 from [0:inf]; //Reverse breakdown voltage [v] parameter real Ibv = 0.001 from [0:inf];//Current at BV [A]

real Vd, Id, Qd, Cf; real f1, f2, f3, Fcp; real Ibv_calc, Vth; real Is_temp, Vth_nom, T_nom, T;

analog begin

Vth = $vt; T = $temperature;

f1 = (Vj/(1 - M))*(1 - pow((1 - Fc), 1 - M)); f2 = pow((1 - Fc), (1 + M)); f3 = 1 - Fc * (1 + M); Fcp = Fc * Vj;

Cf = Tau/Rf;

if (Ibv !=0) Ibv_calc = Ibv; else Ibv_calc = Is * Bv / Vth;

Vd = V(anode, internal);

// Temperature dependence T_nom = Tnom + `P_CELSIUS0; Vth_nom = $vt(T_nom); Is_temp = Is * pow(T/T_nom, Xti / N) * limexp(Eg / Vth_nom - Eg / Vth);

 May 2004 Eagleware Corporation 4

AN-22 Nonlinear Modeling of Step Recovery Diodes Using Verilog-A

// Intrinsic diode // BV is not adjusted to match Ibv if I(BV) <> Ibv if (Vd < 0) begin if (Vd < -Bv) // Past breakdown Id = -Area * Is_temp * (limexp(-(Bv + Vd) / Vth) + Bv / Vth); else if (Vd == -Bv) // At breakdown Id = -Area * Ibv_calc; else if (Vd <= -5 * N * Vth) // -Bv < Vd < -5 nKT/q Id = -Area * Is_temp + Vd * `SPICE_GMIN; else // -5 nKT/q <= Vd < 0 Id = Area * Is_temp * (limexp(Vd / Vth) - 1) + Vd * `SPICE_GMIN; end else // Fwd bias: Id = Area * Is_temp * (limexp(Vd / (N * Vth)) - 1) + Vd * `SPICE_GMIN;

// Capacitance (junction and diffusion) if (Vd <= 0)

Qd = Cr*Vd;

else if ((Vd > 0.0)&&(Vd < Fcp)) Qd = (Cf-Cr/2*Fcp)*pow((Vd+(Cr*Fcp)/(Cf-Cr)),2)-(Cr*Cr*Fcp)/(2*(Cf-Cr));

else Qd = Cf*Vd-(Cf-Cr)*Fcp/2;

I(anode, internal) <+ Id; V(internal, cathode) <+ I(internal, cathode) * (Rs / Area) + Lpk*ddt(Id); I(anode, internal) <+ ddt(Qd);

end endmodule

References

Additional Sources of Information

1) “A Circuit Model of the Step Recovery Diode,” K.L. Kotzebue, Proceedings of the IEEE, December, 1965, pg 2119-2120. 2) “Computer Aided Design of Step Recovery Diode Frequency Multipliers,” Jian Zhang and Antti V. Raisanen, MTT, vol 44, No.12, December, 1996, pg 2612-2616. 3) “Shunt Harmonic Generation Using Step Recovery Diodes,” Stephen Hamilton, Robert Hall, Microwave Journal, April 1967, pg 69-78. 4) “Pulse and Waveform Generation with Step Recovery Diodes,” Hewlett Packard Application Note 918. 5) “Harmonic Generation Using Step Recovery Diodes and SRD Modules,” Hewlett Packard Application Note 920. 6) “Ku-band Step Recovery Multipliers,” Hewlett Packard Application Note 928. 7) “Comb Generator Simplifies Multiplier Design,” Hewlett Packard Application Note 983.

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