Microprocessor E158 Chip Report
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Mudd ][ Microprocessor E158 Chip Report Spring 2008 Table of Contents Introduction .....................................................................................................................................................2 History.............................................................................................................................................................3 Microarchitecture ............................................................................................................................................4 External Interface ............................................................................................................................................7 Floorplan .......................................................................................................................................................10 Timing ...........................................................................................................................................................12 Design Decisions...........................................................................................................................................16 Validation......................................................................................................................................................17 Power Consumption ......................................................................................................................................18 Tapeout..........................................................................................................................................................19 Test Plan........................................................................................................................................................20 Summary .......................................................................................................................................................24 Lessons..........................................................................................................................................................24 References .....................................................................................................................................................27 Appendix: RTL Code ....................................................................................................................................27 Appendix: Test Vectors and Verilog Test Benches.......................................................................................41 Appendix: Schematics...................................................................................................................................57 Appendix: Layout........................................................................................................................................107 Appendix: Microcode Assembler................................................................................................................131 Appendix: ROM Generator .........................................................................................................................152 Appendix: vcd2sp and vcd2cmd..................................................................................................................172 Appendix: 6502 Emulator ...........................................................................................................................189 Introduction The Harvey Mudd College Spring 2008 class of E158, Introduction to CMOS VLSI Design, has designed and built the Mudd II microprocessor that is pin-compatible with the classic 6502 which inspired the first generation of personal computers. The chip supports nearly the full instruction set and is expected to be a drop-in replacement for the processor on an Apple II motherboard. Interrupts and binary-coded decimal (BCD) arithmetic are not needed or implemented. The test chip is fabricated on a MOSIS 1.5x1.5 mm TinyChip in the AMI 0.5 micron CMOS process (λ = 0.3) in a 40-pin DIP package. It was developed using the Electric CAD suite, along with ModelSim for logic verification, HSPICE for electrical and timing verification, and IRSIM for silicon test vector generation. The class wanted to build a relatively complex 8-bit CPU, and the success and history of the Apple II series computer made the MOS Technology 6502 the obvious choice. One of the objectives of the project is to achieve minimum power consumption at the required 1 MHz operating frequency. The chip uses 5 V I/Os, but a variable core voltage, and includes 14,400 transistors. Core power consumption is predicted from SPICE to be 12 mW at 5 V and 46 µW at 1.5 V. Another objective is to explore using Razor transparent latches to detect incipient timing errors before they occur. The chip produces an ERROR signal warning that the critical path is about to miss its setup time. This also facilitates lowering the core voltage until the chip is at the edge of failure. The chip was designed by: Nathaniel Pinckney – Chief of Circuit Design Thomas Barr – Chief of Microarchitecture Heather Justice – Microarchitecture Kyle Marsh – Microarchitecture Jason Squiers – Head of Schematics Eric Burkhart – Schematics Trevin Murakami – Schematics Sam Gordon – Clocking and Razor Latches Tony Evans – Clocking and Razor Latches Michael Braly – Head of Layouts Nisha George – Layouts Corey Hebert – Layouts Matt Jeffryes – ROM Generation Steve Huntzicker – I/O Professor David Harris – Instructor History The MOS Technology 6502 was one of the first low-cost, widely available microprocessor. At the same time that competing microprocessors cost over $125, the 6502 cost $25. An 8-bit design with 16-bit address space, the 6502 was a great success in the new personal computer world. The CPU quickly became the part of choice for both large manufacturers of PCs and individual hobbyists for its ease of programming, performance and cost. The processor derives from the Motorola 6800. After the engineering team for the 6800 left Motorola, they formed MOS Technology to develop their own CPU. There, they developed the 6501, an enhanced version of the 6800. It supported new addressing modes while maintaining pin-compatibility with the original CPU. After a lawsuit, the 6501 was replaced with the 6502, a version that broke pin-compatibility by reordering the pins on the CPU. Figure 1 shows a die photograph of the chip, which contains a datapath at the top, ROM or PLA at the bottom, and some random logic in the middle. Figure 1 MOS Technology 6502 die photo [http://micro.magnet.fsu.edu/chipshots/mos/6502small.html] One of the first uses of the 6502 was the Apple I. The Apple I, a single board computer, was sold at computer club meetings around the Bay Area. While it never sold in great numbers, the Apple I led into the development of the Apple II. The Apple II had many useful features for a personal computer, such as a rudimentary sound system, color graphics and a built in BASIC interpreter, but one of the most revolutionary features of the Apple II was that it was one of the first personal computers to come built into a case. The Apple II was designed to be a computing appliance, for an end user, not a development platform for an engineer, and is largely responsible for the “microcomputer revolution”. Microarchitecture The Mudd II is implemented with a multicycle datapath. The controller uses two ROMs; the opcode ROM decodes each instruction, while the state ROM sequences through the appropriate states to execute the instructions. Figure 2 shows a block diagram of the processor's controller. Figure 2 Mudd II Controller Block Diagram Much of the control is accomplished with the state ROM. The state ROM contains a base state which allows an opcode to be read from the program into the opcode ROM, producing signals that are specific to that particular instruction. Additionally, the opcode ROM specifies which state to jump to after the base state. The controller then steps through a sequence of states and, upon completion of the instruction, returns to the base state in order to retrieve the next opcode. A state can either specify the control signals for the cycle or select the function-specific control signals decoded by the opcode ROM. Branches have a special effect on the sequence of states to be followed; the controller must first determine whether the branch will be taken and then either execute additional states in order to take the branch or jump directly back to the base state in order to not branch. The opcode ROM can decode all 151 opcodes of the 6502 complex instruction set and the state ROM contains 118 states which implement every 6502 instruction except for binary coded decimal arithmetic. Figure 3 Mudd II Datapath Block Diagram Figure 3 shows a block diagram of the processor's datapath. Registers in the datapath contain the program counter (both a low byte, pc_l, and a high byte, pc_h), the processor state flags (p), and the register file values of A, X, Y, and stack pointer (all stored in regfile). Temporary registers (temp_l and temp_h) may be used for storing values within a particular sequence of states. Each cycle sends certain data through the ALU on databuses A and B as determined by the control signals. Databus A may get a constant value (specified by the controller), the data read in from memory, the value of either temporary register, or any value stored in the register file. Databus B may get either byte of