DOCSLIB.ORG

A Survey of Open Source Processors for Fpgas

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
A Survey of Open Source Processors for Fpgas A Survey of Open Source Processors for FPGAs Rui Jia, Colin Yu Lin, Zhenhong Guo and Haigang Yang System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China Corresponding Author: [email protected] Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 CONTENTS A Survey of Open Source Processors for FPGAs 01 Motivation 02 Overview of Open Source Soft Processors 03 Selection of Open Source Processors 04 Implementations and Comparisons 05 Discussions and Conclusion 1 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 FPGA-based SoCs FPGA-based SoCs have become a technology trend for reconfigurable systems. The most attractive and practical methodology for SOC designer is to select reusable components and IPs Processor should be designed, verified, tested and shared in module level. Open source soft core processor Open source hardware improves the design productivity. many open source processors are available. How to choose suitable soft processors for FPGA-based SoCs? Numerous open source processors make the selection process difficult. Differences between existing vendor-provided and open source processors？ 2 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Totally 178 processors found on OpenCores, soft microprocessor and Wikipedia 33 9 processors are not designed Planning for FPGAs->169 processors Pre-Alpha 27 considered Alpha Life cycle is categorized into 68 Beta planning, pre-alpha, alpha, 11 beta, stable, and mature Stable stages unknown 24 6 Only 68 in stable can be used conveniently, in which processor is feature-complete and has few bugs 3 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 68 stable processors: (a)License. (b)Instruction Set Architecture(ISA). (c)Compiler and assembler (d)Verification (d)Design documentation . 4 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 License The license of processors cover: GNU General Public License (GPL), GNU Lesser General Public License (LGPL) Berkeley Software Division (BSD), Creative Commons-Attribution (CC-BY). 5 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Provider ISA Number Instruction Set Architecture (ISA) ARM ARMv2 1 Lattice Semiconductor LatticeMicro32 1 DLX 1 Free Open Cores OpenRISC 3 unnamed 14 Sun Microsystems SPARCv8 1 SPARCv9 4 Atmel AVR 5 Hitachi SuperH-2 1 8080 2 8088 3 Intel 80186 1 MCS-48 1 Microchip Technology PIC-baseline family 5 MIPS I 6 MIPS Technology MIPS 16 1 MIPS 32 4 Proprietary MOS Technology 6502 3 6800 1 68000 1 Motorola 68HC05 1 68HC11 1 In the table, most of the ISAs are property of 68HC08 1 National Semiconductor COP400 1 commercial corporations. Synopsys ARC 3 Texas Instruments MSP430 1 Xilinx MicroBlaze 1 Only 35% of these ISAs are free and can be used without Zilog Z80 4 Total 68 infringements to the commercial corporations. 6 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Compiler and Assembler 38 processors have both compiler and assembler 12 processors only assembler 18 processors do not provide either 7 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Verification Design Documentation about 68% processors have Availability of design files and been verified on FPGAs. documents weigh heavy. 7 of the processors have also About 43% processors have no been verified as ASIC. design documentation. 8 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Summary Features of open source soft processors are summarized in Table below. The table consists of 68 stable soft processors under open source license 9 8 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 CONTENTS A Survey of Open Source Processors for FPGAs 01 Introduction 02 Overview of Open Source Soft Processors 03 Selection of Open Source Processors 04 Implementations and Comparisons 05 Discussions and Conclusion 10 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Selecting Method/Processtotal 68 stable ones, 47 processors under open source license are chosen. choose 36 processors with available compiler and assembler. 17 processors with free ISA are chosen. 11 processors with general ISA 3 multi-core processors processor 1are asynchronous not studied. processor is not studied. 11 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Selecting Method/Process They are Amber ,LatticeMicro32 (LM32), S1, Altor32, OpenRISC 1200 (OR1200), LEON2 and LEON3. Amber23 Amber25 LM32 S1 Altor32 OR1200 LEON2 LEON3 Bit-width 32 32 32 64 32 32 32 32 Pipeline Depth 3 5 6 6 5 5 5 7 n o i x Multiplier √ √ Optional,√(d) √ √ √ √ t √ e t l a i t p n u Divider N/A N/A Optional,√(d) N/A N/A m √ √ √ p U o m C o FPU N/A N/A N/A √ N/A N/A √ √ C Register 15 15 32 640 32 32 40-520, 136(d) 40-520,136(d) e 0,1,2,4(d),8 16(d) r Total Size/Kbytes 8(d),12,16,32 16,24,32(d) 32(d) 16(d) 8(d) 0.008(d)-64 u t c e Instruction Cache/Kbytes 8,12,16(d),32 0,1,2(d),4,8 16(d) 8(d) 8(d) 4(d) 0.004(d)-32 t i 8(d),12,16,32 h c Data Cache/Kbytes 8,12,16(d),32 0,1,2(d),4,8 16(d) 8(d) 8(d) 4(d) 0.004(d)-32 r A e r Sets 256(d) 256(d) 128,256,512(d),... 128(d) 256(d) 512(d) 1(d)-256 h 128(d) o c s s a e C Associativity/Ways 2(d),3,4 or 8 2,3,4(d) or 8 1(d),2 4(d) 1(d) 1(d) 1(d)-4 c 1(d)-4 o r P Byte-per-line/Bytes 16 16 4(d),8,16 32(d) 32 16(d) 32(d) 4(d)-8 Write policy Write through Write through Write through Write through Write through Write through Write through Write through Replacement policy Read- miss Read- miss Read- miss LRU Read- miss LRU LRU,LRR,Random(d) LRU,LRR,Random Shared/Separate TLB N/A N/A N/A Separate N/A Separate N/A(d),Optional N/A(d),Optional U No. of Instruction TLB entries N/A N/A N/A 64 N/A 16,32,64(d),128 2-32,N/A(d) 2-32 M M No. of Data TLB entries N/A N/A N/A 64 N/A 16,32,64(d),128 2-32,N/A(d) 2-32 No. of Shared TLB entries N/A N/A N/A N/A N/A N/A 2-32,N/A(d) 2-32 Wishbone Wishbone Interface Wishbone Wishbone Wishbone Wishbone Wishbone Amba /Amba /Amba 12 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 CONTENTS A Survey of Open Source Processors for FPGAs 01 Introduction 02 Overview of Open Source Soft Processors 03 Selection of Open Source Processors 04 Implementations and Comparisons 05 Discussions and Conclusion 13 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Processor Descriptions Features of selected commercial processors Altera Xilinx Nios II/e Nios II/s Nios II/f MicroBlaze/single MicroBlaze/dual Bit-width 32 32 32 32 32 Pipeline Depth N/A 5 6 3/5(d) 3/5(d) n o i x Multiplier N/A Optional,N/A(d) Optional,√(d) Optional,√(d) Optional,√(d) t e t l a i t p n u Divider N/A Optional,N/A(d) Optional,√(d) Optional,N/A(d) Optional,N/A(d) m p U o m C o FPU N/A N/A N/A Optional,N/A(d) Optional,N/A(d) C Register 32 32 32 32 32 e Total Size/Kbytes N/A 2(d),4,... 4(d),8,... 16,32,N/A(d) 16,32,N/A(d) r u t c e Instruction Cache/KBytes N/A 2(d),4 2(d),4,... 8,16,N/A(d) 8,16,N/A(d) t i h c Data Cache/KBytes N/A N/A 2(d),4,... 8,16,N/A(d) 8,16,N/A(d) r A e r Sets N/A 64(d),128 64(d),128,... 512 512 h o c s s a e C Associativity/Ways N/A 1(d) 1(d) 1 1 c o r P Byte-per-line/Bytes N/A 32(d) 4,16,32(d),... 16(d),32 16(d),32 Write policy N/A N/A Write through Write through(d),Write Back Write through(d),Write Back Replacement policy N/A unkown unkown unkown unkown Shared/Separate TLB N/A N/A Shared+Separate Separate+Shared Separate+Shared U No. of Instruction TLB entries N/A N/A 6(d) Optional,N/A(d) Optional,N/A(d) M M No. of Data TLB entries N/A N/A 4(d) Optional,N/A(d) Optional,N/A(d) No. of Shared TLB entries N/A N/A 128(d) 64,N/A(d) 64,N/A(d) Interface Avalon Avalon Avalon PLB,AXI(d),LMB,FSL,XCL PLB,AXI(d),LMB,FSL,XCL Three versions of Nios II cores are economic, standard and fast cores, Nios II/e, Nios II/s and Nios II/f, respectively. MicroBlaze is the most wildly used soft core provided by Xilinx. 14 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Implementations and Comparisons Then two comparison works are presented: I. All selected processors and three versions of Nios II cores provided by Altera (economic, standard and fast cores, which are noted as Nios II/e, Nios II/s and Nios II/f, respectively ) are implemented on an Altera Stratix V FPGA, and the implementation results are compared and discussed.
Load more

Recommended publications
  • Field Programmable Gate Arrays with Hardwired Networks on Chip
    Field Programmable Gate Arrays with Hardwired Networks on Chip PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Technische Universiteit Delft, op gezag van de Rector Magnificus prof. ir. K.C.A.M. Luyben, voorzitter van het College voor Promoties, in het openbaar te verdedigen op dinsdag 6 november 2012 om 15:00 uur door MUHAMMAD AQEEL WAHLAH Master of Science in Information Technology Pakistan Institute of Engineering and Applied Sciences (PIEAS) geboren te Lahore, Pakistan. Dit proefschrift is goedgekeurd door de promotor: Prof. dr. K.G.W. Goossens Copromotor: Dr. ir. J.S.S.M. Wong Samenstelling promotiecommissie: Rector Magnificus voorzitter Prof. dr. K.G.W. Goossens Technische Universiteit Eindhoven, promotor Dr. ir. J.S.S.M. Wong Technische Universiteit Delft, copromotor Prof. dr. S. Pillement Technical University of Nantes, France Prof. dr.-Ing. M. Hubner Ruhr-Universitat-Bochum, Germany Prof. dr. D. Stroobandt University of Gent, Belgium Prof. dr. K.L.M. Bertels Technische Universiteit Delft Prof. dr.ir. A.J. van der Veen Technische Universiteit Delft, reservelid ISBN: 978-94-6186-066-8 Keywords: Field Programmable Gate Arrays, Hardwired, Networks on Chip Copyright ⃝c 2012 Muhammad Aqeel Wahlah All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without permission of the author. Printed in The Netherlands Acknowledgments oday when I look back, I find it a very interesting journey filled with different emotions, i.e., joy and frustration, hope and despair, and T laughter and sadness.
    [Show full text]
  • ASIC Implemented Microblaze-Based Coprocessor for Data Stream
    ASIC-IMPLEMENTED MICROBLAZE-BASED COPROCESSOR FOR DATA STREAM MANAGEMENT SYSTEMS A Thesis Submitted to the Faculty of Purdue University by Linknath Surya Balasubramanian In Partial Fulfillment of the Requirements for the Degree of Master of Science in Electrical and Computer Engineering May 2020 Purdue University Indianapolis, Indiana ii THE PURDUE UNIVERSITY GRADUATE SCHOOL STATEMENT OF THESIS APPROVAL Dr. John J. Lee, Chair Department of Electrical and Computer Engineering Dr. Lauren A. Christopher Department of Electrical and Computer Engineering Dr. Maher E. Rizkalla Department of Electrical and Computer Engineering Approved by: Dr. Brian King Head of Graduate Program iii ACKNOWLEDGMENTS I would first like to express my gratitude to my advisor Dr. John J. Lee and my thesis committee members Dr. Lauren A. Christopher and Dr. Maher E. Rizkalla for their patience, guidance, and support during this journey. I would also like to thank Mrs. Sherrie Tucker for her patience, help, and encouragement. Lastly, I must thank Dr. Pranav Vaidya and Mr. Tareq S. Alqaisi for all their support, technical guidance, and advice. Thank you all for taking time and helping me complete this study. iv TABLE OF CONTENTS Page LIST OF TABLES :::::::::::::::::::::::::::::::::: vi LIST OF FIGURES ::::::::::::::::::::::::::::::::: vii ABSTRACT ::::::::::::::::::::::::::::::::::::: ix 1 INTRODUCTION :::::::::::::::::::::::::::::::: 1 1.1 Previous Work ::::::::::::::::::::::::::::::: 1 1.2 Motivation :::::::::::::::::::::::::::::::::: 2 1.3 Thesis Outline ::::::::::::::::::::::::::::::::
    [Show full text]
  • RTEMS CPU Supplement Documentation Release 4.11.3 ©Copyright 2016, RTEMS Project (Built 15Th February 2018)
    RTEMS CPU Supplement Documentation Release 4.11.3 ©Copyright 2016, RTEMS Project (built 15th February 2018) CONTENTS I RTEMS CPU Architecture Supplement1 1 Preface 5 2 Port Specific Information7 2.1 CPU Model Dependent Features...........................8 2.1.1 CPU Model Name...............................8 2.1.2 Floating Point Unit..............................8 2.2 Multilibs........................................9 2.3 Calling Conventions.................................. 10 2.3.1 Calling Mechanism.............................. 10 2.3.2 Register Usage................................. 10 2.3.3 Parameter Passing............................... 10 2.3.4 User-Provided Routines............................ 10 2.4 Memory Model..................................... 11 2.4.1 Flat Memory Model.............................. 11 2.5 Interrupt Processing.................................. 12 2.5.1 Vectoring of an Interrupt Handler...................... 12 2.5.2 Interrupt Levels................................ 12 2.5.3 Disabling of Interrupts by RTEMS...................... 12 2.6 Default Fatal Error Processing............................. 14 2.7 Symmetric Multiprocessing.............................. 15 2.8 Thread-Local Storage................................. 16 2.9 CPU counter...................................... 17 2.10 Interrupt Profiling................................... 18 2.11 Board Support Packages................................ 19 2.11.1 System Reset................................. 19 3 ARM Specific Information 21 3.1 CPU Model Dependent Features..........................
    [Show full text]
  • SH-1/SH-2/SH-DSP Programming Manual
    Hitachi SuperH™ RISC Engine SH-1/SH-2/SH-DSP Programming Manual ADE-602-063C Rev. 4.0 5/13/99 Hitachi ,Ltd Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.
    [Show full text]
  • Superh RISC Engine SH-1/SH-2
    SuperH RISC Engine SH-1/SH-2 Programming Manual September 3, 1996 Hitachi America Ltd. Notice When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Introduction The SuperH RISC engine family incorporates a RISC (Reduced Instruction Set Computer) type CPU. A basic instruction can be executed in one clock cycle, realizing high performance operation. A built-in multiplier can execute multiplication and addition as quickly as DSP.
    [Show full text]
  • Superh Family Catalog 3A
    SuperH® Family of Microcontrollers and Microprocessors ® 2006.4 Renesas Technology America SuperH® Family of Microcontrollers & Microprocessors 2006 Catalog Renesas — Your Best Decision for Microcontrollers and Microprocessors Choose for your next design; use for all your future ones. Renesas Technology, the leading global supplier of microcontrollers and microprocessors for embedded systems, especially flash microcomputers, makes it easy to select the right device for any application. The hundreds of devices in our H8®, M16C™ and SuperH® families, among others, have upwardly compatible architectures and standard platforms covering wide spans of performance, integration, power efficiency and price points. Your choices extend from cost-effective 8-bit microcontrollers to high-performance 16-bit and high-end 32-bit devices. These easy-to-use chips can enable your design innovations now and in the future. Our advanced silicon solutions simplify system optimizations, facilitate design enhancements and diversifications, and help you meet tight cost budgets. Key markets for Renesas microcontrollers and microprocessors include the mobile, automotive and PC/AV fields. For example, we are a leader in devices for car information systems, the technology forerunner in application processors for multimedia mobile phones, and an innovator in devices for power inverter applications. By choosing world-class Renesas solutions, you get highly reliable designs produced in high-quality fabrication facilities, and benefit from ongoing development defined by solid technology roadmaps. You can shorten your system design cycles and improve your time-to-market by taking advantage of our total system support, including software solutions, starter kits, reference platforms, reference designs, and middleware. Expert third-party support is available as well.
    [Show full text]
  • IT Acronyms.Docx
    List of computing and IT abbreviations /.—Slashdot 1GL—First-Generation Programming Language 1NF—First Normal Form 10B2—10BASE-2 10B5—10BASE-5 10B-F—10BASE-F 10B-FB—10BASE-FB 10B-FL—10BASE-FL 10B-FP—10BASE-FP 10B-T—10BASE-T 100B-FX—100BASE-FX 100B-T—100BASE-T 100B-TX—100BASE-TX 100BVG—100BASE-VG 286—Intel 80286 processor 2B1Q—2 Binary 1 Quaternary 2GL—Second-Generation Programming Language 2NF—Second Normal Form 3GL—Third-Generation Programming Language 3NF—Third Normal Form 386—Intel 80386 processor 1 486—Intel 80486 processor 4B5BLF—4 Byte 5 Byte Local Fiber 4GL—Fourth-Generation Programming Language 4NF—Fourth Normal Form 5GL—Fifth-Generation Programming Language 5NF—Fifth Normal Form 6NF—Sixth Normal Form 8B10BLF—8 Byte 10 Byte Local Fiber A AAT—Average Access Time AA—Anti-Aliasing AAA—Authentication Authorization, Accounting AABB—Axis Aligned Bounding Box AAC—Advanced Audio Coding AAL—ATM Adaptation Layer AALC—ATM Adaptation Layer Connection AARP—AppleTalk Address Resolution Protocol ABCL—Actor-Based Concurrent Language ABI—Application Binary Interface ABM—Asynchronous Balanced Mode ABR—Area Border Router ABR—Auto Baud-Rate detection ABR—Available Bitrate 2 ABR—Average Bitrate AC—Acoustic Coupler AC—Alternating Current ACD—Automatic Call Distributor ACE—Advanced Computing Environment ACF NCP—Advanced Communications Function—Network Control Program ACID—Atomicity Consistency Isolation Durability ACK—ACKnowledgement ACK—Amsterdam Compiler Kit ACL—Access Control List ACL—Active Current
    [Show full text]
  • The Cortex-M Series: Hardware and Software
    The Cortex-M Chapter Series: Hardware 2 and Software Introduction In this chapter the real-time DSP platform of primary focus for the course, the Cortex M4, will be introduced and explained. in terms of hardware, software, and development environments. Beginning topics include: • ARM Architectures and Processors – What is ARM Architecture – ARM Processor Families – ARM Cortex-M Series – Cortex-M4 Processor – ARM Processor vs. ARM Architectures • ARM Cortex-M4 Processor – Cortex-M4 Processor Overview – Cortex-M4 Block Diagram – Cortex-M4 Registers ECE 5655/4655 Real-Time DSP 2–1 Chapter 2 • The Cortex-M Series: Hardware and Software What is ARM Architecture • ARM architecture is a family of RISC-based processor archi- tectures – Well-known for its power efficiency; – Hence widely used in mobile devices, such as smart phones and tablets – Designed and licensed to a wide eco-system by ARM • ARM Holdings – The company designs ARM-based processors; – Does not manufacture, but licenses designs to semiconduc- tor partners who add their own Intellectual Property (IP) on top of ARM’s IP, fabricate and sell to customers; – Also offer other IP apart from processors, such as physical IPs, interconnect IPs, graphics cores, and development tools 2–2 ECE 5655/4655 Real-Time DSP ARM Processor Families ARM Processor Families • Cortex-A series (Application) Cortex-A57 Cortex-A53 – High performance processors Cortex-A15 Cortex-A9 Cortex-A Cortex-A8 capable of full Operating Sys- Cortex-A7 Cortex-A5 tem (OS) support; Cortex-R7 Cortex-R5 Cortex-R – Applications include smart- Cortex-R4 Cortex-M4 New!: Cortex-M7, Cortex-M33 phones, digital TV, smart Cortex-M3 Cortex-M1 Cortex-M Cortex-M0+ books, home gateways etc.
    [Show full text]
  • A Soft Processor Microblaze-Based Embedded System for Cardiac Monitoring
    (IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 4, No. 9, 2013 A Soft Processor MicroBlaze-Based Embedded System for Cardiac Monitoring El Hassan El Mimouni Mohammed Karim University Sidi Mohammed Ben Abdellah University Sidi Mohammed Ben Abdellah Fès, Morocco Fès, Morocco Abstract—this paper aims to contribute to the efforts of recent years, and has become also an important way to assert design community to demonstrate the effectiveness of the state of the heart’s condition [5 - 9]. the art Field Programmable Gate Array (FPGA), in the embedded systems development, taking a case study in the II. SYSTEM OVERVIEW biomedical field. With this design approach, we have developed a We have designed and implemented a prototype of basic System on Chip (SoC) for cardiac monitoring based on the soft embedded system for cardiac monitoring, whose functional processor MicroBlaze and the Xilkernel Real Time Operating block diagram is shown in the figure 2; it exhibits a modular System (RTOS), both from Xilinx. The system permits the structure that facilitates the development and debugging. Thus, acquisition and the digitizing of the Electrocardiogram (ECG) analog signal, displaying heart rate on seven segments module it includes 2 main modules: and ECG on Video Graphics Adapter (VGA) screen, tracing the An analog module intended for acquiring and heart rate variability (HRV) tachogram, and communication conditioning of the analog ECG signal to make it with a Personal Computer (PC) via the serial port. We have used appropriate for use by the second digital module ; the MIT_BIH Database records to test and evaluate our implementation performance.
    [Show full text]
  • Accelerated V2X Provisioning with Extensible Processor Platform
    Accelerated V2X provisioning with Extensible Processor Platform Henrique S. Ogawa1, Thomas E. Luther1, Jefferson E. Ricardini1, Helmiton Cunha1, Marcos Simplicio Jr.2, Diego F. Aranha3, Ruud Derwig4 and Harsh Kupwade-Patil1 1 America R&D Center (ARC), LG Electronics US Inc. {henrique1.ogawa,thomas.luther,jefferson1.ricardini,helmiton1.cunha}@lge.com [email protected] 2 University of Sao Paulo, Brazil [email protected] 3 Aarhus University, Denmark [email protected] 4 Synopsys Inc., Netherlands [email protected] Abstract. With the burgeoning Vehicle-to-Everything (V2X) communication, security and privacy concerns are paramount. Such concerns are usually mitigated by combining cryptographic mechanisms with a suitable key management architecture. However, cryptographic operations may be quite resource-intensive, placing a considerable burden on the vehicle’s V2X computing unit. To assuage this issue, it is reasonable to use hardware acceleration for common cryptographic primitives, such as block ciphers, digital signature schemes, and key exchange protocols. In this scenario, custom extension instructions can be a plausible option, since they achieve fine-tuned hardware acceleration with a low to moderate logic overhead, while also reducing code size. In this article, we apply this method along with dual-data memory banks for the hardware acceleration of the PRESENT block cipher, as well as for the F2255−19 finite field arithmetic employed in cryptographic primitives based on Curve25519 (e.g., EdDSA and X25519). As a result, when compared with a state-of-the-art software-optimized implementation, the performance of PRESENT is improved by a factor of 17 to 34 and code size is reduced by 70%, with only a 4.37% increase in FPGA logic overhead.
    [Show full text]
  • Performance Evaluation of FPGA Based Embedded ARM Processor
    10.1109/ULTSYM.2013.0135 Performance Evaluation of FPGA based Embedded ARM Processor for Ultrasonic Imaging Spenser Gilliland, Pramod Govindan, Thomas Gonnot and Jafar Saniie Department of Electrical and Computer Engineering Illinois Institute of Technology, Chicago IL, U.S.A. Abstract- This study evaluates the performance of an FPGA based embedded ARM processor system to implement signal processing for ultrasonic imaging and nondestructive testing applications. FPGA based embedded processors possess many advantages including a reduced overall development time, increased performance, and the ability to perform hardware- software (HW/SW) co-design. This study examines the execution performance of split spectrum processing, chirplet signal decomposition, Wigner-Ville distributions and short time Fourier transform implementations, on two embedded processing platforms: a Xilinx Virtex-5 FPGA with embedded MicroBlaze processor and a Xilinx Zynq FPGA with embedded ARM processor. Overall, the Xilinx Zynq FPGA significantly outperforms the Virtex-5 based system in software applications I. INTRODUCTION Figure 1. RUSH SoC setup Generally, ultrasonic imaging applications use personal computers or hand held devices. As these devices are not frequency diverse flaw detection [1], parametric echo specifically designed for efficiently executing estimation [2], and joint time-frequency distribution [3]) on computationally intensive ultrasonic signal processing the RUSH platform using a Xilinx Virtex-5 FPGA with an algorithms, the performance of these applications can be embedded soft-core MicroBlaze processor [4,5] and a improved by executing the algorithms using a dedicated Xilinx Zynq 7020 FPGA with an embedded ARM processor embedded system-on-chip (SoC) hardware. However, [6,7] as shown in Figure 2. porting these applications onto an embedded system requires deep knowledge of the processor architecture and RUSH embedded software development tools.
    [Show full text]
  • ESC-470: ARM 9 Instruction Set Architecture with Performance
    ARM 9 Instruction Set Architecture Introduction with Performance Perspective Joe-Ming Cheng, Ph.D. ARM-family processors are positioned among the leaders in key embedded applications. Many presentations and short lectures have already addressed the ARM’s applications and capabilities. In this introduction, we intend to discuss the ARM’s instruction set uniqueness from the performance prospective. This introduction is also trying to follow the approaches established by two outstanding textbooks of David Patterson and John Hennessey [PetHen00] [HenPet02]. 1.0 ARM Instruction Set Architecture Processor instruction set architecture (ISA) choices have evolved from accumulator, stack, register-to- memory, to register-register (load-store) organization. ARM 9 ISA is a load-store machine. ARM 9 ISA takes advantage of its smaller set of registers (16 vs. many 32-register processors) to incorporate more direct controls and achieve high encoding density. ARM’s load or store multiple register instruction, for example , allows enlisting of all possible registers and conditional execution in one instruction. The Thumb mode instruction set is another exa mple of how ARM ISA facilitates higher encode density. Rather than compressing the code, Thumb -mode instructions are two 16-bit instructions packed in a 32-bit ARM-mode instruction space. The Thumb -mode instructions are a subset of ARM instructions. When executing in Thumb mode, a single 32-bit instruction fetch cycle effectively brings in two instructions. Thumb code reduces access bandwidth, code size, and improves instruction cache hit rate. Another way ARM achieves cycle time reduction is by using Harvard architecture. The architecture facilitates independent data and instruction buses.
    [Show full text]