A Survey of Open Source Processors for Fpgas

Home , ARC (processor), DLX, MicroBlaze, SuperH

A Survey of Open Source Processors for FPGAs

Rui Jia, Colin Yu Lin, Zhenhong Guo and Haigang Yang

System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China

Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 CONTENTS A Survey of Open Source Processors for FPGAs

01 Motivation 02 Overview of Open Source Soft Processors 03 Selection of Open Source Processors 04 Implementations and Comparisons 05 Discussions and Conclusion

1 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 FPGA-based SoCs FPGA-based SoCs have become a technology trend for reconfigurable systems. The most attractive and practical methodology for SOC designer is to select reusable components and IPs Processor should be designed, verified, tested and shared in module level. Open source soft core processor Open source hardware improves the design productivity. many open source processors are available.

How to choose suitable soft processors for FPGA-based SoCs? Numerous open source processors make the selection process difficult. Differences between existing vendor-provided and open source processors？ 2 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Totally 178 processors found on OpenCores, soft microprocessor and Wikipedia 33 9 processors are not designed Planning for FPGAs->169 processors Pre-Alpha 27 considered Alpha Life cycle is categorized into 68 Beta planning, pre-alpha, alpha, 11 beta, stable, and mature Stable stages unknown 24 6 Only 68 in stable can be used conveniently, in which processor is feature-complete and has few

bugs 3 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 68 stable processors: (a)License. (b)Instruction Set Architecture(ISA). (c)Compiler and assembler (d)Verification (d)Design documentation . 4 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 License

The license of processors cover: GNU General Public License (GPL), GNU Lesser General Public License (LGPL) Berkeley Software Division (BSD), Creative Commons-Attribution (CC-BY). 5 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Provider ISA Number Instruction Set Architecture (ISA) ARM ARMv2 1 Lattice Semiconductor LatticeMicro32 1 DLX 1 Free Open Cores OpenRISC 3 unnamed 14 Sun Microsystems SPARCv8 1 SPARCv9 4 Atmel AVR 5 Hitachi SuperH-2 1 8080 2 8088 3 Intel 80186 1 MCS-48 1 Microchip Technology PIC-baseline family 5 MIPS I 6 MIPS Technology MIPS 16 1 MIPS 32 4 Proprietary MOS Technology 6502 3 6800 1 68000 1 Motorola 68HC05 1 68HC11 1 In the table, most of the ISAs are property of 68HC08 1 National Semiconductor COP400 1 commercial corporations. Synopsys ARC 3 Texas Instruments MSP430 1 Xilinx MicroBlaze 1 Only 35% of these ISAs are free and can be used without Zilog Z80 4 Total 68 infringements to the commercial corporations.

6 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Compiler and Assembler

38 processors have both compiler and assembler 12 processors only assembler 18 processors do not provide either

7 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Verification Design Documentation

about 68% processors have Availability of design files and been verified on FPGAs. documents weigh heavy. 7 of the processors have also About 43% processors have no been verified as ASIC. design documentation. 8 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Summary Features of open source soft processors are summarized in Table below. The table consists of 68 stable soft processors under open source license

9 8 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 CONTENTS A Survey of Open Source Processors for FPGAs

01 Introduction 02 Overview of Open Source Soft Processors 03 Selection of Open Source Processors 04 Implementations and Comparisons 05 Discussions and Conclusion

10 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Selecting Method/Processtotal 68 stable ones, 47 processors under open source license are chosen. choose 36 processors with available compiler and assembler. 17 processors with free ISA are chosen.

11 processors with general ISA 3 multi-core processors processor 1are asynchronous not studied. processor is not studied.

11 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Selecting Method/Process They are Amber ,LatticeMicro32 (LM32), S1, Altor32, OpenRISC 1200 (OR1200), LEON2 and LEON3.

Amber23 Amber25 LM32 S1 Altor32 OR1200 LEON2 LEON3 Bit-width 32 32 32 64 32 32 32 32

Pipeline Depth 3 5 6 6 5 5 5 7

o i x Multiplier √ √ Optional,√(d) √ √ √ √

t √

p n u Divider N/A N/A Optional,√(d) N/A N/A

m √ √ √

m C

o FPU N/A N/A N/A √ N/A N/A √ √ C Register 15 15 32 640 32 32 40-520, 136(d) 40-520,136(d)

e 0,1,2,4(d),8 16(d)

r Total Size/Kbytes 8(d),12,16,32 16,24,32(d) 32(d) 16(d) 8(d) 0.008(d)-64

t c

e Instruction Cache/Kbytes 8,12,16(d),32 0,1,2(d),4,8 16(d) 8(d) 8(d) 4(d) 0.004(d)-32 t

i 8(d),12,16,32 h

c Data Cache/Kbytes 8,12,16(d),32 0,1,2(d),4,8 16(d) 8(d) 8(d) 4(d) 0.004(d)-32

e r Sets 256(d) 256(d) 128,256,512(d),... 128(d) 256(d) 512(d) 1(d)-256

h 128(d)

a e

C Associativity/Ways 2(d),3,4 or 8 2,3,4(d) or 8 1(d),2 4(d) 1(d) 1(d) 1(d)-4

c 1(d)-4

o r

P Byte-per-line/Bytes 16 16 4(d),8,16 32(d) 32 16(d) 32(d) 4(d)-8 Write policy Write through Write through Write through Write through Write through Write through Write through Write through Replacement policy Read- miss Read- miss Read- miss LRU Read- miss LRU LRU,LRR,Random(d) LRU,LRR,Random Shared/Separate TLB N/A N/A N/A Separate N/A Separate N/A(d),Optional N/A(d),Optional

U No. of Instruction TLB entries N/A N/A N/A 64 N/A 16,32,64(d),128 2-32,N/A(d) 2-32 M

M No. of Data TLB entries N/A N/A N/A 64 N/A 16,32,64(d),128 2-32,N/A(d) 2-32 No. of Shared TLB entries N/A N/A N/A N/A N/A N/A 2-32,N/A(d) 2-32 Wishbone Wishbone Interface Wishbone Wishbone Wishbone Wishbone Wishbone Amba /Amba /Amba

12 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 CONTENTS A Survey of Open Source Processors for FPGAs

01 Introduction 02 Overview of Open Source Soft Processors 03 Selection of Open Source Processors 04 Implementations and Comparisons 05 Discussions and Conclusion

13 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Processor Descriptions Features of selected commercial processors

Altera Xilinx Nios II/e Nios II/s Nios II/f MicroBlaze/single MicroBlaze/dual Bit-width 32 32 32 32 32

Pipeline Depth N/A 5 6 3/5(d) 3/5(d)

o i

x Multiplier N/A Optional,N/A(d) Optional,√(d) Optional,√(d) Optional,√(d)

p n

u Divider N/A Optional,N/A(d) Optional,√(d) Optional,N/A(d) Optional,N/A(d)

m C

o FPU N/A N/A N/A Optional,N/A(d) Optional,N/A(d) C Register 32 32 32 32 32

e Total Size/Kbytes N/A 2(d),4,... 4(d),8,... 16,32,N/A(d) 16,32,N/A(d)

t c

e Instruction Cache/KBytes N/A 2(d),4 2(d),4,... 8,16,N/A(d) 8,16,N/A(d)

i h

c Data Cache/KBytes N/A N/A 2(d),4,... 8,16,N/A(d) 8,16,N/A(d)

r Sets N/A 64(d),128 64(d),128,... 512 512

a e

C Associativity/Ways N/A 1(d) 1(d) 1 1

o r

P Byte-per-line/Bytes N/A 32(d) 4,16,32(d),... 16(d),32 16(d),32 Write policy N/A N/A Write through Write through(d),Write Back Write through(d),Write Back Replacement policy N/A unkown unkown unkown unkown Shared/Separate TLB N/A N/A Shared+Separate Separate+Shared Separate+Shared

U No. of Instruction TLB entries N/A N/A 6(d) Optional,N/A(d) Optional,N/A(d) M

M No. of Data TLB entries N/A N/A 4(d) Optional,N/A(d) Optional,N/A(d) No. of Shared TLB entries N/A N/A 128(d) 64,N/A(d) 64,N/A(d) Interface Avalon Avalon Avalon PLB,AXI(d),LMB,FSL,XCL PLB,AXI(d),LMB,FSL,XCL Three versions of Nios II cores are economic, standard and fast cores, Nios II/e, Nios II/s and Nios II/f, respectively. MicroBlaze is the most wildly used soft core provided by Xilinx. 14 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Implementations and Comparisons Then two comparison works are presented: I. All selected processors and three versions of Nios II cores provided by Altera (economic, standard and fast cores, which are noted as Nios II/e, Nios II/s and Nios II/f, respectively ) are implemented on an Altera Stratix V FPGA, and the implementation results are compared and discussed. II. The selected processors and MicroBlaze supplied by Xilinx are also implemented on a Xilinx Virtex-7 FPGA, and the implementation results are compared and discussed.

15 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Regs Fmax/MHz Altera Stratix V FPGA 3500 400 3000 350 300 (a) shows the resource 2500 250 2000 comparison results 200 1500 Nios II/e/s/f can be implemented 150 with less ALMs and registers than 1000 100 500 50 Pipeline ALMs Depth all the open source processors. 0 1000 2000 3000 4000 5000 6000 0 2 4 6 8

(a) Logic Resources Utilization (b) Pipeline depth and Fmax TBMBs/bits LEON3 needs the least resources P /mW 5 CD x 10 100 3.5 in all selected open source 3 80 processors. 2.5 60 2 The average ALMs and registers 1.5 of Nios II e/s/f is 19% and 29% of 40 1 0.5 the averages of all open source 20 0 Cache Size 0 ALMs -0.5 processors. 0 1000 2000 3000 4000 5000 6000 0 5 10 15 20 25 30 35

Amber23 Amber25 LM32 OR1200 LEON3 Altor32 16 Nios II/e Nios II/s Nios II/f Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Regs Fmax/MHz Altera Stratix V FPGA 3500 400 3000 350 300 (b) compares the maximum 2500 250 frequency vs. pipeline depth 2000 200 1500 Fmax of Nios II/e/s/f are higher 150 than all open source processors. 1000 100 500 50 Pipeline ALMs Depth Fmax of Nios II/e is the highest and 0 1000 2000 3000 4000 5000 6000 0 2 4 6 8 F of Nios II/s is the lowest in all (a) Logic Resources Utilization (b) Pipeline depth and Fmax max TBMBs/bits P /mW 5 CD x 10 three versions of Nios II. 100 3.5 3 80 LEON3 with 7 stages of pipeline 2.5 and Amber23 with a 3-stage 60 2 1.5 pipeline achieve the highest and 40 1 0.5 the lowest frequencies in all open 20 0 Cache Size source processors, respectively. 0 ALMs -0.5 0 1000 2000 3000 4000 5000 6000 0 5 10 15 20 25 30 35 Fmax of open source processor is (c) ALMs and PCD (d) Cache Size and TBMBs proportionate to the pipeline Amber23 Amber25 LM32 OR1200 LEON3 Altor32 depth. 17 Nios II/e Nios II/s Nios II/f Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Regs Fmax/MHz Altera Stratix V FPGA 3500 400 3000 350 300 2500 The core static thermal power 250 2000 200 dissipations P of all processors 1500 CS 150 are nearly the same, because they 1000 100 are mainly decided by the chosen 500 50 Pipeline ALMs Depth 0 1000 2000 3000 4000 5000 6000 0 2 4 6 8

FPGA device. (a) Logic Resources Utilization (b) Pipeline depth and Fmax TBMBs/bits P /mW 5 CD x 10  The core dynamic thermal power 100 3.5 3 dissipations PCD and the number of 80 2.5

ALMs are expressed in (c). 60 2 1.5 PCD is proportionate to ALMs 40 1 P of Nios II/e/s/f are less than 0.5 CD 20 0 Cache all open source processors. Size 0 ALMs -0.5 0 1000 2000 3000 4000 5000 6000 0 5 10 15 20 25 30 35

Amber23 Amber25 LM32 OR1200 LEON3 Altor32 18 Nios II/e Nios II/s Nios II/f Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Regs Fmax/MHz Altera Stratix V FPGA 3500 400 3000 350 300 2500 250 2000 Total block memory bits (TBMBs) 200 1500 are mainly decided by total cache 150 1000 size. 100 500 50 Pipeline ALMs Depth (d) illustrates the relationship 0 1000 2000 3000 4000 5000 6000 0 2 4 6 8 (a) Logic Resources Utilization (b) Pipeline depth and Fmax TBMBs/bits between total block memory bits P /mW 5 CD x 10 100 3.5 (TBMBs) and the total cache size. 3 80 The values of TBMBs vary directly 2.5 60 2 with the total size of caches. 1.5 40 1 0.5 20 0 Cache Size 0 ALMs -0.5 0 1000 2000 3000 4000 5000 6000 0 5 10 15 20 25 30 35

Amber23 Amber25 LM32 OR1200 LEON3 Altor32 19 Nios II/e Nios II/s Nios II/f Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Regs Fmax/MHz

Xilinx Virtex-7 FPGA 3500 250 (a) shows the resource 3000 2500 200 comparison results 2000 MicroBlaze can be implemented150 0 150 1000 with less LUTs and Regs than all Pipeline 500 LUTs 100 Depth 1000 2000 3000 4000 5000 6000 7000 2 3 4 5 6 7 8 open source processors. (a) Logic Resources Utilization (b) Pipeline depth and Fmax

PCD/mW NR LEON3 needs the least 90 50 80 40 resources in all selected open 70 60 30 source processors. 50 40 20 The LUTs and Regs of 30 10 MicroBlaze is 41% and 58% of the20 10 0 Cache LUTs 0 Size averages of all open source 1000 2000 3000 4000 5000 6000 7000 0 5 10 15 20 25 30 35 processors. (c) LUTs and Pd (d) Cache Size and NR Amber23 Amber25 LM32 OR1200 LEON3 Altor32 20 MicroBlaze Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Regs Fmax/MHz

Xilinx Virtex-7 FPGA 3500 250 (b) compares the maximum 3000 2500 200 frequency vs. pipeline depth 2000

The Fmax of MicroBlaze is higher150 0 150 1000 than all open source processors Pipeline 500 LUTs 100 Depth 1000 2000 3000 4000 5000 6000 7000 2 3 4 5 6 7 8 except LEON3. (a) Logic Resources Utilization (b) Pipeline depth and Fmax

PCD/mW NR  LEON3 with 7 stages of pipeline90 50 80 40 and Amber23 with a 3-stage 70 60 30 pipeline achieve the highest and 50 40 20 lowest frequencies in all open 30 10 source processors, respectively. 20 10 0 Cache LUTs 0 Size  Fmax of open source processor is10 00 2000 3000 4000 5000 6000 7000 0 5 10 15 20 25 30 35 proportionate to the pipeline depth. (c) LUTs and Pd (d) Cache Size and NR Amber23 Amber25 LM32 OR1200 LEON3 Altor32 21 MicroBlaze Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Regs Fmax/MHz

Xilinx Virtex-7 FPGA 3500 250 the quiescent power (P ) of all 3000 s 2500 200 processors are nearly the same, 2000 because they are mainly decided1 500 150 1000 by the chosen FPGA device. Pipeline 500 LUTs 100 Depth 1000 2000 3000 4000 5000 6000 7000 2 3 4 5 6 7 8 The core dynamic thermal power (a) Logic Resources Utilization (b) Pipeline depth and Fmax

PCD/mW NR dissipations PCD and the number of90 50 80 40 LUTs are expressed in (c). 70 60 30 Pd is proportionate to LUTs, and5 0 40 20 Pd of MicroBlaze is less than all 30 10 open source processors. 20 10 0 Cache LUTs 0 Size 1000 2000 3000 4000 5000 6000 7000 0 5 10 15 20 25 30 35

Amber23 Amber25 LM32 OR1200 LEON3 Altor32 22 MicroBlaze Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Regs Fmax/MHz

Xilinx Virtex-7 FPGA 3500 250 The number of RAMB36E1’s 3000 2500 200 (NR36E1) and the number of 2000 RAMB18E1’s (NR18E1) are mainly1 500 150 1000 decided by total cache size. Pipeline 500 LUTs 100 Depth 1000 2000 3000 4000 5000 6000 7000 2 3 4 5 6 7 8 (d) illustrates the relationship (a) Logic Resources Utilization (b) Pipeline depth and Fmax

PCD/mW NR between equivalent RAM blocks 90 50 80 40 (NR) and the total cache size, 70 60 30 where NR = 2 × NR36E1 + NR18E1. 50 40 20 The values of NR vary directly 30 10 with the total size of caches. 20 10 0 Cache LUTs 0 Size 1000 2000 3000 4000 5000 6000 7000 0 5 10 15 20 25 30 35

Amber23 Amber25 LM32 OR1200 LEON3 Altor32 23 MicroBlaze Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 CONTENTS A Survey of Open Source Processors for FPGAs

01 Introduction 02 Overview of Open Source Soft Processors 03 Selection of Open Source Processors 04 Implementations and Comparisons 05 Discussions and Conclusion

24 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Discussions: Based on the implementation results in last section, we discuss the two different categories of processors, open source versus commercial. 1. Open Source or Not?

Commercial soft cores Open source processors Commercial soft cores: free to access the source code reduce logic utilization, dynamic with excellent usability power consumption and CAD tool explore the strategies of run-time; optimizations for research and achieve high performance engineering. The configuration of them is  open source processors can be flexible. chosen to accelerate applications  EDA tools from FPGA venders requiring deep customizations. provide many configuration choices

25 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Discussions: Based on the implementation results in last section, we discuss the two different categories of processors, open source versus commercial. 2. Implementation

Commercial soft cores are superior to open source processors in logic utilization. The maximum frequency of commercial soft cores which are optimized by venders are higher than open source processors. The on-chip memory utilization depends on the total cache size.

26 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Discussions: Based on the implementation results in last section, we discuss the two different categories of processors, open source versus commercial. 3. Configurability and Conveniency

Commercial soft cores Open source processors All designed using user-friendly Advantages of customization and EDA tools from FPGA vendors. exploration for optimization in Soft cores with great configurability engineering and research. and lots of optimized IPs are avaiavle. Engineers and researchers can Systems can be constructed with a experiment and verify any possible suitable soft core, minimal peripherals methods for their deep customized and highly optimized hardware. optimizations.

27 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Conclusion : Processor should be designed, verified, tested and shared in module level to increase the design productivity. From the points of usability and stability, a selection process of open source processors is presented. The selected open source processors and existing commercial soft processors are implemented, compared and discussed. Based on the optimization for their own FPGAs, commercial soft cores are superior to open source processors in logic utilization and performance. Open source processors with excellent usability and flexibility can be used to explore the strategies of optimizations for research and engineering. 28 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Suggestions and discussions are welcome by email: [email protected]

Thank you!

29 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所  Implementations and Comparisons on Altera Stratix V FPGA

S1 and LEON2 need much more ALMs, registers Amber23 Amber25 LM32 S1 AltOR32 OR1200 LEON2 LEON3 Nios II/e Nios II/s Nios II/f and total block memory bits than all other processors, ALMs 3073 5278 2141 39519 2014 2428 5678 1239 409 590 811 and the maximum frequency of S1 is the lowest. REGs 1875 3221 2468 55061 1754 1191 10546 1272 591 862 1347 TBMB / bits 152,575 305,664 52,736 270,432 69,632 156,288 72704 8,704 10,240 27,200 44,544

Fmax(100℃)/MHz 84.73 96.11 179.92 52.32 94.64 110.3 158.5 212.27 367.51 260.48 297.89

Fmax(-40℃)/MHz 83.08 96.15 171.14 56.15 91.99 107.4 158.55 209.95 337.04 250.38 288.68

PCS / mW 1738.22 1744.96 1735.37 1751.5 1735.08 1737.05 1738.29 1733.99 1733.48 1733.87 1734.5

PCD / mW 48.44 90.38 24.13 369.47 17.71 30.22 61.56 13.31 10.46 12.28 16.56

PI/O / mW 36.13 62.51 48.38 50.25 43.98 56.56 35.90 43.31 41.91 42.50 42.36

Pt / mW 1822.78 1897.85 1807.87 2171.22 1796.77 1823.84 1835.75 1790.61 1785.85 1788.66 1793.42

TA&S 4min16s 7min3s 1min22s 12min52s 1min44s 1min12s 1min35s 38s 15s 15s 35s

TF 20min35s 23min19s 29min17s 1h27min27s 29min35s 20min45s 34min36s 17min47s 25min35s 16min12s 17min19s

Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所  Implementations and Comparisons on Xilinx Virtex-7 FPGA

Dual-core MicroBlaze needs almost twice of the Amber23 Amber25 LM32 S1 AltOR32 OR1200 LEON2 LEON3 MicroBlaze/single MicroBlaze/dual resources of the single-core version. LUTs 3274 6592 3281 56690 2742 3669 3674 2522 1491 3507 Regs 2306 3409 2233 38028 1629 1276 1559 1144 1114 2485

MicroBlaze can be implemented with less LUTs and NR36E1 8 16 4 48 2 4 2 0 2 2 Mem registers than all open source processors. NR18E1 4 8 0 17 1 2 3 2 0 0  LEON3 needs the least resources in all selected Fmax(25℃)/MHz 114.59 117.40 204.3 65.77 113.27 143.37 192.82 238.83 233.1 216.92 Ps / mW 429 435 428 476 430 431 430 431 487 487 open source processors. Pd / mW 23 83 18 489 37 44 34 44 12 14 The LUTs and registers of MicroBlaze is 41% and Pt/mW 452 519 446 965 467 475 464 474 499 501 58% of the averages of all open source processors. TS&T 1min20s 1min45s 15s 11min41s 1min55s 1min37s 1min21s 1min20s 1min8s 2min3s TF&P 5min45s 7min57s 4min24s 38min37s 7min39s 6min15s 4min42s 4min26s 3min15s 4min3s

Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所