A Survey of Open Source Processors for FPGAs Rui Jia, Colin Yu Lin, Zhenhong Guo and Haigang Yang System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China Corresponding Author: [email protected] Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 CONTENTS A Survey of Open Source Processors for FPGAs 01 Motivation 02 Overview of Open Source Soft Processors 03 Selection of Open Source Processors 04 Implementations and Comparisons 05 Discussions and Conclusion 1 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 FPGA-based SoCs FPGA-based SoCs have become a technology trend for reconfigurable systems. The most attractive and practical methodology for SOC designer is to select reusable components and IPs Processor should be designed, verified, tested and shared in module level. Open source soft core processor Open source hardware improves the design productivity. many open source processors are available. How to choose suitable soft processors for FPGA-based SoCs? Numerous open source processors make the selection process difficult. Differences between existing vendor-provided and open source processors？ 2 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Totally 178 processors found on OpenCores, soft microprocessor and Wikipedia 33 9 processors are not designed Planning for FPGAs->169 processors Pre-Alpha 27 considered Alpha Life cycle is categorized into 68 Beta planning, pre-alpha, alpha, 11 beta, stable, and mature Stable stages unknown 24 6 Only 68 in stable can be used conveniently, in which processor is feature-complete and has few bugs 3 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 68 stable processors: (a)License. (b)Instruction Set Architecture(ISA). (c)Compiler and assembler (d)Verification (d)Design documentation . 4 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 License The license of processors cover: GNU General Public License (GPL), GNU Lesser General Public License (LGPL) Berkeley Software Division (BSD), Creative Commons-Attribution (CC-BY). 5 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Provider ISA Number Instruction Set Architecture (ISA) ARM ARMv2 1 Lattice Semiconductor LatticeMicro32 1 DLX 1 Free Open Cores OpenRISC 3 unnamed 14 Sun Microsystems SPARCv8 1 SPARCv9 4 Atmel AVR 5 Hitachi SuperH-2 1 8080 2 8088 3 Intel 80186 1 MCS-48 1 Microchip Technology PIC-baseline family 5 MIPS I 6 MIPS Technology MIPS 16 1 MIPS 32 4 Proprietary MOS Technology 6502 3 6800 1 68000 1 Motorola 68HC05 1 68HC11 1 In the table, most of the ISAs are property of 68HC08 1 National Semiconductor COP400 1 commercial corporations. Synopsys ARC 3 Texas Instruments MSP430 1 Xilinx MicroBlaze 1 Only 35% of these ISAs are free and can be used without Zilog Z80 4 Total 68 infringements to the commercial corporations. 6 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Compiler and Assembler 38 processors have both compiler and assembler 12 processors only assembler 18 processors do not provide either 7 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Verification Design Documentation about 68% processors have Availability of design files and been verified on FPGAs. documents weigh heavy. 7 of the processors have also About 43% processors have no been verified as ASIC. design documentation. 8 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Summary Features of open source soft processors are summarized in Table below. The table consists of 68 stable soft processors under open source license 9 8 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 CONTENTS A Survey of Open Source Processors for FPGAs 01 Introduction 02 Overview of Open Source Soft Processors 03 Selection of Open Source Processors 04 Implementations and Comparisons 05 Discussions and Conclusion 10 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Selecting Method/Processtotal 68 stable ones, 47 processors under open source license are chosen. choose 36 processors with available compiler and assembler. 17 processors with free ISA are chosen. 11 processors with general ISA 3 multi-core processors processor 1are asynchronous not studied. processor is not studied. 11 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Selecting Method/Process They are Amber ,LatticeMicro32 (LM32), S1, Altor32, OpenRISC 1200 (OR1200), LEON2 and LEON3. Amber23 Amber25 LM32 S1 Altor32 OR1200 LEON2 LEON3 Bit-width 32 32 32 64 32 32 32 32 Pipeline Depth 3 5 6 6 5 5 5 7 n o i x Multiplier √ √ Optional,√(d) √ √ √ √ t √ e t l a i t p n u Divider N/A N/A Optional,√(d) N/A N/A m √ √ √ p U o m C o FPU N/A N/A N/A √ N/A N/A √ √ C Register 15 15 32 640 32 32 40-520, 136(d) 40-520,136(d) e 0,1,2,4(d),8 16(d) r Total Size/Kbytes 8(d),12,16,32 16,24,32(d) 32(d) 16(d) 8(d) 0.008(d)-64 u t c e Instruction Cache/Kbytes 8,12,16(d),32 0,1,2(d),4,8 16(d) 8(d) 8(d) 4(d) 0.004(d)-32 t i 8(d),12,16,32 h c Data Cache/Kbytes 8,12,16(d),32 0,1,2(d),4,8 16(d) 8(d) 8(d) 4(d) 0.004(d)-32 r A e r Sets 256(d) 256(d) 128,256,512(d),... 128(d) 256(d) 512(d) 1(d)-256 h 128(d) o c s s a e C Associativity/Ways 2(d),3,4 or 8 2,3,4(d) or 8 1(d),2 4(d) 1(d) 1(d) 1(d)-4 c 1(d)-4 o r P Byte-per-line/Bytes 16 16 4(d),8,16 32(d) 32 16(d) 32(d) 4(d)-8 Write policy Write through Write through Write through Write through Write through Write through Write through Write through Replacement policy Read- miss Read- miss Read- miss LRU Read- miss LRU LRU,LRR,Random(d) LRU,LRR,Random Shared/Separate TLB N/A N/A N/A Separate N/A Separate N/A(d),Optional N/A(d),Optional U No. of Instruction TLB entries N/A N/A N/A 64 N/A 16,32,64(d),128 2-32,N/A(d) 2-32 M M No. of Data TLB entries N/A N/A N/A 64 N/A 16,32,64(d),128 2-32,N/A(d) 2-32 No. of Shared TLB entries N/A N/A N/A N/A N/A N/A 2-32,N/A(d) 2-32 Wishbone Wishbone Interface Wishbone Wishbone Wishbone Wishbone Wishbone Amba /Amba /Amba 12 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 CONTENTS A Survey of Open Source Processors for FPGAs 01 Introduction 02 Overview of Open Source Soft Processors 03 Selection of Open Source Processors 04 Implementations and Comparisons 05 Discussions and Conclusion 13 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Processor Descriptions Features of selected commercial processors Altera Xilinx Nios II/e Nios II/s Nios II/f MicroBlaze/single MicroBlaze/dual Bit-width 32 32 32 32 32 Pipeline Depth N/A 5 6 3/5(d) 3/5(d) n o i x Multiplier N/A Optional,N/A(d) Optional,√(d) Optional,√(d) Optional,√(d) t e t l a i t p n u Divider N/A Optional,N/A(d) Optional,√(d) Optional,N/A(d) Optional,N/A(d) m p U o m C o FPU N/A N/A N/A Optional,N/A(d) Optional,N/A(d) C Register 32 32 32 32 32 e Total Size/Kbytes N/A 2(d),4,... 4(d),8,... 16,32,N/A(d) 16,32,N/A(d) r u t c e Instruction Cache/KBytes N/A 2(d),4 2(d),4,... 8,16,N/A(d) 8,16,N/A(d) t i h c Data Cache/KBytes N/A N/A 2(d),4,... 8,16,N/A(d) 8,16,N/A(d) r A e r Sets N/A 64(d),128 64(d),128,... 512 512 h o c s s a e C Associativity/Ways N/A 1(d) 1(d) 1 1 c o r P Byte-per-line/Bytes N/A 32(d) 4,16,32(d),... 16(d),32 16(d),32 Write policy N/A N/A Write through Write through(d),Write Back Write through(d),Write Back Replacement policy N/A unkown unkown unkown unkown Shared/Separate TLB N/A N/A Shared+Separate Separate+Shared Separate+Shared U No. of Instruction TLB entries N/A N/A 6(d) Optional,N/A(d) Optional,N/A(d) M M No. of Data TLB entries N/A N/A 4(d) Optional,N/A(d) Optional,N/A(d) No. of Shared TLB entries N/A N/A 128(d) 64,N/A(d) 64,N/A(d) Interface Avalon Avalon Avalon PLB,AXI(d),LMB,FSL,XCL PLB,AXI(d),LMB,FSL,XCL Three versions of Nios II cores are economic, standard and fast cores, Nios II/e, Nios II/s and Nios II/f, respectively. MicroBlaze is the most wildly used soft core provided by Xilinx. 14 Institute of Electronics, Chinese Academy of Sciences, Beijing China 中国科学院电子学研究所 Implementations and Comparisons Then two comparison works are presented: I. All selected processors and three versions of Nios II cores provided by Altera (economic, standard and fast cores, which are noted as Nios II/e, Nios II/s and Nios II/f, respectively ) are implemented on an Altera Stratix V FPGA, and the implementation results are compared and discussed.