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Intel® Celeron® Processor 900 Series and Ultra Low Voltage 700 Series

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Intel® Celeron® Processor 900 Series and Ultra Low Voltage 700 Series Intel® Celeron® Processor 900 Series and Ultra Low Voltage 700 Series Datasheet For platforms based on Mobile Intel® 4 Series Chipset family February 2010 Document Number: 320389-003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Φ 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information. 45nm product is manufactured on a lead-free process. Lead is below 1000 PPM per EU RoHS directive (2002/95/EC, Annex A). Some EU RoHS exemptions for lead may apply to other components used in the product package. Enhanced Intel SpeedStep® Technology for specified units of this processor are available. See the Processor Spec Finder at http:// processorfinder.intel.com or contact your Intel representative for more information. Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality. Φ Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor. Intel, Celeron, Intel Core Duo, Intel SpeedStep, MMX and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2008-2010, Intel Corporation. All rights reserved. 2 Datasheet Contents 1Introduction..............................................................................................................6 1.1 Terminology .......................................................................................................7 1.2 References .........................................................................................................8 2 Low Power Features ..................................................................................................9 2.1 Clock Control and Low-Power States ......................................................................9 2.1.1 Core Low-Power State Descriptions........................................................... 11 2.1.1.1 Core C0 State........................................................................... 11 2.1.1.2 Core C1/AutoHALT Powerdown State ........................................... 11 2.1.1.3 Core C1/MWAIT Powerdown State............................................... 12 2.1.1.4 Core C2 State........................................................................... 12 2.1.1.5 Core C3 State........................................................................... 12 2.1.2 Package Low-Power State Descriptions...................................................... 12 2.1.2.1 Normal State............................................................................ 12 2.1.2.2 Stop-Grant State ...................................................................... 12 2.1.2.3 Stop-Grant Snoop State............................................................. 13 2.1.2.4 Sleep State .............................................................................. 13 2.2 FSB Low-Power Enhancements............................................................................ 14 2.3 Processor Power Status Indicator (PSI-2) Signal .................................................... 14 3 Electrical Specifications ........................................................................................... 15 3.1 Power and Ground Pins ...................................................................................... 15 3.1.1 FSB Clock (BCLK[1:0]) and Processor Clocking........................................... 15 3.2 Voltage Identification and Power Sequencing ........................................................ 15 3.3 Catastrophic Thermal Protection .......................................................................... 18 3.4 Reserved and Unused Pins.................................................................................. 19 3.5 FSB Frequency Select Signals (BSEL[2:0])............................................................ 19 3.6 FSB Signal Groups............................................................................................. 19 3.7 CMOS Signals ................................................................................................... 21 3.8 Maximum Ratings.............................................................................................. 21 3.9 Processor DC Specifications ................................................................................ 22 4 Package Mechanical Specifications and Pin Information .......................................... 28 4.1 Package Mechanical Specifications ....................................................................... 28 4.2 Processor Pinout and Pin List .............................................................................. 30 4.3 Alphabetical Signals Reference ............................................................................ 47 5 Thermal Specifications and Design Considerations .................................................. 56 5.1 Monitoring Die Temperature ............................................................................... 57 5.1.1 Thermal Diode ....................................................................................... 57 5.1.2 Intel® Thermal Monitor........................................................................... 58 5.1.3 Digital Thermal Sensor............................................................................ 60 5.2 Out of Specification Detection ............................................................................. 61 5.3 PROCHOT# Signal Pin ........................................................................................ 61 Datasheet 3 Figures 1 Core Low-Power States .............................................................................................10 2 Package Low-Power States ........................................................................................11 3 Active VCC and ICC Loadline ......................................................................................25 4 Processor (ULV SC) Die Micro-FCBGA Processor Package Drawing ...................................29 5 Processor Top View Upper Left Side ............................................................................30 6 Procssor Top View Upper Right Side ............................................................................31 7 Processor Top View Lower Left Side ............................................................................32 8 Processor Top View Lower Right Side ..........................................................................33 Tables 1 Coordination of Core Low-Power States at the Package Level..........................................11 2 Voltage Identification Definition..................................................................................16 3 BSEL[2:0] Encoding for BCLK Frequency......................................................................19 4 FSB Pin Groups ........................................................................................................20 5 Processor Absolute Maximum Ratings..........................................................................22 6 Voltage and Current Specifications for the Single-Core, Ultra Low Voltage (ULV, 10 W) Processor ................................................................................................................23
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