iCEblink40-HX1K Evaluation Kit User’s Guide
September 2012 Revision: EB73_01.1 iCEblink40-HX1K Evaluation Kit User’s Guide
Introduction Thank you for choosing the Lattice Semiconductor iCEblink™40-HX1K Evaluation Kit.
This guide describes how to begin using the iCEblink40-HX1K Evaluation Kit, an easy-to-use platform for rapidly prototyping designs using the iCE40 FPGA. Features • High-performance, low-power iCE40HX1K FPGA • USB programming, debugging, virtual I/O functions, and power supply • Four user LEDs • Four capacitive-touch buttons • 3.3 MHz clock source • 1Mbit SPI serial configuration PROM • Supported by Lattice iCEcube2™ design software • 68 LVCMOS/LVTTL (3.3V) digital I/O connections on 0.1” through-hole connections • Supports third-party I/O expansion boards and modules, including 3.3V Arduino Shield boards (requires addi- tional sockets, not supplied)
Figure 1. iCEblink40-HX1K Evaluation Board and Major Hardware Features
USB Programming, Low Power iCE40 68 User I/O Pins Debug and Power FPGA (3.3V)
Capacitive Touch Buttons
User LEDs
Software Requirements Before using the iCEblink40 board, please be sure to download and install iCEcube2 release 2011.12 or later. This and later versions include the programming software for the iCEblink40 board. Currently, the programming software is only available for the Windows operating system. http://www.latticesemi.com/products/designsoftware/icecube2/downloads.cfm
During the installation process, be sure to install the Adept USB Programming Software, as shown in Figure 2.
1. Make sure that Adept USB Programming Software is checked. This is the default setting.
2. Click Next.
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Figure 2. Select the Adept Programming Software for Installation
1
2
A few steps later, select the installation for the Adept programming software, as shown in Figure 3.
3. Make sure that both the Adept Runtime and Adept Application options are checked, which are the default settings.
4. Click Next.
Figure 3. Adept Setup Options
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4
Connecting to the iCEblink40 Evaluation Board Before connecting the iCEblink40 board, be sure to download and install a supported version of the iCEcube2 soft- ware.
Connect the iCEblink40 evaluation board to your PC using the USB cable provided. The USB connector on the board is labeled with reference designator J3 and is located in the upper left corner. Once connected, the red power-good LED (LD1) adjacent to the USB connector illuminates. See Figure 4 to locate the power-good LED.
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Power and Configuration Status LEDs The iCEblink40 evaluation board has two status LEDs, as shown in Figure 4. These two status LEDs indicate the current status of the iCEblink40 board, as listed in Table 1. The red LED, LD1, located near the USB connector indi- cates if the USB power supply, the 3.3V supply, and the 1.2V supply are within the specified ranges.
The yellow LED, LD6, located below the FPGA indicates whether the FPGA is configured properly. This LED lights up when the FPGA is correctly loaded with a valid bitstream.
Figure 4. iCEblink40 Status LEDs Power-Good LED (LD1) (Red LED)
iCE40HX1K VQ100
FPGA Configuration Done LED (LD6) (Yellow LED)
Table 1. iCEblink40 Status LED Descriptions
Power-Good Configuration DONE LED (LD1) LED (LD6) Description The board is powered, the FPGA successfully configured and the FPGA On On application is operating. Board is unpowered. Connect the board to a computer USB port, a pow- ered hub, or a USB-based wall plug. Off Off If board is plugged in and previously operating, indicates that an SPI Flash programming operation is in progress The board is powered but the FPGA is not yet configured. On Off ACTION: Program the onboard SPI Flash PROM with a valid FPGA configuration bitstream. ERROR: The board is powered but there is a problem with the USB Off On power supply or with the on-board regulator.
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Pre-programmed Demonstration Design The iCEblink40 board comes preprogrammed with a demonstration application. The application supports two inter- faces.
1. Control the LEDs from the four capacitive touch buttons on the board itself.
2. Control the LEDs and other internal logic using the USB-based I/O expansion interface. Operating the Capacitive Touch Buttons Upon power up, the green LEDs on the board scroll in an upward pattern, as described in Figure 5. Pressing any of the capacitive touch buttons stops the LEDs from scrolling and places the board in a different operating mode.
Figure 5. Preprogrammed Demonstration Design LEDs Scroll Upward 1. Power On Green LEDs scroll upward.
2. Press any button to enter LED Toggle Mode.
Toggle LED with Button Press
3. Press a button to toggle the associated LED on or off. If no button is pressed within five seconds, the board returns to Scroll LEDs Mode.
In the second operating mode, toggle individual LEDs on and off by pressing the associated capacitive touch but- ton.
If no button was pressed during the last five seconds, the board returns to scrolling the LEDs.
The demonstration application is available for download from the Lattice website at: www.latticesemi.com/iceblink40-hx1k. Virtual I/O Expansion Debugging Interface The iCEblink40 board is powered and programmed via the USB interface. Additionally, the USB interface also pro- vides a convenient means to monitor and control logic inside the FPGA, as shown in Figure 6. The USB controller drives a byte-wide parallel port expander implemented within the FPGA, controlled by software running on the PC. The Digilent ADEPT2 I/O Expansion screen, shown in Figure 7, provides a mix of virtual switches, pushbuttons, LEDs, light bars, and 32-bit input and outputs.
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Figure 6. iCEblink40 Board Supports Virtual I/O Connections over USB Debug I/O Expansion Core
Debug I/O Expansion Core
DB LEDs[7:0] Data[7:0] LightBar[23:0] ASTB Address Strobe USB DSTB FromFPGA[31:0] To/From Data Strobe Controller Switches[15:0] FPGA WRITE Read/#Write Buttons[15:0] WAIT Wait ToFPGA[31:0]
FPGA
Control and monitor FPGA logic values in real-time, over USB, from PC graphical interface
Digilent Adept 2
Figure 7. Digilent Adept 2 I/O Expansion Interface and FPGA Connections
VLightBar
To FPGA [31:0] From FPGA [31:0] 23 0 VLEDs
34567 201
1112131415 10 9 8 1112131415 10 9 8
VButtons VSwitches 567 34 201
34567 201
Using the Virtual I/Os in the Demo Application By default, the virtual I/Os are disconnected and the USB controller’s I/O connections to the FPGA are high-imped- ance (Hi-Z).
To connect the virtual I/O, perform the following steps outlined in Figure 8.
1. From the Windows Start menu, select Start > All Program > Digilent > Adept > Adept.
2. Ensure that the Adept interface connects to the iCE40.
3. Click the I/O Ex tab.
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4. Click Start I/O. Remember, the associated I/O Expander design must be part of the compiled FPGA design before the Virtual I/Os work.
5. If the virtual I/O expansion design is functioning correctly, the green virtual status LED will turn from red to green.
Figure 8. Starting the Digilent Adept Virtual I/O Expansion Application
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3
4 5
To disconnect the virtual I/O interface, simply click the Stop I/O button in the graphical interface. Controlling the Physical LEDs from Virtual I/Os in the Demonstration Design When active, the virtual I/Os optionally control the physical LEDs on the board, as shown in Figure 9. For example, with the virtual I/Os active, change the position of virtual switch [7] (the bottom left switch in the graphical interface). Note how the physical LEDs on the board change direction.
Change virtual switch [6] to the up position. Now, the physical LEDs are controlled by the virtual switches [3:0] and virtual pushbuttons [3:0]. The values of the virtual switches are XORed together inside the FPGA. The virtual slide switches set a specific value for the physical LEDs. The pushbutton momentarily inverts the value while the virtual pushbutton is pressed in the graphical interface.
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Figure 9. Controlling the Physical LEDs from Virtual I/O
Virtual Switches Virtual Pushbuttons [7] [3] [2] [1] [0] [6] 1: Scroll down [3] [2] [1] [0] 1: Control LEDs from Virtual I/Os 0: Scroll up 0: Control LEDs from FPGA
LD2 BTN1
LD3 BTN2 Physical Buttons and LEDs LD4 BTN3
LD5 BTN4 Direction
Controlling the Virtual Light Bar in the Demonstration Design When the virtual I/Os are active, the virtual light bar lights up from left to right, controlled by logic inside the FPGA. The virtual pushbuttons [15] and [14] control the light bar. Pushbutton [15] resets the light bar, clearing all the lights. Pushbutton [14] forces the light bar to hold its current value.
Figure 10. Controlling the Virtual Light Bar Lights Up from Left to Right
Light Bar
[15] [14]
Reset Hold Light Value Bar
Controlling the Virtual LEDs in the Demonstration Design The virtual I/O interface includes eight, round, green LEDs, as shown in Figure 11. The values displayed on these virtual LEDs depends on the settings of virtual switches [9] and [8].
The eight LEDs are separated into left and right halves. When both virtual switches [9] and [8] are Low—the down position—the left LEDs echo the scrolling pattern of the LEDs, regardless if a physical cap-sense button was pressed. Use virtual switch [7] to reverse the direction of these LEDs. The right-most LEDs show the current toggle status of the four physical cap-sense buttons.
Changing virtual switch [8] to High—the up position—the four left-most LEDs then show the current value of the time-out counter than marks the five seconds after pressing a cap-sense button. Press a cap-sense button to reset the timer and note that the toggle status of the physical button changes on the right-most LEDs. The timer resets each time a physical button is pressed. Wait five seconds and the physical LEDs change back to the scrolling pat- tern.
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Figure 11. Controlling the Virtual LEDs LEDs
[9] [8] Scrolling LED Toggle value pattern of physical cap-sense buttons [9] [8] (push button to Cap-sense change) time-out counter
[9][8] [3] [2] [1] [0] [3] [2] [1] [0]
When virtual switch [9] is High—in the up position—then the left LEDs are controlled by virtual switches [3:0] and the right LEDs are controlled by virtual pushbuttons [3:0]. Virtual Values to and from FPGA in the Demonstration Design The virtual I/O interface also includes a 32-bit value from the FPGA logic and a 32-bit value to the FPGA logic, as shown in Figure 12. Two virtual switches, [14] and [15], control the behavior in of the virtual 32-bit values in the demonstration design.
Figure 12. Virtual Values To and From the FPGA
To FPGA From FPGA [13] 0x1000ffff efff0000
Send Format: Hexadecimal Reset
[15] [14] Continuously No function increment
[15] [14] Continuously No function decrement
[15] [14] One’s complement Input value of input value
[15] [14] Reverse bit order Input value of input value
Clocking Resources The iCEblink40 board includes a Linear Technology LT1799 oscillator (X1 on the board and in the schematic) to generate a 3.33 MHz clock. FPGA Input The output from the LT1799 oscillator feeds pin 13 of the iCE40HX1K FPGA. FPGA pin 13 is also the global buffer input GBIN7.
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Supporting Other Frequencies On the iCEblink40 board, the LT1799 produces a 3.3 MHz clock output by default. Other frequencies are possible via simple modifications of the board using the 1x3 connections on JP2, as listed in Table 2.
Table 2. Selecting Other Oscillator Frequencies Using Jumper JP2
Clock Frequency JP2 Setting Jumper Position
3.33 MHz (default) None
333 kHz Upper Position
33.3 MHz Lower Position
User LEDs The iCEblink40 iCE40HX1K evaluation board includes four green user LEDs, located along the left side of the board, as shown in Figure 1. Operation To light a user LED, drive the associated FPGA pin High, as shown in Table 3. To darken the LED, drive the associ- ated FPGA pin Low.
Table 3. User LED Operation
Operation FPGA Action Light LED Drive High (1) Darken LED Drive Low (0)
The LEDs may appear to glow slightly before the FPGA is configured or if the FPGA pin is unused. This is because the FPGA I/Os have a soft pull-up resistor which may provide just enough current for the LED to glow dimly. To completely turn off an LED, drive it Low. FPGA Connections The FPGA drives the user LEDs using the FPGA pins listed in Table 4. These same signals also connect to the J12 header located in the lower left corner.
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Table 4. User LED Connections
Designator Location FPGA Pin Header Connections LD2 LD2 [59] 59 J12.1 LD3 LD3 [56] 56 J12.2 LD4 LD4 [53] 53 J12.3 LD5 LD5 [51] 51 J12.4
Capacitive Touch Buttons The iCEblink40 iCE40HX1K evaluation board has four capacitive-touch buttons, located toward the left side of the board, as shown in Figure 1. These buttons have dedicated connections only to the FPGA. These signals go nowhere else on the board and are not available on any of the breakout headers. FPGA Connections Table 5 lists the four capacitive touch buttons on the iCEblink40 board and the associated FPGA pins.
Table 5. Capacitive Touch Buttons
Designator Location FPGA Pin BTN1 BTN1 [60] 60 BTN2 BTN2 [57] 57 BTN3 BTN3 [54] 54 BTN4 BTN4 [52] 52
Operation Figure 13 shows the circuit used for each capacitive-touch button. Each button is attached to one I/O pin on the FPGA. Each signal line includes a 100 k pull-up resistor to 3.3V and a 100 pF capacitor down to ground.
Figure 13. Example Capacitive Touch Button Circuit
I/O Pin Capacitive Sample Touch Button 100 kΩ
Value 100 pF
Figure 15 shows the general overall flowchart for the demonstration design to read the value on a capacitive touch button.
The sampling signal drives the voltage on the capacitive-touch button to ground in order to bleed of any residual charge as shown in Figure 14. After a period of time, depending on the button sample frequency, the button is allowed to float High.
Once the FPGA output goes to Hi-Z (high-impedance, floating, three-state), the 100k pull-up resistor to 3.3V charges the 100 pF capacitor. After about an RC time constant ( or tau), the voltage on the pad exceeds the input switching threshold of the FPGA. A finger pressed against the capacitive-touch button adds about another 5 pF of capacitance, increasing the RC constant and delaying the Low-to-High transition for a pressed button.
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Figure 14. Capacitive Touch Timing Examples
Sampling Allow pad to Signal Drive pad to ground float High
Button: Switching τ = RC No Finger Threshold BUTTON
Button Value: Time delta between No Finger pressed and unpressed button ~300-500 ns Button: Switching τ = R(C + C ) Finger Press Threshold BUTTON FINGER
Button Value: Finger Press
The switching time difference between an unpressed and one or more pressed buttons is roughly 300 to 500 ns. Using the 3.33 MHz input, this amounts to a one clock delay difference between an unpressed and pressed but- tons.
The simple circuit used on the iCEblink40 board detects simultaneous button presses on up to three of the capaci- tive-touch buttons. Pressing all four buttons is the same as pressing no buttons.
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Figure 15. iCEblink40 Demo Application Capacitive Touch Button Flowchart
Start
Drive pin connected to capacitive button Low long enough to guarantee that the pin is at GND, despite the attached RC network.
Force pin to Hi-Z. The external pull-up resistor pulls the pin High and charges the capacitor.
Did any pin go High?
Yes
Wait one 3.3 MHz clock period (300 ns).
Sample all pin values.
Are all Yes buttons High?
Did pin No value change from last sample?
Yes
Toggle pin value
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User I/O Connections Figure 16 shows the location of the 3.3V-compatible digital I/O connections on the iCEblink40 board. Each connec- tion shows the pin number of the FPGA I/O pin that attaches to the connection. Likewise, Table 6 lists the various I/O headers and their designed usage.
Figure 16. Location of the 3.3V Digital I/O Connections and the FPGA Pin Number Digital I/O (3.3V) 3.3V Arduino Shield Compatible GND [86] [83] [81] [79] [74] [72] [69] [66] [18] [12] [99] [96] [94] [91] [89] Digital I/O (3.3V)
3.3V [87] [85] [82] [80] [78] [73] [71] [68] GND [19] [16] [15] [97] [95] [93] [90] SPI PROM [100] [1] [7] Connections [2] [8] [3] [9] [49] [4] [10] [45] [46] PMOD PMOD [48] PMOD12 GND 3.3V 3.3V GND PMOD Double PMOD12 [33] [20] [28] [21] [27] [24] [26] [25] PMOD PMOD PMOD12
[13] GND 3.3V GND [30] [36] [40] [42] [62] [64] 3.3V [51] [53] [56] [59] [33] PMOD PM OD Clocks
User LEDs PMOD12 PM OD Double PMOD 12 Double-wide Digilent 2x6 Header [29] [34] [37] [41] [63] [65] PMOD12 Digilent 2x6 Header Digital I/O (3.3V) PMOD Digilent 1x6 Header
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Table 6. Digital I/O Headers and Their Functions
I/O Header Header Group Type Location Function J2 2x8 0.1” centers Top edge, middle 3.3V digital I/O. Compatible with 3.3V Arduino Shield boards. J4 2x8 0.1” centers Top edge, left side 3.3V digital I/O. Compatible with 3.3V Arduino Shield boards. 3.3V digital I/O. 3.3V digital I/O. Compatible with Digilent 1x6 and J1 2x6 0.1 centers Left edge, top 2x6 PMod modules. Also supports double PMod12 modules when used with header J6. 3.3V digital I/O. Compatible with Digilent 1x6 and 2x6 PMod mod- J6 2x6 0.1 centers Left edge bottom ules. Also supports double PMod12 modules when used with header J1. J7 1x6 0.1 centers offset Left edge, top Production programming of USB controller. 3.3V digital I/O. Connections between the mobile FPGA and the J11 1x6 0.1 centers offset Middle, toward left SPI PROM. Compatible with Digilent 1x6 PMod modules. 3.3V digital I/O. Portions compatible with Digilent 1x6 and 2x6 J5 2x8 0.1” centers Bottom edge, right side PMod modules. Portions also compatible with 3.3V Arduino Shield boards. Middle, to left of 3.3V digital I/O. Clock connections from the LTC1799 oscillator JP3 1x2 0.1” centers FPGA (GBIN7) and possible into GBIN2. 3.3V digital I/O. Connections to the user LED I/O. Compatible J12 1x6 0.1” centers Bottom edge, left side with Digilent 1x6 Pmod modules.
Supported Pmod Peripheral Modules As shown in Figure 16, the iCEblink40 board supports a variety of Pmod peripheral modules for easy I/O expan- sion. Table 7 lists the 0.1” through-hole headers on the iCEblink40 board that support Pmod modules. Pmod mod- ules come in a few different form factors and each Pmod header includes power and ground supplies. Figure 17 shows the how the different Pmod form factors interrelate. The easiest way to support a Pmod module is to add the appropriate female socket listed, or an equivalent. Straight-through or right-angle through-hole sockets are listed. Male headers are also possible solutions when using the interface cable provided with most Pmod modules.
Table 7. Pmod Module Headers
Female Socket (Manufacturer/Part Number) Header Type Straight-through Right-angle 2x6 header on 0.1” centers. Each is a Pmod12 header that Sullins Connector Sullins Connector J1, J12 supports two six-pin Pmod modules. Both together form a Solutions Solutions double-wide Pmod connection. PPPC062LFBN-RC PPPC062LJBN-RC 2x8 header on 0.1” centers. The left side of header J5 forms Sullins Connector Sullins Connector a Pmod12 header, as shown in Figure 16. A 2x6 header sim- J5 Solutions Solutions ilar to J1, J12 can also be used but must be mounted toward PPPC082LFBN-RC PPPC082LJBN-RC the right end of the holes as marked.
As shown in Figure 17, a Pmod module has six connections—four I/O plus power and ground. A Pmod12 module has 12 connections and the module is effectively two six-pin Pmod modules stacked together. Finally, a double- wide Pmod12 consists of two Pmod12 headers spaced apart. Most of the Pmod modules also include interface cables to allow easy connection to other header types.
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Figure 17. Pmod Module Types Pmod12
Pmod 3.3V I/O GND
I/O 3V GND 3. 11 Pmod12 Pmod Pmod
Double-wide Pmod12 3.3V 3.3V GND I/O I/O GND
1 1 Pmod12 Pmod12 Pmod Pmod Pmod Pmod
For a complete list of Pmod peripheral modules, visit the Digilent web site. www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9 Arduino Shield Board Support The iCEblink40 board also mechanically and electrically supports select 3.3V Arduino Shield boards popular in the microcontroller development community. The Shield connections are located on headers J4, J2, J8 and a portion of J5 as shown in Figure 18. Headers jumper J4 and J2 are 3.3V digital I/O connections. Header J8 provides power connections to the Shield board. The left side of header J5 also provides 3.3V digital I/O but the 3.3V and GND connections do not connect to the Shield board.
Figure 18. Arduino Shield Board Connections Arduino Shield Connections
iCE40HX1K VQ100
Required Header Sockets To support Arduino Shield boards, the indicated headers must be loaded with female socket headers on 0.1” head- ers, as listed in Table 19.
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Table 8. Sockets to Support Arduino Shield Boards
Header(s) Description Quantity Manufacturer/Part Number Sullins Connector Solutions J2, J4, J5 2x8 female header socket on 0.1” centers 3 PPPC082LFBN-RC Sullins Connector Solutions J8 1x6 female header socket on 0.1” centers 1 PPPC061LFBN-RC
Tested Arduino Boards Figure 19 shows the Arduino Shield boards have been tested for basic compatibility. Other Arduino Shield boards may also be compatible.
Figure 19. Compatible Arduino Shield Boards
chipKITBasic I/O Shield chipKIT Pmod Shield-Uno
USB Interface The iCEblink40 board is powered by connecting the board to a computer USB port, a power USB hub, or a USB- based AC adapter, commonly used in consumer electronics. A typical USB port provides up to 500 mA at 5V, pro- viding up to 2.5W of total power. The iCE40HX1K consumes SIGNIFICANTLY LESS power, even when operating at full performance. However, be careful when using the board to power off-board peripheral funds. Connector The USB connector to the board is located in the upper left corner, labeled J3. The board connects using a stan- dard USB cable with a male mini-B connector. Power Supply Figure 20 shows the iCEblink40 power supply circuit that derives power from the USB mini-B connector (J3). The USB connector provides up to 500 mA at +5V DC. An Analog Devices ADP2140 regulator generates +1.2V for the FPGA core VCC and +3.3V for all I/O connections. The regulator also indicates when power is good and lights up the red power-good LED (LD1).
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Figure 20. iCEblink40 USB Power Supply Circuit
Power-Good LED (LD1) Mini-B USB +5V Connector (J3) (500 mA)
Analog Devices (JP1) iCE40HX1K ADP2140 +1.2V VCC FPGA Voltage (300 mA) Regulator
+3.3V VCCIO (600 mA)
Configuration Done LED (LD6)
Jumper JP1 provides a convenient location from which to measure core power to the FPGA. SPI Flash Programming The USB interface also provides Flash programming for the on-board SPI PROM, as described in “Programming the iCEblink40 Board” below.
Digilent Parallel Port (DPP) The Digilent Parallel Port (DPP) interface is used for virtual I/O and debugging using a USB connection to the board from a Windows PC. See “Virtual I/O Expansion Debugging Interface” on page 5 for additional information. 1Mbit SPI Configuration PROM The configuration bitstream for the iCE40 FPGA is stored in a M25P10A 1Mbit SPI serial Flash PROM. The PROM is large enough to hold two configuration images and supports the iCE40 WarmBoot feature, if so enabled within the FPGA application. The PROM is physically located on the back side of the board. Programming the iCEblink40 Board The iCEblink40 board includes on-board USB-based programming support either from the Lattice iCEcube2 soft- ware or using a command from a console window or DOS box. From iCEcube2 Figure 21 shows the command sequence for programming the SPI Flash PROM on the iCEblink40 board using the iCEcube2 development software.
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Figure 21. Programming the iCEblink40 Board from iCEcube2
3
1 4
2
5
6
1. Select Tool > Programmer from the iCEcube2 menu bar.
2. Click the dropdown button ( ) under Programming Hardware.
3. Select iCEblink40.
4. The bitstream file should already be set appropriately based on the iCEcube2 project settings. If not, click Image Files Settings to select the configuration bitstream file.
5. Click Execute to program the iCEblink40 board.
If all is working correctly, the power-on LED and the configuration done LED will both go out momentarily as iCEcube2 programs the on-board SPI Flash PROM. After programming is complete, both LEDs should light up again and the FPGA will execute the new configuration image. From Command Line The iCEblink40 programming software can also be executed from a console window or DOS box. To open a con- sole window or DOS box, click the Start button and type cmd in the textbox immediately above the Start button.
Executable Location After installation, the programming software executable is called iceutil.exe and is located in the \Sbt- Tools\sbt_backend\bin\win32\opt directory. The iecutil.exe executable can be copied into the same directory as the FPGA bitstream image or can be pointed to on the command line.
FPGA Bitstream Configuration File The required bitstream image is part of the iCEcube2 project. Multiple versions of the bitstream are stored in the
Raw Hexadecimal Command Example
Intel Hexadecimal Command Example
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Help
Note: The iCEblink40 HX1K evaluation board uses an early version of the iCE40HX1K silicon that has higher than expected static current consumption. Although the demonstration application consumes less than 500 µA, the pro- duction silicon will consume even less current. Similarly, the lower power iCE40LP1K devices use even less power than the iCE40HX1K FPGA. Easy Method Using a Multimeter Connect the iCEblink40 board through your high-accuracy multimeter. Use a meter with a minimum of 10,000 counts; 50,000 counts or more is recommended for better accuracy.
To take a quick measurement, follow these steps.
1. Disconnect power to the iCEblink40 board by removing the USB cable connection, either at the board or at the computer.
2. Remove the jumper JP1, which isolates the FPGA’s core supply from the 1.2V supply on the board.
3. Connect your multimeter’s alligator or test clips to the stake pins on header JP1.
4. Configure the multimeter to measure current using its highest mA or Amp range. This setting typically has the lowest voltage drop internally within the meter.
5. Re-connect the USB cable that supplies power to the iCEblink40 board and configure the FPGA device if nec- essary.
6. Observe the power reading on the multimeter. At low clock rates, which results in lower power consumption, switch the meter to a lower amperage setting for better accuracy. However, this also may increase the resis- tance across the meter leads. Using too low of a meter setting causes a large voltage drop within the meter, potentially violating the minimum input voltage specification to the FPGA device.
7. The value measured by the multimeter is a current. Convert the measurement to power using Equation 1. The voltage is the operating voltage, the voltage across the jumper. This value can be accurately measured with a second multimeter to show the voltage drop across the first. However, just measuring the initial voltage, before taking any current readings, usually provides acceptable accuracy and the voltage drop across the meter is generally small.
Power= Current Voltage (1)
Although this method is easy, here are a few caveats and pointers.
• Always start at the highest current setting for your meter. Using too small a setting may damage your meter! After determining the maximum current range for your measurement, then you can safely use the appro- priate lower current setting. • The voltage drop across the meter leads may violate the minimum supply voltage specification for the mobile- FPGA device. To determine the voltage drop, use a second multimeter to measure either the voltage across the first meter’s leads during a test or the resistance between the first meter’s leads. • Using the highest current measurement setting typically results in the lowest voltage drop.
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Using High-Precision, Small-Value Resistors For more-accurate, time-sensitive measurements, place a low-value resistor across the jumper test point. Accord- ing to Ohm’s Law, the current passing through the resistor produces a voltage drop. Measure the voltage differen- tial across the resistor during expected operation. Convert the measurement to power using Equation 2. The voltage is the measured voltage across the resistor; the resistance is the value of the resistor. 2 Voltage Power = ------(2) Resistan ce The following are a few guidelines on selecting a resistor.
• Use a high-precision resistor. • The resistor must handle the power dissipated under the anticipated test conditions. • Too small a resistor value may result in too small a voltage difference across the resistor to measure with your test equipment. • Too large a resistor value may result in too large of a voltage difference across the resistor. Too large a voltage drop might violate the minimum voltage specifications for the FPGA device.
Figure 22 shows an example header block designed to fit over one of the jump locations. Measure the voltage drop across the low-value resistor, either with a voltmeter or with data acquisition equipment.
Figure 22. Resistor Header Block
Voltmeter
Low Ω, High Precision Resistor
This method is recommended for taking power measurements over time. Mechanical Specifications Figure 23 shows the mechanical dimensions for the iCEblink40 board, including the location of the four mounting holes. With a jumper installed on JP1, the board height is approximately 0.700 inches high, including the four rub- ber feet mounted on the bottom side of the board.
21 iCEblink40-HX1K Evaluation Kit User’s Guide
Figure 23. iCEblink40 HX1K Board Mechanical Dimension
iCE40HX1K VQ100
Ordering Information
China RoHS Environment-Friendly Description Ordering Part Number Use Period (EFUP) iCEblink40-HX1K Evaluation Kit ICE40HX1K-BLINK-EVN
Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: [email protected] Internet: www.latticesemi.com Revision History Date Version Change Summary May 2012 01.0 Initial release. September 2012 01.1 Nomenclature change from “mobileFPGA” to “FPGA”.
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
22 iCEblink40-HX1K Evaluation Kit User’s Guide
Appendix A. Schematic Figure 24. Schematic B C D A n n n n o o o o tt tt tt tt u u u u B B B B p p p p a a a a 1/1 CapButton C CapButton C CapButton C CapButton C BTN1 No Load BTN2 No Load BTN3 No Load BTN4 No Load SK/GA f 1 1 1 1 6 6 5% 5% 5% 5% C5 100pF C27 100pF C28 100pF C36 100pF R2 100K R9 100K R18 100K R29 100K GND GND GND GND VCC_ 3V3 VCC_ 3V3 VCC_ 3V3 VCC_ 3V3 LD2 LD3 LD4 LD5 CAP BTN1 CAP BTN2 CAP BTN3 CAP BTN4
J5 8 x 2
390 390 390 390 1 R5 R11 R22 R31 2
3 4
D N G D GN
5
VCC_ 3V3 6 6013-500-002 B.0
IMOD-2 IMOD-1
7 8
4 - MOD I 3 OD- IM les. 1 2 3 4 5 6
10
9 LED1 LED2 LED3 LED4
1x6 0 B D - 0 E4 -DB1 40 E iC
iC J12
11 12
0-DB2 4
C4-B iCE iCE40-DB3 Number Revision
13 14
B4 D iCE40- iCE40-DB5
15 16
iCE40-DB6 iCE40-DB7 NOT STUF FED NOT STUF FED LED1 LED2 LED3 LED4 iCEblink40HX1 Evaluation Kit GND
Tabloid
1 2
J2 Title Size Date:File: 5/3/2012 C:\Users\..\iCE4 0_Ev al_Board.SchDoc By: Drawn o Sheet
8 x
2 sa field y SiliconBlue 1x2
J10
2
1 NOT STUF FED 1 0 2- C DS 2-02 C DS
4
3 VCC_ 3V3
-03 2 DSC DSC2-04
5 6
DSC2-05
DSC2-06 1 2 3 4 5 6
quested b
8
7 NOT STUF FED
1x6 7 DSC2-0 2-08 C
ield. DS
J11 JP3 R39 0
9 0 1
DSC2-09 DSC2-10 C18 10nF
11 5 12 5
DSC2-11 DSC2-12
13 14
DSC2-13
DSC2-14 Foot Foot
5 1
NOT STUF FED 16 F2 F4 DSC2-15 DSC2-16 C17 10nF Basic I/O sh Basic NOT STUF FED iCE4 0-SS_B iCE4 0-SCK GND VCC_ 3V3 DSC2-07 DSC2-06 DSC2-05 DSC2-04 DSC2-03 DSC2-02 DSC2-01 IM OD-1 IM OD-2 IM OD-3 IM OD-4 CAP BTN1 LED1 CAP BTN2 LED2 CAP BTN3 LED3 CAP BTN4 LED4 iCE4 0-WAIT SYS CLK iCE4 0-SO iCE4 0-SI
J4
2x8 M25P10-SS_B iCE4 0-SS_B
C16 0.1uF
1 2
1 0 1- SC D 1-02 C
DS Foot Foot
4
3 GND F1 F3
C DS -03 1 DSC1-04
5 6
DSC1-05 63 62 DSC1-06 74 73 72 71 69 68 66 65 64 60 59 57 56 54 53 52 51 C15 1uF
8
7 re PMOD support SPI Optional
7 -0 1 DSC -08 C1 S D
9 10
9 -0 1 SC D -10 1 SC D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
11
12 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO DSC1-11
DSC1-12 P P
PIO1 P PIO1 P PIO1 P PIO1 P PIO1 P PIO1 P PIO1 P PIO1 P PIO1 P PIO1 P PIO1 P PIO1 P PIO1 P PIO1 P PIO1 P PIO1 P PIO1 P 14
13 / /
SC1-14 D
GND R36 10K
2 3 15 16 1 _ O I C C V
NOT STUF FED VCCIO_1
5 1 C1- S D -16 1 C DS 67 N N
_ O I C C 1 1 CCIO_ V
V BI BI M echanically with compatible 58 GBIN2G /PIO1 GBIN3G /PIO1 IC2 D iCE4 0VQ1 00 HLD GND 2 7
iCE4 0-SS_B iCE4 0-SI NOT STUFFED NOT IC4 SDO
M25P10-AVM N6
HOLD 1 2 3 4 5 6
GND VCC
1x6 4 J8 8 GND VCC_ 3V3 C26 10nF
GND
C40 10nF SDI SCK WP CS
B _ S S _ I P S / / / S O I PIOS/SPI_SS_B P
49 5 6 3 1 C25 10nF
C
0 O I PIO0 P K CK C S _ I P S / / / S O I PIOS/SPI_ P
4 S 4
SC2-08 D 78 48 C39 1uF
VC D1 SB0503EC-TR
I / / / 0 O O0 I P P I S _ I P SPI_SI S / S O I P
iCE4 0-CRES ET VCC_ 3V3 US B5V0 PIOS _
9 7 46 -09 2 SC
D I
0 O I PIO0 P O S _ I PI_SO P S / / / S O I PIOS/ P
P S
80 5 4 0
DSC2-1 C24 10nF SPI_VCC S
0 O I P
PIO0 GND IC2 C iCE4 0VQ1 00 WP
81
DSC2-11 10K R33
0 0 O I PI P O
82 2 1 - 2 SC D
50 0 I
0 O O I P P
3 DSC2-1 83 C34 10nF
I 0 O0 O I P P
DSC2-14
85 10K R34
I 0 O O0 I P
P GND
75 11 35 61 77 DSC2-15 86 76 C23 10nF VCC_ CORE
0 I 0 O O I P P
7 8 SC2-16 D C33 1uF
I 0 O0 O I P / 1 N I B GBIN1/P G
T
DSC1-01 89 5
C C C C
0 O I P / 0 N I B G GBIN0/PIO0 V S
DSC1-02 90 2
C22 0.1uF A
VCC VC VCC VC VCC VC VCC VC
_ 0 O I P
PIO0 F
SC1-03 D 1 9 P
_
0 O I P PIO0 P P
4 0 - 1 SC D
93 VPV P_2V5
P
0 I
0 O O I P
P VPV P_FAS T
DSC1-05 94 C21 0.1uF
R27 4.7K
I 0 O O0 I P P
DSC1-06 95
0 0 O I PI P
O 0 0
D D D D D D D D D D 07 - DSC1 96
0 O I P
PIO0 _ _
LD6 iCE4 0-SO iCE4 0-SCK M25P10-SS_B
DSC1-08 97 C20 1uF GND GN GND GN GND GN GND GN GND GN GND GN GND GN GND GN GND GN GND GN
O O
R26 4.7K R30 10 I 0 O0 O I P
P I
IC2 F iCE4 0VQ1 00 iCE40HX1K
DSC1-09 99
0 I 0 O O I P
P CCI
GND
DSC1-10 100 5 VCCIO_VCC 0 VCCIO_V 0
B _ T E S E R C
17 23 32 39 47 55 70 84 98 CRESET_B
IC2 E iCE4 0VQ1 00
SET RE -C iCE40 C19 1uF 44
E N O D C
GND CDONE iCE40-CDONE 43
88 92 GND
1 L E S B C / / / 2 O I PIO2/CBSEL1 P
0 -DB 0 E4 iC 42
L C 0 0 L E S BSE B C / / / 2 O I P
VCC_ 3V3 PIO2/
iCE40-DB1 41
2 O I P
VCC_ 3V3 PIO2
CE40-DB2 i C9 10nF 40
2 O I PIO2 P
3 -DB 0 E4 iC 37
2 O I PIO2 P
iCE40-DB4 VCC_ CORE 36
2 B 2 O I P PIO / 4 4 N I I B G G / N
CE40-DB5 i C8 10nF 34
2 O I P / 5 N I B GBIN5/PIO2 G
IT A -W 0 E4 iC 3
3 3 3
2 O I P
GND PIO2
iCE40-DB6
JP1 30
2 2 O I P
2 2 PIO
CE40-DB7 i
C7 0.1uF 29
3 _ O I C C V 2 O I PIO2 P
VCCIO_3 _ _
No Load
E T E40-WRI iC 8 2
C2 1uF 22
O O
3 _ O I C C V 2 O I PIO2 P
VCCIO_3 B A iCE40-DSTB 27
14 J6
4 5
I 2 1 6 R40 0 3 _ O_ O I C C VCC V 2 O I PIO2 P
3 0 0 CE40-ASTB i 26
C6 1uF 6 VCCIO_VCCI 2 VCCIO_VCCI 2
P P
11
SHUNT IC2 B iCE4 0VQ1 00 5
DG N G
/D /D ND
10
VCC_ 3V3 4
3 3 A B A B A B A B A B A B A B A B T AI -W 3-4 D O M P
0 0 1 1 2 2 3 3 4 5 6 6 7 7 8 8 iCE40
31 38 3 IO IO 9
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PMOD3-3 L1 1uH iCE40-WRITE P P
P P P P P P P P P P P P P P P P
/ /
8
D D D D D D D D D D D D D D D D 2
STB -D 3-2 D O M P
C4 10uF iCE40 / / / / / / / / / / / / / / / /
7 6
7
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 Double Wide PMOD Wide Double Power Measurement Test Point Test Measurement Power
N N
B -AST 40 E 3-1 D O M P I I iC C14 10nF
2x6 od B B Pm IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VCC_ 1V2 PIO3/DP00AP PIO3/DP00BP PIO3/DP01AP PIO3/DP01BP PIO3/DP02AP PIO3/DP02BP PIO3/DP03AP PIO3/DP03BP PIO3/DP04AP GBIN7G /PIO3/DP04B GBIN6G /PIO3/DP05A PIO3/DP05BP PIO3/DP06AP PIO3/DP06BP PIO3/DP07AP PIO3/DP07BP PIO3/DP08AP PIO3/DP08BP C32 10nF IC2 A iCE4 0VQ1 00 2 6 4 1 2 3 4 7 8 9 C13 10nF 10 12 13 15 16 18 19 20 21 24 25 B C31 10nF 2 W FB F T IC1 SW S
C12 10nF
VOUT2 VOU D N G P
PGND NOT STUF FED
1 C30 0.1uF
J1
D D N G G 12 6
N GND
P
D N G A 11 5
AGND GND GND
G D N G 3
C11 0.1uF ND
10
VCC_ 3V3 4
DSC1-11 DSC1-12 DSC1-14 DSC1-15 DSC1-16
PMOD2-4 PMOD2-3 PMOD2-2 PMOD2-1 PMOD1-4 PMOD1-3 PMOD1-2 PMOD1-1 SYS CLK PMOD3-4 PMOD3-3 PMOD3-2 PMOD3-1 PMOD2-4
C29 1uF PMOD1-4
3
1 2 9 Mechanically compatible with Mechanically compatible
PMOD2-3 1 2 PMOD1-3
8
G 2 IN IN N N
ADP 2140ACP Z3312R7
P OD1-2 M D2-2 VIN1 V VIN2 V PG P EN1 E EN2 E C10 1uF PMO
7 1
PMOD2-1 PMOD1-1
2x6 od Pm 5 9 8 7 10 GND VCC_ 3V3 JP2 2 2 US B-ON SYS CLK C1 8.2uF NOT STUF FED DIV 5 4 US B5V0 33.33 MHz LD1 iCE4 0-SS_B iCE4 0-SCK iCE4 0-SO iCE4 0-SI iCE4 0-CRES ET iCE4 0-CDONE iCE4 0-AS TB iCE4 0-DS TB iCE4 0-WRITE iCE4 0-WAIT iCE4 0-DB0 iCE4 0-DB1 iCE4 0-DB2 iCE4 0-DB3 iCE4 0-DB4 iCE4 0-DB5 iCE4 0-DB6 iCE4 0-DB7 15pF C43 T V 4.7K R1 R3 10 I U DIV D OUT O scilla tor R13 200 R15 200 R17 200 R20 200 R23 200 R25 200 VCC_ 3V3 IS P-RES ET D T R7 75 R10 200 N E + V+ V SET S GND G R12 200 R14 200 R16 200 R19 200 R21 200 R24 200 X2 8MHz Ba sic o X1 LTC1 799CS 5#TRP BF DIV= OPENDIV= VCC_ 3V3 DIV= GND 3.33 (DEFAULT) MHz 333 kHz 1 3 2 C42 15pF R6 75 R8 200 R35 200 R32 10k Power-On LED Power-On iCE4 0-CRES ET R28 3.0K 2 1 24 IC3 D GND US B5V0
AT9 0US B2
C35 0.1uF
C AVC UGND
8 2
32 XTAL1 CE
GND US B-S S_B US B-S CK US B-M OSI US B-M IS O
C C V D PA
VCC_ 3V3 U D+ D- US B5V0 GND
1 3 PC1/RES ET P PC0/XTAL2
C VC GND
4 3 US B-ON US B-AS TB US B-DS TB US B-WRITE US B-WAIT US B-DB0 US B-DB1 US B-DB2 US B-DB3 US B-DB4 US B-DB5 US B-DB6 US B-DB7 ROHS D-/SDATA D+/SCK VCAP 22 19 20 16 8 17 14 18 7 10 6 9 23 21 11 12 15 25 13 5 26 C44 0.1uF 5 1 3 S1 4 2 S2 1 2 3 4 5 6 30 29 27 1 1 1x6 C41 1uF J7 IC3 B IC3 A IC3 C 0.1uF C38 G V S1 ID D- S2 D+ PD4/INT4 22 R37 C37 0.1uF Chinese ROHS Chinese PB5/PCINT5 PB6/PCINT6 NOT STUF FED AT9 0US B2-16MU PC2/PCINT1 1 PC4/PCINT1 0 S3 S4 PD6/RTS /INT6 R38 22 USAB Mini B PB0/SS/PCINT0 PB4/T1/PCINT4 PD1/AIN0 /INT1 J3 PD0/OC0B/INT0 PD3/TXD1 /INT3 1nF/250V C3 AT9 0US B2 AT9 0US B2 AT9 0US B2 PB1/SCLK/P CINT1 PC5/OC1B/PCINT9 PC6/OC1A/PCINT8 PD5/XCK/P CINT1 2 S3 S4 IS P-RES ET US B-M OSI US B-M IS O US B-S CK GND US B3V3 Atmel Programming USB Block PC7/INT4 /ICP 1/CLK0 PD2/RXD1 /INT2 /AIN1 PB2/PDI/M OSI/PCINT2 US B3V3 GND US B5V0 US B3V3 GND D- D+ PD7/CTS /HWB/T0 /INT7 PB3/PDO/MIS O/PCINT3 1M R4 PB7/OC0A/OC1 C/PCINT7 AT9 0US B2-16MU AT9 0US B2-16MU AT9 0US B2-16MU GND GND Lattice Semi Lattice B C D A
23 iCEblink40-HX1K Evaluation Kit User’s Guide
Appendix B. Bill of Materials (Major Components) Table 9. Bill of Materials
Reference Vendor Part Number Description IC2 Lattice Semiconductor iCE40HX1K-VQ100 iCE40 HX-series FPGA IC1 Analog Devices ADP2140ACPZ3312R7 Low-quiescent buck/LDO regulator (1.2V, 3.3V) X1 Linear Technology LTC1799CS5#TRPBF Oscillator IC4 Micron Technology M25P10-AVMN6 1Mbit SPI serial configuration Flash PROM IC3 Atmel Corporation AT90USB162-16MU USB programming and debugging interface
24