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IBM Gekko RISC Microprocessor User's Manual

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IBM Gekko RISC Microprocessor User's Manual IBM Gekko RISC Microprocessor User’s Manual Version 1.2 May 25, 2000 IBM Confidential Trademarks The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both: IBM IBM Logo PowerPC AIX PowerPC 750 Gekko Other company, product, and service names may be trademarks or service marks of others. Document History Date Description Preliminary Edition 3/29/00 Initial release of new format 2nd Preliminary Edition 4/18/00 Minor changes, most are transparent to user (removal of conditional text, etc.) 3rd Preliminary Edition 5/25/00 Minor change in section 4.5.6 This unpublished document is the preliminary edition of IBM Gekko RISC Microprocessor User’s Manual. This document contains information on a new product under development by IBM. IBM reserves the right to change or discontinue this product without notice. © 2000 International Business Machines Corporation . All rights reserved. CONTENTS Chapter 1 Gekko Overview 1.1—Gekko Microprocessor Overview - - - - - - - - - - - - - - - - - - - - - - - 1-1 1.2—Gekko Microprocessor Features - - - - - - - - - - - - - - - - - - - - - - - - 1-4 1.2.1—Overview of Gekko Microprocessor Features - - - - - - - - - 1-4 1.2.2—Instruction Flow - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1-6 1.2.2.1—Instruction Queue and Dispatch Unit - - - - - - - - 1-7 1.2.2.2—Branch Processing Unit (BPU) - - - - - - - - - - - - 1-7 1.2.2.3—Completion Unit - - - - - - - - - - - - - - - - - - - - - - 1-8 1.2.2.4—Independent Execution Units- - - - - - - - - - - - - - 1-9 1.2.3—Memory Management Units (MMUs)- - - - - - - - - - - - - - - 1-10 1.2.4—On-Chip Level 1 Instruction and Data Caches - - - - - - - - - 1-11 1.2.5—On-Chip Level 2 Cache Implementation - - - - - - - - - - - - - 1-12 1.2.6—System Interface/Bus Interface Unit (BIU) - - - - - - - - - - - 1-12 1.2.7—Signals - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1-14 1.2.8—Signal Configuration - - - - - - - - - - - - - - - - - - - - - - - - - - 1-15 1.2.9—Clocking - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1-15 1.3—Gekko Microprocessor: Implementation - - - - - - - - - - - - - - - - - - 1-16 1.4—PowerPC Registers and Programming Model - - - - - - - - - - - - - - - 1-18 1.5—Instruction Set - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1-23 1.5.1—PowerPC Instruction Set- - - - - - - - - - - - - - - - - - - - - - - - 1-23 1.5.2—Gekko Microprocessor Instruction Set - - - - - - - - - - - - - - 1-24 1.6—On-Chip Cache Implementation - - - - - - - - - - - - - - - - - - - - - - - - 1-25 1.6.1—PowerPC Cache Model - - - - - - - - - - - - - - - - - - - - - - - - 1-25 1.6.2— Gekko Microprocessor Cache Implementation - - - - - - - - 1-25 1.7—Exception Model - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1-25 1.7.1—PowerPC Exception Model- - - - - - - - - - - - - - - - - - - - - - 1-25 1.7.2—Gekko Microprocessor Exception Implementation - - - - - - 1-27 1.8—Memory Management - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1-28 1.8.1—PowerPC Memory Management Model - - - - - - - - - - - - - 1-28 1.8.2— Gekko Microprocessor Memory Management Implementation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1-29 1.9—Instruction Timing - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1-29 1.10—Power Management - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1-31 1.11—Thermal Management - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1-32 1.12—Performance Monitor - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1-33 Chapter 2 Programming Model 2.1—Gekko Processor Register Set - - - - - - - - - - - - - - - - - - - - - - - - - 2-1 2.1.1—Register Set - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2-1 2.1.2—Gekko-Specific Registers - - - - - - - - - - - - - - - - - - - - - - - 2-8 2.1.2.1—Instruction Address Breakpoint Register (IABR) - - - - - - - - - - - - - - - - - - - - - - 2-8 2.1.2.2—Hardware Implementation-Dependent Register 0- - - - - - - - - - - - - - - - - - - - - - - - - - - 2-8 2.1.2.3—Hardware Implementation-Dependent IBM Gekko RISC Microprocessor User’s Manual IBM Confidential 5/25/00 Page iii CONTENTS (Continued) Register 1- - - - - - - - - - - - - - - - - - - - - - - - - - - 2-12 2.1.2.4—Hardware Implementation-Dependent Register 2- - - - - - - - - - - - - - - - - - - - - - - - - - - 2-13 2.1.2.5—Performance Monitor Registers - - - - - - - - - - - - 2-14 2.1.2.6—Instruction Cache Throttling Control Register (ICTC) - - - - - - - - - - - - - - - - - - - - - - 2-19 2.1.2.7—Thermal Management Registers (THRM1–THRM3) - - - - - - - - - - - - - - - - - - - - 2-19 2.1.2.8—Direct Memory Access (DMA) registers - - - - - - 2-22 2.1.2.9—Graphics Quantization Registers (GQRs) - - - - - 2-23 2.1.2.10—Write Pipe Address Register (WPAR)- - - - - - - 2-24 2.1.2.11—L2 Cache Control Register (L2CR)- - - - - - - - - 2-25 2.2—Operand Conventions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2-27 2.2.1—Data Organization in Memory and Data Transfers - - - - - - 2-27 2.2.2—Alignment and Misaligned Accesses - - - - - - - - - - - - - - - 2-27 2.2.3—Floating-Point Operand and Execution Models—UISA - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2-28 2.3—Instruction Set Summary - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2-32 2.3.1—Classes of Instructions - - - - - - - - - - - - - - - - - - - - - - - - - 2-33 2.3.1.1—Definition of Boundedly Undefined - - - - - - - - - 2-33 2.3.1.2—Defined Instruction Class - - - - - - - - - - - - - - - - 2-33 2.3.1.3—Illegal Instruction Class - - - - - - - - - - - - - - - - - 2-33 2.3.1.4—Reserved Instruction Class - - - - - - - - - - - - - - - 2-34 2.3.1.5—Gekko’s Implementation- Specific Instructions - - - - - - - - - - - - - - - - - - - 2-34 2.3.2—Addressing Modes- - - - - - - - - - - - - - - - - - - - - - - - - - - - 2-35 2.3.2.1—Memory Addressing - - - - - - - - - - - - - - - - - - - 2-35 2.3.2.2—Memory Operands- - - - - - - - - - - - - - - - - - - - - 2-35 2.3.2.3—Effective Address Calculation - - - - - - - - - - - - - 2-35 2.3.2.4—Synchronization - - - - - - - - - - - - - - - - - - - - - - 2-36 2.3.3—Instruction Set Overview - - - - - - - - - - - - - - - - - - - - - - - 2-37 2.3.4—PowerPC UISA Instructions - - - - - - - - - - - - - - - - - - - - - 2-37 2.3.4.1—Integer Instructions - - - - - - - - - - - - - - - - - - - - 2-37 2.3.4.2—Floating-Point Instructions - - - - - - - - - - - - - - - 2-41 2.3.4.3—Load and Store Instructions- - - - - - - - - - - - - - - 2-46 2.3.4.4—Branch and Flow Control Instructions- - - - - - - - 2-58 2.3.4.5—System Linkage Instruction—UISA - - - - - - - - - 2-60 2.3.4.6—Processor Control Instructions—UISA - - - - - - - 2-61 2.3.4.7—Memory Synchronization Instructions—UISA - - 2-64 2.3.5—PowerPC VEA Instructions- - - - - - - - - - - - - - - - - - - - - - 2-65 2.3.5.1—Processor Control Instructions—VEA- - - - - - - - 2-65 2.3.5.2—Memory Synchronization Instructions—VEA - - 2-66 2.3.5.3—Memory Control Instructions—VEA - - - - - - - - 2-67 2.3.5.4—Optional External Control Instructions - - - - - - - 2-69 2.3.6—PowerPC OEA Instructions- - - - - - - - - - - - - - - - - - - - - - 2-70 2.3.6.1—System Linkage Instructions—OEA - - - - - - - - - 2-70 Page iv Version 1.2 IBM Confidential IBM Gekko RISC Microprocessor User’s Manual CONTENTS (Continued) 2.3.6.2—Processor Control Instructions—OEA- - - - - - - - 2-71 2.3.6.3—Memory Control Instructions—OEA - - - - - - - - 2-71 2.3.7—Recommended Simplified Mnemonics - - - - - - - - - - - - - - 2-73 Chapter 3 Gekko Instruction and Data Cache Operation 3.1—Data Cache Organization - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3-3 3.2—Instruction Cache Organization - - - - - - - - - - - - - - - - - - - - - - - - 3-4 3.3—Memory and Cache Coherency - - - - - - - - - - - - - - - - - - - - - - - - 3-5 3.3.1—Memory/Cache Access Attributes (WIMG Bits)- - - - - - - - 3-6 3.3.2—MEI Protocol - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3-6 3.3.2.1—MEI Hardware Considerations- - - - - - - - - - - - - 3-8 3.3.3—Coherency Precautions in Single Processor Systems - - - - - 3-9 3.3.4—Coherency Precautions in Multiprocessor Systems - - - - - - 3-9 3.3.5—Gekko-Initiated Load/Store Operations- - - - - - - - - - - - - - 3-10 3.3.5.1—Performed Loads and Stores - - - - - - - - - - - - - - 3-10 3.3.5.2—Sequential Consistency of Memory Accesses- - - 3-10 3.3.5.3—Atomic Memory References - - - - - - - - - - - - - - 3-10 3.4—Cache Control - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3-11 3.4.1—Cache Control Parameters in HID0 - - - - - - - - - - - - - - - - 3-11 3.4.1.1—Data Cache Flash Invalidation - - - - - - - - - - - - - 3-12 3.4.1.2—Data Cache Enabling/Disabling - - - - - - - - - - - - 3-12 3.4.1.3—Data Cache Locking- - - - - - - - - - - - - - - - - - - - 3-12 3.4.1.4—Instruction Cache Flash Invalidation- - - - - - - - - 3-12 3.4.1.5—Instruction Cache Enabling/Disabling- - - - - - - - 3-13 3.4.1.6—Instruction Cache Locking - - - - - - - - - - - - - - - 3-13 3.4.2—Cache Control Instructions - - - - - - - - - - - - - - - - - - - - - - 3-13 3.4.2.1—Data Cache Block Touch (dcbt) and Data Cache Block Touch for Store (dcbtst) - - - - 3-14 3.4.2.2—Data Cache Block Zero (dcbz)- - - - - - - - - - - - - 3-14 3.4.2.3—Data Cache Block Store (dcbst) - - - - - - - - - - - - 3-14 3.4.2.4—Data Cache Block Flush (dcbf) - - - - - - - - - - - - 3-15 3.4.2.5—Data Cache Block Invalidate (dcbi)
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