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Automatic Identification and Utilization of Custom Instructions for Network Automatic Identification and Utilization of Custom Instructions for Network Processors Von der Fakult¨at f¨ur Elektrotechnik und Informationstechnik der Rheinisch–Westf¨alischen Technischen Hochschule Aachen zur Erlangung des akademischen Grades eines Doktors der Ingenieurwissenschaften genehmigte Dissertation vorgelegt von Diplom–Informatiker Hanno Scharw¨achter aus Leverkusen/Nordrhein-Westfalen Berichter: Universit¨atsprofessor Dr. rer. nat. Rainer Leupers Universit¨atsprofessor Dr.-Ing. Gerd Ascheid Tag der m¨undlichen Pr¨ufung: 21.05.2015 Diese Dissertation ist auf den Internetseiten der Hochschulbibliothek online verf¨ugbar. Zusammenfassung Gordon E. Moore beschrieb 1965 einen wegweisenden Trend f¨ur die Chipentwicklung: Er sagte voraus, dass sich die Anzahl der verwendeten Schaltkreise pro Fl¨acheneinheit f¨ur einen Prozessor alle zwei Jahre verdoppeln w¨urde. Dieser Trend hat sich bis heute bewahrheitet und erm¨oglicht seitdem dramatische Ver¨anderungen des Prozessorentwurfs. Insbesondere im Bereich der Pro- tokollverarbeitung (TCP/IP/Ethernet) wurde die Entwicklung neuer Prozessoren durch enorme Zuwachsraten an Internet-Nutzern und innovativer Anwendungen wie Voice-over-IP, Internet Tele- fonie u.a. (die heute l¨angst Standard sind) befeuert. Aus dieser Situation heraus entstand die Vision eines Netzwerkprozessors (NPU), welcher die effiziente Verarbeitung hoher Datenvolumen mit der Flexibilit¨at zur Entwicklung neuer Algorithmen verbindet. Der Spagat zwischen diesen unterschiedlichen Anforderungen bewirkt zeitaufw¨andige Entwurfszyklen, so dass automatisierte Entwurfsmethoden und entsprechende Werkzeuge zwingend notwendig sind, um mit vertret- barem Aufwand ein NPU-System zu entwerfen. Compiler-in-the-Loop Architektur-Exploration wird heutzutage als der richtige Weg angesehen dieses Problem zu l¨osen. In diesem Zusammen- hang spielen automatisierte Compiler-Erzeugung und Instruktionssatz-Erweiterung (ISE) wichtige Rollen. Beide Techniken erm¨oglichen Prozessordesignern den Instruktionssatz (ISA) einer NPU an die Anforderungen von Netzwerkanwendungen komfortabel anzupassen und dar¨uber hinaus ein entsprechendes Programmiermodell durch einen Compiler f¨ur Anwender bereitzustellen. Diese Ar- beit pr¨asentiert Fallstudien zu Architektur-Exploration und Compiler-Optimierung in Verbindung mit ISE f¨ur NPUs. Motiviert durch die gewonnenen Erkenntnisse wird ein Rahmenwerk zur au- tomatisierten Compiler/Architektur Co-Exploration entwickelt. Der Vorteil dieses Rahmenwerks begr¨undet sich auf der M¨oglichkeit durch Analyse von C-Anwendungen eine optimierte ISA und einen passenden Compiler zu entwickeln und dadurch den Entwurf programmierbarer Prozessorar- chitekturen f¨ur diese Anwendungen zu unterst¨utzen. Gleichzeitig wird der Ablauf der Architektur- Exploration beschleunigt, da zeiaufw¨andige Analysen der Anwendungen und Retargierung des Compilers effektiv unterst¨utzt werden. iii iv Das Rahmenwerk basiert auf zwei Werkzeugen: Einer Analyse von C-Anwendungen zur Identi- fizierung von Instruktionen f¨ur eine ISE sowie eines Code-Generators zur Erzeugung eines Al- gorithmus, der, eingebettet in einen Compiler, die automatische Verwendung der Instruktionen durch einen Compiler erm¨oglicht. Die Analyse bezieht vollst¨andige Anwendungen ein und ist nicht auf einzelne Abschnitte der An- wendungen beschr¨ankt. Durch ihre polynomische Laufzeitkomplexit¨at k¨onnen mit diesem Ansatz auch komplexe oder mehrere Anwendungen verarbeitet werden. Das Ergebnis dieses Verfahrens ist eine Beschreibung der Instruktionen in einer Form, wie sie der Code-Generator verarbeiten kann. Basierend auf dieser Beschreibung erzeugt der Code-Generator einen Algorithmus zur Code- Selektion. Diese besitzt lineare Laufzeitkomplexit¨at und kann beliebig komplexe Instruktionen erfassen; insbesondere Instruktionen, welche mehrere Ergebnisse gleichzeitig berechnen. Das gesamte Rahmenwerk ist eingebettet in eine industrieerprobte Methodik zur Architektur- Exploration. Diese erlaubt die iterative Entwicklung eines Prozessors basierend auf einem Mod- ell in Architekturbeschreibungssprache. W¨ahrend der Exploration k¨onnen relevante Werkzeuge wie Assembler, Linker oder Simulator aus dem Modell heraus erzeugt werden. So ergibt sich ein verbesserter Design-Ablauf, wobei der Designer in einem einzigen Entwurfszyklus einen opti- mierten Satz Instruktionen und einen dazu passenden Compiler erh¨alt. In nachfolgenden Zyklen ¨ubernimmt er die Instruktionen in sein Prozessormodell und evaluiert die Ver¨anderungen anhand der verarbeiteten Anwendungen mit Hilfe des neuen Compilers und des generierten Simulators. Abstract 1965, Gordon E. Moore has described a groundbreaking trend for the design of processors: he pre- dicted a doubling of the number of circuit components fabricated on a single chip every two years. This trend has proven itself to be true and has enabled spectacular rates of progress in semicon- ductor technology since then. Particularly in the field of protocol processing, system design has been driven by the continuously growing number of Internet users and traffic accompanying the rise of new network protocols like Voice-over-IP, VPN or Internet TV (which have long become standards). This development has led to the rise of a new type of Application-Specific Instruction Set Processor (ASIP) especially designed to support high-level programmability of network pro- tocols and efficient packet processing at the same time, called Network Processing Unit (NPU). Designing such systems under increasing time-to-market pressure imposes clear requirements for systematic and, moreover, automated design methodologies for building NPUs, so that time and effort to design a system containing both hardware and software remains acceptable. Compiler– in–the–Loop (CiL) architecture exploration is widely accepted as being the right track for fast development of ASIPs like NPUs. In this context, automatic application-specific Instruction Set Extension (ISE) and code generation by a compiler have received huge attention in the past. To- gether, both techniques enable processor designers to quickly adapt a processor’s Instruction Set Architecture (ISA) to the needs of a certain set of applications and to provide an appropriate high- level programming model. This manuscript presents a detailed analysis of architecture exploration for NPUs. It develops a scalable framework for automatic compiler/architecture co-exploration, targeting the domain of network applications. First, the framework is based on a novel code-selection technique for the compiler and an appropri- ate code-generator for this technique. The code-generator takes a description of the ISA as input and produces a set of C-functions allowing for comfortable implementation of the aforementioned code-selection. The code-selection algorithm features linear runtime complexity and — in contrast to traditional approaches of this type — is capable of handling arbitrary complex instructions; especially inherent parallel instructions computing multiple results at the same time. v vi Second, the framework is based on a novel methodology for automatic identification of possible ISEs. It identifies new instructions through the analysis of complete applications and is not restricted to selected hotspots of these applications. Its polynomial runtime complexity enables the analysis of (a set of) complex real-world applications. It results in a grammar description of the most efficient hardware instructions, which can in turn be processed by the aforementioned code-generator. By embedding this tool flow in an industry-proven architecture exploration framework, a method- ology for simultaneous compiler/architecture co-exploration is derived, which allows for iterative development of a processor model, written in Architecture Description Language (ADL). During architecture exploration, relevant tools like assembler, linker and simulator can be generated based on the processor model. Thereby an improved design flow is created that enables designers to retrieve an optimized ISA and appropriate compiler in a single iteration. In subsequent itera- tions, he integrates the instructions in the processor model and evaluates the effects on the target applications with the help of the retargeted compiler and generated simulator. Acknowledgments First and foremost I would like to thank my thesis supervisor Professor Rainer Leupers for pro- viding me with the opportunity to work in his group as well as for his important advice and constant encouragement throughout the course of my research. He always left me a lot freedom and contributed much to an enjoyable and productive working atmosphere. I am also thankful to the Professors Gerd Ascheid and Heinrich Meyr. I want to thank all of them for the lessons they gave me on the importance of details for the success of a scientific or engineering project. It has been a distinct privilege for me to work with them. There were a number of people in my everyday circle of colleagues who have enriched my personal life in various ways and who were also true friends. I am particular indebted to my colleagues Manuel Hohenauer, Kingshuk Karuri, Jiangjiang Ceng and Stefan Kraemer who worked together with me from the first minute. Without their contributions, their support and the inspiring atmosphere within our team, this work would have not been possible. I thank all of you. Special thanks goes also to David Kammler who were my partner in many publications. His expertise in hardware generation was an invaluable asset for my work.
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