DOCSLIB.ORG

Invent the New Reality. Intel Architecture =

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Invent the New Reality. Intel Architecture = Invent the new reality. Intel Architecture = Embedded + Dynamic + Visual Pat Gelsinger Senior Vice President and Co-General Manager Digital Enterprise Group In Retrospect “The vision of a billion connected “Our vision is for a billion phones and a billion connected interconnected computers “We are heading toward a handsets is happening . By 2010, attached to the Internet. The world of a billion — a those same trends will give us a mobile or wireless vision is a billion connected 1.5B connected PCs, except this billion subscribers who can talk computers.” time, it's broadband . Those same to each other and also have trends will give us 2.5B Internet access.” connected handsets.” Andrew S. Grove Craig Barrett Paul Otellini Chairman & CEO, Intel Corporation CEO, Intel Corporation President & COO, Intel Corporation IDF, February 17, 1998 IDF August 22, 2000 IDF, Sept 23, 2003 The Internet Today: 3rd Generation Ubiquitous Many Researchers Mainframes Servers, PC’s Cell Phones The Embedded Internet: 4th Stage Pervasive Ubiquitous Many Researchers Mainframes Servers, PC’s Cell Phones Embedded Internet – 7x24, Every Modality of Life The Embedded Internet by 2015 15B Devices Pervasive Ubiquitous Many Researchers Mainframes Servers, PC’s Cell Phones Embedded Internet – 7x24, Every Modality of Life The Next Wave of Devices “Personal” “Public” Towards 15B Devices by 2015 Top Barriers Reliability and Long Life Software Scalability Low Power and Low Cost Privacy and Data Security IPv4 Addressing Open Standards Towards 15B Devices by 2015 Top Barriers Solutions Reliability and Long Life Intel® Products Software Scalability Intel Architecture Low Power and Low Cost Intel® Atom™ Processor and SoCs Privacy and Data Security Encryption, Standards, Policy IPv4 Addressing Drive Towards IPv6 by 2012 Wifi, WiMAX, RFID, Bluetooth Open Standards ZigBee, Z-Wave, LTE, P2P SIP, Open IPTV Serving the Embedded Segment Since 1976 1970’s 1980’s 1990’s 2000 2005 1st Integrated Silicon Chipset For Embedded Intel Creates 1st Embedded Ecosystem Ecosystem Program Intel Enters Keynote at Intel Intel st Embedded 1 Embedded Revenue Revenue Market Market Systems $500M+ In $1B+ In Segment Conference Embedded Embedded Embedded Market Segment Is Growing Celebrating 30+ Years in Embedded The Preferred Architecture for Embedded Internet Scalable Architecture Long Life Cycle Support PC Embedded Solutions from <1W-130W Intel Architecture Purpose Built Solutions World’s Best Ecosystem and Tools Embedded Products Today and Future Traditional Embedded IA Desktop Mobile Embedded Products Today and Future Traditional New Low Power IA Embedded IA Introduced: April 2008 Fan-less <5W Platform Small Footprint ~700 Embedded Customer Design Engagements Accelerating Conversion From Other Architectures Desktop Mobile Embedded Products Today and Future Traditional New Low Power IA and SoCs for Embedded Embedded IA Announced July 2008 First IA SOC since 80386EX in 1994 – Intel® QuickAssist Technology – Communications I/O Industrial temperature offering 45% area savings*, 30% power savings* Q3’08 production Desktop Mobile 2008 Embedded Products Today and Future Traditional New Low Power IA and SoCs for Embedded Embedded IA Q1’09 2H’09 Desktop Mobile 2008 Home Automation Open Architecture Low-power Small Form Factor IP Media Phones: Resetting Expectations For The Home Phone In-Vehicle Infotainment: Bringing IT to the Car Emerging Open Infotainment Platform Design Services TV: Terrestrial/Satellite Middleware and Rich 3D GPS Applications Social Networking Board Vendors/ODMs Online Gaming Video On Demand Operating Systems Office Synch Complimentary Auto Silicon NG Remote Diagnostics Supported by Broad Eco-System Industry Momentum “BMW Group welcomes Intel’s “A more open and standard “With open infotainment commitment to the approach to infotainment platforms, our traditional tier automotive infotainment product development will 1 suppliers could concentrate space, enabling us to bridge enable the automotive on using their engineering the gap between current industry to more quickly meet power to create new automotive implementations the consumer demands for innovations for us. I also and the consumer sector.” Multimedia and Internet expect quality improvements access.” since multiple suppliers will Christoph Grote be able to use and test the Senior Vice President Information & Tsuguo NOBE same software." Communication Systems General Manager BMW Group NISSAN MOTOR CO., LTD. Mr Häussermann VP Infotainment Development Daimler - Mercedes Benz BMW Group In-Vehicle Infotainment Alex Busch Information and Communication Systems BMW Group “… the solution for the future could be to add vehicle-specific components and requirements to existing IT technology and make it suitable for use in cars.” (Source: BMW Group press release, March 12, 2008, http://www.press.bmwgroup.com/pressclub/gb02.nsf, BMW Innovation Day 2008) The Embedded Internet by 2015 15B Devices Pervasive Ubiquitous Many Researchers Mainframes Servers, PC’s Cell Phones Embedded Internet – 7x24, Every Modality of Life Intel Architecture Embedded + Dynamic + Visual Tick-Tock Development Model: Predictable, Sustained Microprocessor Leadership Intel® Core™ Nehalem microarchitecture Future uArch Merom Penryn Nehalem Westmere Sandy Bridge NEW NEW NEW NEW NEW Microarchitecture Process Microarchitecture Process Microarchitecture 65nm 45nm 45nm 32nm 32nm TOCK TICK TOCK TICK TOCK Montecito / Tukwila Poulson Montvale NEW NEW NEW Microarchitecture Microarchitecture Microarchitecture 90nm 65nm 32nm Forecast All dates, product descriptions, availability and plans are forecasts and subject to change without notice. Next Generation Intel® Itanium® (Tukwila) st “With Intel’s upcoming 1 2B transistor chip quad-core Tukwila processor, Windows Built for mission critical enterprise Server solutions running on Itanium-based – On-die error protection systems will provide an even more scalable and – RAS reliable datacenter foundation for our – Advanced power and thermal management customers.” 2nd generation Virtualization Technology Bill Laing Strong roadmap with Poulson and Kittson Corporate Vice President Windows Server Division, Microsoft Business Critical Capabilities for Most Demanding Systems Intel® Xeon® 7400 Series (Dunnington) Virtualization platform of choice – just got better Cores Cores Investment Protection Cache – Intel VT FlexMigration System Interface – Socket compatible with Xeon™ 7300 Cores Cache 45 nm high-k – 6 cores – 16MB shared L3 cache Extending MP Leadership in September 2008 Intel® Xeon® Processor 7400 Series: Setting New Enterprise Performance Records TPC Benchmark* C - DB2 TPC Benchmark* C – SQL Server 1,200,632 tpmC 634,825 tpmC First 8S 1 M+ TPC-C database result for Xeon! SPECjbb*2005 - – Java HotSpot TPC Benchmark* E JVM 671.4 tpsE 531,669 bops vConsolidate – SPECint*_rate2006 VMware* ESX 39% better** 277 peak score Unquestioned Expandable Server Leadership **Intel Xeon X7460 (16M cache, 2.66GHz, 1066FSB) 6-Core compared to Intel Xeon X7350 (4M cache, 2.93GHz, 1066FSB) Quad-Core Nehalem Family Server and Efficient Expandable (4S+) Workstation Performance (2S) Business and High End Mainstream Consumer Desktop Client Clients Thin and Light Notebook Nehalem: Next Generation Micro-architecture Energy Efficient Performance Turbo Mode Intel Hyper-Threading Dynamic Power Management Technology Nehalem 3x Memory Bandwidth Intel’s 2nd Generation Virtualization Best in Class Bandwidth with QPI Industry’s First Dynamically Scalable Architecture Rajesh Kumar Intel Fellow Director, Circuit & Low Power Technologies Intel Corporation Integrated Power Gate Clock Gate – Standard in all Intel CPUs VCC – Eliminates switching power – Leakage power remains Power Gate: New Core0 Core1 Core2 Core3 – Eliminates switching and leakage power Memory System, Cache, I/O VTT – Enables idle cores to go to near zero power (C6) independently – Transparent to platform and software – No incremental platform cost Power Gates Silicon Technology Polymer M9 7 mm Cu M1-8 Package Like Metal (M9) Deposited On Specialized, Ultra-low Leakage Transistor Silicon to Create Low On-resistance Developed for High Off-resistance Intel Design and Process Technology Co-development Power Management: Power Control Unit Vcc BCLK Core 0 Vcc PLL Frequency PLL Sensors Core 1 • Integrated microcontroller Vcc Frequency PLL • Controlled by firmware Sensors • Real time sensors for Core 2 current/ power, voltage, PCU Vcc temperature Frequency PLL Sensors • Enables sophisticated Core 3 algorithms for current Uncore , operating conditions Vcc LLC Frequency PLL Sensors Frequency (F) Core 0 No Turbo Core 1 Core 2 Core 3 Lightly Threaded Workload <TDP Workload Threaded Lightly Nehalem TurboMode Frequency (F) Core 0 Core 1 Core 2 Core 3 Frequency (F) Core 0 No Turbo Core 1 Core 2 Core 3 Lightly Threaded Workload <TDP Workload Threaded Lightly Near Zero Power For Inactive Cores Inactive For Power Zero Near Nehalem TurboMode Power Gates Frequency (F) Core 0 Core 1 Core 2 Core 3 Nehalem Turbo Mode Power Gates Turbo Mode Near Zero Power For Inactive Cores Adds Additional Performance Bins* In Response To Workload No Turbo Lightly Threaded Workload < TDP Core 1 Core 2 Core 3 Core 1 Core 0 Core 0 Frequency (F) Frequency Frequency (F) Frequency *within power and thermal constraints Nehalem Turbo Mode Power Gates Turbo Mode Near Zero Power For Inactive Cores Adds Additional Performance Bins* In Response To Workload No Turbo Lightly Threaded Workload < TDP Core 1 Core 2 Core 3 Core 1 Core 0 Core 0 Frequency
Load more

Recommended publications
  • Evolution of Microprocessor Performance
    EvolutionEvolution ofof MicroprocessorMicroprocessor PerformancePerformance So far we examined static & dynamic techniques to improve the performance of single-issue (scalar) pipelined CPU designs including: static & dynamic scheduling, static & dynamic branch predication. Even with these improvements, the restriction of issuing a single instruction per cycle still limits the ideal CPI = 1 Multiple Issue (CPI <1) Multi-cycle Pipelined T = I x CPI x C (single issue) Superscalar/VLIW/SMT Original (2002) Intel Predictions 1 GHz ? 15 GHz to ???? GHz IPC CPI > 10 1.1-10 0.5 - 1.1 .35 - .5 (?) Source: John P. Chen, Intel Labs We next examine the two approaches to achieve a CPI < 1 by issuing multiple instructions per cycle: 4th Edition: Chapter 2.6-2.8 (3rd Edition: Chapter 3.6, 3.7, 4.3 • Superscalar CPUs • Very Long Instruction Word (VLIW) CPUs. Single-issue Processor = Scalar Processor EECC551 - Shaaban Instructions Per Cycle (IPC) = 1/CPI EECC551 - Shaaban #1 lec # 6 Fall 2007 10-2-2007 ParallelismParallelism inin MicroprocessorMicroprocessor VLSIVLSI GenerationsGenerations Bit-level parallelism Instruction-level Thread-level (?) (TLP) 100,000,000 (ILP) Multiple micro-operations Superscalar /VLIW per cycle Simultaneous Single-issue CPI <1 u Multithreading SMT: (multi-cycle non-pipelined) Pipelined e.g. Intel’s Hyper-threading 10,000,000 CPI =1 u uuu u u Chip-Multiprocessors (CMPs) u Not Pipelined R10000 e.g IBM Power 4, 5 CPI >> 1 uuuuuuu u AMD Athlon64 X2 u uuuuu Intel Pentium D u uuuuuuuu u u 1,000,000 u uu uPentium u u uu i80386 u i80286
    [Show full text]
  • Extended Lifecycle Series
    MAINBOARD D2778-D Issue April 2010 ATX Extended Lifecycle Series Pages 2 ® Intel X58 Express Chipset for DDR3 - 1333 SDRAM Memory (ECC Support) ® TM and Intel Xeon® (“Nehalem” and “Westmere”) and Core i7 Processors Chipset: Memory: Intel® X58 Express Chipset DDR3 800 SDRAM (Tylersburg-36S / ICH10-R) DDR3 1066 SDRAM DDR3 1333 SDRAM Processors: with ECC Support (depends on processor) ® ® Intel Xeon Processor 5500 / 5600 series ® ® Product Features: Intel Xeon Processor 3500 / 3600 series Intel® CoreTM i7 Processor series Dual PCIe x16 (Gen2) onboard 5.1 multichannel audio onboard Compatible with Intel® processors LGA1366 (up to ® LSI FW322 FireWire™ onboard 130W TDP) supporting Intel QuickPath USB 2.0 onboard Interconnect GbE LAN onboard supporting ASF 2.0 Serial ATA II RAID onboard Trusted Platform Modul V1.2 onboard Intel® QuickPath technology Data Sheet Issue: April 2010 Datasheet D2778-D Page 2 / 2 Audio Realtek ALC663, 5.1 Multichannel, High Definition Audio Board Size ATX: 12“ x 9.6“ (304.8 x 243.8 mm) ® LAN Chipset Intel “Tylersburg” X58 Express Chipset / ICH10-R Realtek 8111DP Ethernet Controller with 10/100/1000 MBit/s, DASH 1.1, Memory Wake-on-LAN (WoL) by interesting Packets, Link Status Change and Magic 6 DIMM Sockets DDR3, max. 24GB, Single / Dual / Triple Channel Packet™, PXE Support, BIOS MAC Address Display 800/1066/1333MHz, single rank / dual rank unbuffered, ECC / no n-ECC Drives support (depends on processor) - 6 Serial ATA II 300 Interfaces (up to 3GBit/s, NCQ); RAID 0, 1, 10, 5 Processors Intel® Xeon® Processor 5500 / 5600 series (Nehalem-EP / Westmere) Features D2778-D Intel® Xeon® Processor 3500 /3600 series (Nehalem-WS / Westmere) Chipset Intel X58 / ICH10R Intel® Core™ i7 Processor series Board Size ATX Socket B (LGA1366), max.
    [Show full text]
  • User Guide XFX X58i Motherboard
    User Guide XFX X58i Motherboard Table of Contents Chapter 1 Introduction .............................................................................................3 1.1 Package Checklist .................................................................................................3 1.2 Specifi cations .......................................................................................................4 1.3 Mainboard Layout .................................................................................................5 1.4 Connecting Rear Panel I/O Devices ........................................................................6 Chapter 2 Hardware Setup .......................................................................................7 2.1 Choosing a Computer Chassis ................................................................................7 2.2 Installing the Mainboard .......................................................................................7 2.3 Installation of the CPU and CPU Cooler ..................................................................8 2.3.1 Installation of the CPU ....................................................................................8 2.3.2 Installation of the CPU Cooler .........................................................................9 2.4 Installation of Memory Modules .............................................................................9 2.5 Connecting Peripheral Devices .............................................................................10 2.5.1
    [Show full text]
  • Fuzhouxiang Import/Export (Shunxiang) Co., Ltd
    Fuzhouxiang Import/Export (Shunxiang) Co., Ltd. We always insist on the principle “Quality of product & benefit for customer at first forever”, assure that all products which we supply are quality goods absolutely. We have built good relationships with our customers with 100% quality guarantee, most competitive price, prompt delivery & best service for the past several years. Please join us, you will feel our sincerity, fairy & conscience. Apple'Mac-Book Pro MGXA2LL/A 15-Inch Laptop Notebook Computer with Retina Display (2.2 GHz Intel Core i7 Processor, 16 GB RAM, 256 GB HDD) Mac-Book Pro MGXA2LL/A 15- Inch Laptop with Retina Display (2.2 GHz Intel Core i7 Processor, 16 GB RAM, 256 GB HDD) 2.2 GHz Quad-Core Intel Core i7 Processor (Turbo Boost up to 3.4 GHz, 6 MB shared L3 cache) 16 GB 1600 MHz DDR3L RAM; 256 GB PCIe-based Flash Storage 15.4- inch IPS Retina Display, 2880-by-1800 resolution Intel Iris Pro Graphics OS X Mavericks, Up to 8 Hours of Battery Life Apple'Mac-Book Pro 15" with Apple'Care+ Z0SH0000N CTO with Touch Bar: 2.9GHz quad-core Intel Core i7, 2TB - Space Gray Mac-Book Pro with Touch Bar 2.9GHz quad-core Intel Core i7, Turbo Boost up to 3.8GHz, with 6MB shared L3 cache (Configurable to 2.9GHz quad-core Intel Core i7, Turbo Boost up to 3.8GHz, with 8MB shared L3 cache) 2TB PCIe-based onboard SSD 16GB of 2133MHz LPDDR3 onboard memory 15.4-inch (diagonal) LED-backlit display with IPS technology; 2880-by- 1800 native resolution at 220 pixels per inch with support for millions of colors 500 nits brightness Radeon Pro 460 with
    [Show full text]
  • Course #: CSI 440/540 High Perf Sci Comp I Fall ‘09
    High Performance Computing Course #: CSI 440/540 High Perf Sci Comp I Fall ‘09 Mark R. Gilder Email: [email protected] [email protected] CSI 440/540 This course investigates the latest trends in high-performance computing (HPC) evolution and examines key issues in developing algorithms capable of exploiting these architectures. Grading: Your grade in the course will be based on completion of assignments (40%), course project (35%), class presentation(15%), class participation (10%). Course Goals Understanding of the latest trends in HPC architecture evolution, Appreciation for the complexities in efficiently mapping algorithms onto HPC architectures, Familiarity with various program transformations in order to improve performance, Hands-on experience in design and implementation of algorithms for both shared & distributed memory parallel architectures using Pthreads, OpenMP and MPI. Experience in evaluating performance of parallel programs. Mark R. Gilder CSI 440/540 – SUNY Albany Fall '08 2 Grades 40% Homework assignments 35% Final project 15% Class presentations 10% Class participation Mark R. Gilder CSI 440/540 – SUNY Albany Fall '08 3 Homework Usually weekly w/some exceptions Must be turned in on time – no late homework assignments will be accepted All work must be your own - cheating will not be tolerated All references must be sited Assignments may consist of problems, programming, or a combination of both Mark R. Gilder CSI 440/540 – SUNY Albany Fall '08 4 Homework (continued) Detailed discussion of your results is expected – the program is only a small part of the problem Homework assignments will be posted on the class website along with all of the lecture notes ◦ http://www.cs.albany.edu/~gilder Mark R.
    [Show full text]
  • Intel® Desktop Board DX58SO Technical Product Specification
    Взято с сайта www.wit.ru Intel® Desktop Board DX58SO Technical Product Specification October 2008 Order Number: E51290-001US The Intel® Desktop Board DX58SO may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in the Intel Desktop Board DX58SO Specification Update. Revision History Revision Revision History Date -001 First release of the Intel® Desktop Board DX58SO Technical Product October 2008 Specification This product specification applies to only the standard Intel® Desktop Board DX58SO with BIOS identifier SOX5810J.86A. Changes to this specification will be published in the Intel Desktop Board DX58SO Specification Update before being incorporated into a revision of this document. INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. All Intel® desktop boards are evaluated as Information Technology Equipment (I.T.E.) for use in personal computers (PC) for installation in homes, offices, schools, computer rooms, and similar locations.
    [Show full text]
  • Itanium Processor
    IA-64 Microarchitecture --- Itanium Processor By Subin kizhakkeveettil CS B-S5….no:83 INDEX • INTRODUCTION • ARCHITECTURE • MEMORY ARCH: • INSTRUCTION FORMAT • INSTRUCTION EXECUTION • PIPELINE STAGES: • FLOATING POINT PERFORMANCE • INTEGER PERFORMANCE • CONCLUSION • REFERENCES Itanium Processor • First implementation of IA-64 • Compiler based exploitation of ILP • Also has many features of superscalar INTRODUCTION • Itanium is the brand name for 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64). • Itanium's architecture differs dramatically from the x86 architectures (and the x86-64 extensions) used in other Intel processors. • The architecture is based on explicit instruction-level parallelism, in which the compiler makes the decisions about which instructions to execute in parallel Memory architecture • From 2002 to 2006, Itanium 2 processors shared a common cache hierarchy. They had 16 KB of Level 1 instruction cache and 16 KB of Level 1 data cache. The L2 cache was unified (both instruction and data) and is 256 KB. The Level 3 cache was also unified and varied in size from 1.5 MB to 24 MB. The 256 KB L2 cache contains sufficient logic to handle semaphore operations without disturbing the main arithmetic logic unit (ALU). • Main memory is accessed through a bus to an off-chip chipset. The Itanium 2 bus was initially called the McKinley bus, but is now usually referred to as the Itanium bus. The speed of the bus has increased steadily with new processor releases. The bus transfers 2x128 bits per clock cycle, so the 200 MHz McKinley bus transferred 6.4 GB/sand the 533 MHz Montecito bus transfers 17.056 GB/s.
    [Show full text]
  • (12) Patent Application Publication (10) Pub. No.: US 2011/0142067 A1 JEHL Et Al
    US 2011 O142067A1 (19) United States (12) Patent Application Publication (10) Pub. No.: US 2011/0142067 A1 JEHL et al. (43) Pub. Date: Jun. 16, 2011 (54) DYNAMIC LINK CREDIT SHARING IN QPI Publication Classification (76) Inventors: Timothy J. JEHL, Gilbert, AZ (51) Int. Cl. (US); Pradeepsunder Ganesh, HO4, 3/02 (2006.01) Chandler, AZ (US); Aimee Wood, (52) U.S. Cl. ........................................................ 370/462 Tigard, OR (US); Robert Safranek, Portland, OR (US); John A. Miller, (57) ABSTRACT Portland, OR (US): Selim Bilgin, A method and system for dynamic credit sharing in a quick Hillsboro, OR (US); Osama path interconnect link. The method including dividing incom Neiroukh, Jerusalem (IL) ing credit into a first credit pool and a second credit pool; and allocating the first credit pool for a first data traffic queue and (21) Appl. No.: 12/639,556 allocating the second credit pool for a second data traffic queue in a manner So as to preferentially transmit the first data (22) Filed: Dec. 16, 2009 traffic queue or the second data traffic queue through a link. NCOMING CREDIT CREDIT SWW CONTROLED SHARING BIAS REGISTERS is LOCAL TRAFFIC LOCAL TRAFFIC CREDITS 26A RTTH TRAFFIC RITH TRAFFIC 28A CREDITS 28B/ 26B 26 2 Patent Application Publication Jun. 16, 2011 Sheet 1 of 2 US 2011/O142067 A1 FIG. LINKO DEVICE FIG. 2 Patent Application Publication Jun. 16, 2011 Sheet 2 of 2 US 2011/O142067 A1 US 2011/O 142067 A1 Jun. 16, 2011 DYNAMIC LINK CREDIT SHARING IN QPI tion only and are not intended as a definition of the limits of the invention.
    [Show full text]
  • Intel® Processor Architecture
    Intel® Processor Architecture January 2013 Software & Services Group, Developer Products Division Copyright © 2013, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Agenda •Overview Intel® processor architecture •Intel x86 ISA (instruction set architecture) •Micro-architecture of processor core •Uncore structure •Additional processor features – Hyper-threading – Turbo mode •Summary Software & Services Group, Developer Products Division Copyright © 2013, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. 2 Intel® Processor Segments Today Architecture Target ISA Specific Platforms Features Intel® phone, tablet, x86 up to optimized for ATOM™ netbook, low- SSSE-3, 32 low-power, in- Architecture power server and 64 bit order Intel® mainstream x86 up to flexible Core™ notebook, Intel® AVX, feature set Architecture desktop, server 32 and 64bit covering all needs Intel® high end server IA64, x86 by RAS, large Itanium® emulation address space Architecture Intel® MIC accelerator for x86 and +60 cores, Architecture HPC Intel® MIC optimized for Instruction Floating-Point Set performance Software & Services Group, Developer Products Division Copyright © 2013, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. 3 Itanium® 9500 (Poulson) New Itanium Processor Poulson Processor • Compatible with Itanium® 9300 processors (Tukwila) Core Core 32MB Core Shared Core • New micro-architecture with 8 Last Core Level Core Cores Cache Core Core • 54 MB on-die cache Memory Link • Improved RAS and power Controllers Controllers management capabilities • Doubles execution width from 6 to 12 instructions/cycle 4 Intel 4 Full + 2 Half Scalable Width Intel • 32nm process technology Memory QuickPath Interface Interconnect • Launched in November 2012 (SMI) Compatibility provides protection for today’s Itanium® investment Software & Services Group, Developer Products Division Copyright © 2013, Intel Corporation.
    [Show full text]
  • Intel® Desktop Board DX58SO2 Technical Product Specification
    Intel® Desktop Board DX58SO2 Technical Product Specification November 2010 Order Number: G13828-001US The Intel Desktop Board DX58SO2 may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in the Intel Desktop Board DX58SO2 Specification Updates. Revision History Revision Revision History Date -001 First release of the Intel® Desktop Board DX58SO2 Technical Product November 2010 Specification This product specification applies to only the standard Intel® Desktop Board DX58SO2 with BIOS identifier SOX5820J.86A. Changes to this specification will be published in the Intel Desktop Board DX58SO2 Specification Update before being incorporated into a revision of this document. INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. All Intel® desktop boards are evaluated as Information Technology Equipment (I.T.E.) for use in personal computers (PC) for installation in homes, offices, schools, computer rooms, and similar locations.
    [Show full text]
  • Itanium and Vnuma
    Virtualisation Case Study: Itanium and vNUMA Matthew Chapman [email protected] 1 ITANIUM ➜ High-performance processor architecture ➜ Also known as IA-64 ➜ Joint venture between HP and Intel ➜ Not the same instruction set as IA-32/AMD64/EM64T ➜ Very good floating-point performance 2000: Itanium“Merced” 180nm,upto800Mhz,4MBcache 2002: ItaniumII“McKinley” 180nm,upto1Ghz,3MBcache 2003: ItaniumII“Madison” 130nm,upto1.6Ghz,6MBcache 2004: Itanium II “Madison 9M” 130 nm, up to 1.67Ghz, 9MB cache 2006: Itanium II “Montecito” 90 nm, dual-core, up to 1.6Ghz, 24MB cache 2008: “Tukwila” 65nm,quad-core,upto2.5Ghz? ITANIUM 2 EXPLICITLY PARALLEL INSTRUCTION-SET COMPUTING (EPIC) ➜ Goal to increase instructions per cycle ➜ Itanium can have similar performance to x86 at a lower clock speed ➜ Based on Very Long Instruction Word (VLIW) ➜ Explicit parallelism in instruction set ➜ Simplified instruction decode and issue ➜ Scheduling decisions made by compiler Memory Branch Branch Branch Integer Integer Integer Integer MI;I bundle Integer Memory Memory Memory Memory Floating−point Floating−point Floating−point Floating−point VLIW Instruction MFI bundle Integer Execution Units Execution Units EPIC Instructions EXPLICITLY PARALLEL INSTRUCTION-SET COMPUTING (EPIC) 3 EXAMPLE Load and add three numbers in assembly code: ld8 r4 = [r1] ld8 r5 = [r2] ld8 r6 = [r3] ;; add r7 = r4, r5 ;; add r8 = r6, r7 ;; EXAMPLE 4 Resulting instructions: MMI ld8 r4=[r1] ld8 r5=[r2] nop.i 0 M;MI; ld8 r6 = [r3] ;; add r7=r4,r5 // Arithmetic on M too nop.i 0 ;; M;MI add r8 = r6, r7
    [Show full text]
  • Chapter 29 Itanium Architecture
    Chapter 29 Itanium Architecture Chapter 29 - Itanium Architecture July 2003 Chapter 29 / Page 1 Chapter 29 Itanium Architecture INDEX Introduction 3 Overview of the Itanium Architecture 3 Main features of EPIC....................................................................................................... 3 The Itanium processor family (IPF) 5 HP-UX Itanium Releases 6 Differences between HP-UX for PA and IPF ................................................................... 6 What needs to be considered on an IPF system 8 How an IPF system boots.................................................................................................. 8 Boot disk layout and EFI................................................................................................... 8 How to configure the Console input/output devices....................................................... 10 The boot process ............................................................................................................. 13 How to mirror the root disk............................................................................................. 18 How to replace a failed disk............................................................................................ 21 The ARIES emulator 22 IPF vs. PA-RISC Terminology 22 Additional Information 23 July 2003 Chapter 29 / Page 2 Chapter 29 Itanium Architecture Introduction When PA-RISC was released, HP began designing the architecture to replace it. Several years into the project, HP determined that the economics
    [Show full text]