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An Outlook of Technology Scaling Beyond Moore's Law

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An Outlook of Technology Scaling Beyond Moore's Law An Outlook of Technology Scaling Beyond Moore's Law Adrian M. Ionescu Ecole Polytechnique Fédérale de Lausanne Adrian Ionescu, October 2005 1 Summary • Introduction: Moore’s law… • More Moore, Beyond CMOS, More-than-More • Fundamental limits • Evolutionary and non-classical MOSFET (More Moore…) • Emerging nanoelectronics (… beyond CMOS) Single/few electron electronics & QCA Nanowires & carbon nanotubes Molecular electronics Spintronics • Conclusion Adrian Ionescu, October 2005 2 40 years of Moore’s law: 1965 - 2005 • 1965: a single transistor cost more than a dollar • 1975: the cost of a transistor had dropped to less than a penny, while transistor size allowed for almost 100,000 transistors on a single die • 1979 to 1999, processor performance went from about 1.5 million instructions per second (MIPS), to almost 50 MIPS on the i486™, to over 1,000 MIPS on the Intel® Pentium® III • Today's Intel® processors run at 3.2 GHz and higher, deliver over 10,000 MIPS, and can be manufactured in high volumes with transistors that cost less than 1/10,000th of a cent Adrian Ionescu, October 2005 3 How it started… Adrian Ionescu, October 2005 4 … and where we are… Source: http://www.intel.com/research/silicon/mooreslaw.htm Adrian Ionescu, October 2005 5 90 nm Intel’s processor First planar integrated Montecito (2004) circuit (1961) Itanium Processor Family Transistors: 1.72 Billion Frequency: >1.7GHz Power: ~100W Source: Intel Developer Forum, September, 2004 Adrian Ionescu, October 2005 6 Source: M. Bohr, Intel Development Forum, September 2004. Adrian Ionescu, October 2005 7 CMOS scaling (1) Alternative devices CMOS Nanotechnology benefits for 100 electronics and m) CMOS IC evolution μ 10 computing: 1 • nano-processors with CMOS 0.1μm in 2002 declining energy 0.1 • ultra-small terra-bit 0.01 level storage Feature Size ( Feature Transition Region Alternative 0.001 Quantum devices • > GHz frequency and devices bandwidth Atomic dimensions • integrated nano- 1960 2000 2020 2040 1980 sensors Year • novel functionalities Adrian Ionescu, October 2005 8 CMOS scaling (2) Classical Scaling Consequence (Denard) Voltage: V/α Higher density: α2 Oxide: tox/α Higher speed: α Wide width: W/α Power: 1/α2 Gate width: L/α Power density: const. Diffusion: xd/α Doping: αNA Deviations from classical scaling • gate leakage • reliability • performance at higher voltage Consequence • increase of power density Adapted after: H-S. P. Wong, et al., Proceedings of the IEEE, vol. 87, No. 4, pp. 537-70, 2001. Adrian Ionescu, October 2005 9 Gate dielectric @ fundamental scaling limit Practical limits on the thickness of the SiO2 gate oxide are crucial. Two fundamental considerations: • roughness to be controlled @ atomic scale: leakage of 1nm oxide increases by 10 every 0.1nm rms roughness • intrinsic transition region to reach bulk SiO2 properties: 0.3-0.5 nm Assume tolerable gate leakage is 100 Acm and gate area is 1% of a 1- cm chip and power-supply voltage of 1 V, the power dissipation due to the gate current is 1 W. J. D. Plummer and P. B. Griffin, Proceedings of the IEEE, Vol. 89, pp. 240 –258, 2001. D. A. Muller et al., Nature, pp. 758-761, June 1999. Adrian Ionescu, October 2005 10 Power is key limiting factor? • Active power • Passive power (gate & subthreshold leakage) Problems: • Server microprocessors cannot simultaneaously use all their transistors due to power limitations • Leakage power limits max usable μP frequency Gate Length (μm) Adrian Ionescu, October 2005 11 Cost limit Adrian Ionescu, October 2005 12 Fundamental limits From: thermodinamics, quantum-mechanics, electromagnetics • Limit on energy transfer during a binary switching: E(min) = (ln2) kT (=kTlogeN, N=2) (J. Neumann) • Heisenberg’s uncertainty principle: ΔE > h/Δt Æ forbidden region for power-delay • electromagnetics Æ τ > L/c0 (limited time of electromagnetic wave travelling across interconnects) Adrian Ionescu, October 2005 13 Why E(min) = kT x ln2 ? Binary signal discrimination: the slope of the static transfer curve of a (CMOS) binary logic gate must be greater than unity in absolute value at the transition point where input and output voltage levels are equal Æ CMOS inverter ⎡ Cfs ⎤ Cd Vdd(min) = 2[]kT / q ⎢1+ ⎥ ln(2 + ) ⎣ Cox + Cd ⎦ Cox kT kT Vdd(min) ≅ 2()ln 2 = 1.38 = 0.036V @T = 300K q q Min signal energy stored on gate: kT Es(min) = (1/ 2)Q Vdd = ()1/ 2 q x 2 ()ln 2 = kT x ln 2 == 0.693kT g q 2 εox Lmin ⎡ t ox ⎤ 2 1/ 2 with : Cg = ⇒ Lmin = ⎢ ⎥q /[]2()ln 2 kT = 9.3nm @ t ox = 1nm t ox ⎣εox ⎦ Source: J.D. Meindl, J. A. Davis, IEEE JSSC, Vol. 35, October 2000, pp. 1515-1516. Adrian Ionescu, October 2005 14 Fundamental limits Average power transfer during a binary transition, P, versus transition time, td. The red, orange, and green zones are forbidden by fundamental, silicon material, and 50-nm channel length transistor device level limits,respectively. Allowable design space Source: J. D. Meindl, Q. Chen, J. A. Davis, Science, Vol. 293, pp. 2044-2049, September 2001 Adrian Ionescu, October 2005 15 MOSFET @ nanoscale: what changes? 10µm Classical transport Gate (collisions, mobility) N+ N+ scattering 1021 ) ) -3 0.2µm 2,5 -3 1020 cm/s) 2 cm/s) classicalClassique 7 7 1,5 1019 Velocity overshoot 1 Quantique 0,5 1018 + 1D quantum effects Concentration d'électrons (cm quantum 0 17 Vitesse (x10 10 Electron conc. (cm Velocity (10 Velocity 0 0,05 0,1 0,0227 0,0237 0,0247 0,0257 Profondeur par rapport à l'interface (µm) 0.1µm Distance alongle long the du channel canal (µm) (μm) Coordinate from surface (μm) Gate Parameter (dopant) N+ N+ fluctuations 20nm Gate Ballistic transport N+ N+ + 2D quantum effects Adrian Ionescu, October 2005 16 Example: Process Variations (1) • main affected parameter: VT • both the discrete random dopant distribution in the channel region and the quantum effects in the inversion layer should be considered for < 100nm • due to channel dopant variations in individual devices, threshold voltage fluctuations in ULSI’s are estimated to exceed 0.1 V in the for less than 0.1 • μm if the doping is not optimized Source: T. Mizuno, IEEE Transactions on Electron Devices, Vol. 47, pp. 756–761, April 2000. A. Asenov et al., IEEE Transactions on Electron Devices, Vol. 48, pp. 722-729, April 2001. Adrian Ionescu, October 2005 17 Example: Process Variations (2) There is a most suitable NA to supress δVT • SOI: • bulk-Si: Design for NA vs Leff in nano-region ULSI: (a) SOI (b) bulk MOSFET’s. The shaded regions indicate suitable NA for ΔI /I < 10%, 6δV < 0.1 V, and suppressing the short channel effects. More design space exists for SOI! Adrian Ionescu, October 2005 18 The ideal MOS switch @ nanoscale: what should be improved? • Control of short channel Quasi-ideal switch effects Æ VT, Ioff • Subthreshold slope: better than 60mV/decade? , log) • Mobility, velocity saturation, lin ballistic transport Æ Ion I ( • Contact and series MOS switch resistances V • Impact of process variations Adrian Ionescu, October 2005 19 Solutions for better-than-60mV/decade subthreshold slope kT C C kT S = ln10 (1+ dep + ss ) → ln10 = 60mV / decade q Cox Cox q Various concepts: • I-MOS • Tunnel FET • NEM-MOSFET • Hybrid devices •… Adrian Ionescu, October 2005 20 I-MOS Subthreshold slope improvement by avalanche breakdown current in gated-diode Source: K. Gopalakrishnan et al., IEEE Transactions on Electron Devices, Vol. 52, Jan. 2005 pp. 69 – 76. Adrian Ionescu, October 2005 21 Si/SiGe Vertical Tunnel FET (1) • Why S < 60mV/decade in tunnel FET? B Sd= (log/ IdV )−1 < 60mV/dec IAV=⋅−ξ exp( ) dgs eff ξ 1 dVeff ξξ+ Bd −1 =+ln10(2 ) VdVeff gsξ dV gs < 60mV/dec / ln10 = 26mV/dec V 2 S = GS Where: 3/ 2 • Bkane depends on effective mass 2VGS + BKane Eg / D • D depends on tox, L, Vds, and dopings Adrian Ionescu, October 2005 22 Si/SiGe Vertical Tunnel FET (2) Subthreshold swing S vs. Ge mole fraction in the δp+ layer Source: K. K. Bhuwalka, J Schulze and I Eisele, J. J. of Appl Phys 43, 4073 (2004) Adrian Ionescu, October 2005 23 Simulation prediction: SS of tunnel FET Issues: • what physics and practical transistor • materials • fabrication S = 1mV/decade @ room temperature Source : P. F. Wang et al. Solid-State Electronics 48, 2281 (2004). Adrian Ionescu, October 2005 24 NEM or Suspended-Gate FET 10-6 0.14 Vd = 50mV 0.12 Source I leakage, Gate -7 (A) 10 d Pull-in 0.1 Drain 0.08 10-8 Suspended-Gate 20μm 0.06 g (pA) Drain current, I 0.04 10-9 0.02 -10 AlSi 1% 10 0 -6 -4 -2 0 2 4 6 8 10 Vg (V) 220nm • ultra-low gate leakage in off-state Gate oxide 40nm (quasi-negligible) Silicon 200nm • 10mV/decade SS demonstrated by EPFL Adrian Ionescu, October 2005 25 Evolutionary MOSFET: more Moore… Source: H-S. P. Wong, et al., Proceedings of the IEEE, vol. 87, No. 4, pp. 537-70, 2001. Adrian Ionescu, October 2005 26 Non-classical MOSFET (1): more Moore… Adrian Ionescu, October 2005 27 Non-classical MOSFET (2): more Moore… Adrian Ionescu, October 2005 28 Emerging (nano)technologies No mature and/or credible candidate for ‘beyond CMOS’ yet! 4-D parametrization of emerging nano-technologies: size x speed x energy x cost Source: J. A. Hutchby et al., IEEE Circuits and Devices Magazine, Vol. 18, pp. 28–41, March 2002. Adrian Ionescu, October 2005 29 Emerging logic devices (…after Moore) Source: ITRS 2003. Adrian Ionescu, October 2005 30 Single/few electron electronics Single Electron Transistor MOS transistor (SET) versus (MOSFET) SET MOSFET Gate Drain (D) Drain CTD , RD Gate Source Drain Gate Source Drain CG VDS n+ n+ Gate (G) CTS ,RS p V GS conductive conductive Source tunneling Source (S) pn+ n-channel junctions island junctions • electron conduction is one by one (!) • many electrons simultaneously • drain & gate control Coulomb blockade (CB) participate to the conduction • needs opaque junctions: • gate controls channel RT > RQ~26kΩ • junctions highly transparent • needs very small island (~1nm) for room • works inherently at room temperature temperature operation Adrian Ionescu, October 2005 31 HOW SET works? SET principle (orthodox theory): K.K.
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