(12) Patent Application Publication (10) Pub. No.: US 2011/0142067 A1 JEHL Et Al
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US 2011 O142067A1 (19) United States (12) Patent Application Publication (10) Pub. No.: US 2011/0142067 A1 JEHL et al. (43) Pub. Date: Jun. 16, 2011 (54) DYNAMIC LINK CREDIT SHARING IN QPI Publication Classification (76) Inventors: Timothy J. JEHL, Gilbert, AZ (51) Int. Cl. (US); Pradeepsunder Ganesh, HO4, 3/02 (2006.01) Chandler, AZ (US); Aimee Wood, (52) U.S. Cl. ........................................................ 370/462 Tigard, OR (US); Robert Safranek, Portland, OR (US); John A. Miller, (57) ABSTRACT Portland, OR (US): Selim Bilgin, A method and system for dynamic credit sharing in a quick Hillsboro, OR (US); Osama path interconnect link. The method including dividing incom Neiroukh, Jerusalem (IL) ing credit into a first credit pool and a second credit pool; and allocating the first credit pool for a first data traffic queue and (21) Appl. No.: 12/639,556 allocating the second credit pool for a second data traffic queue in a manner So as to preferentially transmit the first data (22) Filed: Dec. 16, 2009 traffic queue or the second data traffic queue through a link. NCOMING CREDIT CREDIT SWW CONTROLED SHARING BIAS REGISTERS is LOCAL TRAFFIC LOCAL TRAFFIC CREDITS 26A RTTH TRAFFIC RITH TRAFFIC 28A CREDITS 28B/ 26B 26 2 Patent Application Publication Jun. 16, 2011 Sheet 1 of 2 US 2011/O142067 A1 FIG. LINKO DEVICE FIG. 2 Patent Application Publication Jun. 16, 2011 Sheet 2 of 2 US 2011/O142067 A1 US 2011/O 142067 A1 Jun. 16, 2011 DYNAMIC LINK CREDIT SHARING IN QPI tion only and are not intended as a definition of the limits of the invention. As used in the specification and in the claims, BACKGROUND OF THE INVENTION the singular form of “a”, “an, and “the include plural ref 0001 1. Field of the Invention erents unless the context clearly dictates otherwise. 0002 The present invention pertains to data management, and in particular to a dynamic link credit sharing method and BRIEF DESCRIPTION OF THE DRAWINGS system in quick path interconnect. 0010. In the accompanying drawings: 0003 2. Discussion of Related Art 0011 FIG. 1 is a schematic diagram showing a transmitter 0004 QuickPath Interconnect (QPI) protocol is a credit side and a receiverside of a link, according to an embodiment based protocol. In its simplest form, on a single-processor of the present invention; motherboard architecture, a single QPI is used to connect the processor to the Input-Output (IO) hub. The IO hub can in turn 0012 FIG. 2 is a schematic diagram depicting the local be connected to peripheral devices such as graphics cards, etc. and route-through traffic queues to and from a device, accord The IO hub can further communicate with an Input-Output ing to an embodiment of the present invention; and Controller Hub (e.g., Intel's Southbridge ICH10) for connect 0013 FIG. 3 is a schematic diagram depicting an imple ing and controlling peripheral devices. mentation of a credit sharing mechanism between local data 0005 For example, QPI can be used to connect an Intel traffic queue and route-through data traffic queue at the trans Core i7 processor (a 64-bit x86-64 processor) to an Intel X58 mitter side of the link shown in FIG. 1, according to an IO hub. In more complex instances of the architecture, sepa embodiment of the present invention. rate QPI link pairs connect one or more processors and one or more IO hubs (or routing hubs) in a network on the mother DETAILED DESCRIPTION OF EMBODIMENTS board, allowing all of the components to access other com OF THE INVENTION ponents via the network. As with HyperTransport (a bidirec tional serial/parallel high-bandwidth point-to-point link), the 0014 FIG. 1 is a schematic diagram showing a transmitter QuickPath Interconnect (QPI) architecture allows for side and a receiverside of a link, according to an embodiment memory controller integration, and enables a non-uniform of the present invention. The link 10 has a transmitter side memory architecture (NUMA). (TS) 12 on one side and a receiver side (RS) 14 on the opposite side. For example, the link 10 can use the QuickPath BRIEF SUMMARY OF THE INVENTION interconnect Protocol to connect between the transmitter side 12 (e.g., an Intel Core i7 processor) and a receiver side 14 0006 An aspect of the present invention is to provide a (e.g., an Intel X58 IO hub or another Intel Core i7 processor). method including dividing incoming credit into a first credit The transmitter side (TS) 12 of link 10 must “know’ in pool and a second credit pool; and allocating the first credit advance that adequate space is available on the receiver side pool for a first data traffic queue and allocating the second (RS) 14 of the link 10 before the transmitter side 12 can start credit pool for a second data traffic queue in a manner so as to a given transaction with the receiver side 14. To achieve a preferentially transmit the first data traffic queue or the sec seamless and Substantially error free transmission between ond data traffic queue through a link. the transmission side 12 and the receiverside 14 of the link 10, 0007 Another aspect of the present invention is to provide the receiverside 14 of the link 10 “informs” the transmission a system including a link having a transmitter side and a side 12 of availability of “credit.” In other words, the receiver receiver side; and a controlled bias register configured to side 14 advertises credits to the transmitter side 12. In order to divide incoming credit into a first credit pool and a second inform the transmitter side 12 of the availability of credit on credit pool. The first credit pool is allocated for a first data the receiver side 14, in one embodiment, a communication traffic queue and the second credit pool is allocated for a channel or link 16, independent from link 10, is established second data traffic queue Such that the transmitter side pref between the receiverside 14 and the transmitter side 12 of the erentially transmits the first data traffic queue or the second link 10. The receiverside 14 can then communicate with the data traffic queue through the link. transmitter side 12 via communication path or link 16 to 0008 Although the various steps of the method are inform the transmitter side 12 of availability of credit on the described in the above paragraphs as occurring in a certain receiver side 14. In this way, the transmitter side 12 would order, the present application is not bound by the order in “know” how much room or credit in terms of data size is which the various steps occur. In fact, in alternative embodi available on one or more channels on the receiverside 14. The ments, the various steps can be executed in an order different term data size is used herein to mean in general either flits (80 from the order described above or otherwise herein. bit data portions) or data packets for individual known trans 0009. These and other objects, features, and characteris mission packet types. Although, in this embodiment, the link tics of the present invention, as well as the methods of opera 16 is depicted as being independent from link 10, as it can be tion and functions of the related elements of structure and the appreciated the link 16 can be a sideband of the link 10 to combination of parts and economies of manufacture, will inform the transmitter side 12 of availability of credit at the become more apparent upon consideration of the following receiverside 14. It is noted that the components 12 and 14 are description and the appended claims with reference to the respectively referred to as transmitter side 12 and receiver accompanying drawings, all of which form a part of this side 14, when referring to transmitting data through link 10 specification, wherein like reference numerals designate cor from component 12 to component 14. As it can be appreci responding parts in the various figures. In one embodiment of ated, the components 12 and 14 can act, respectively, as the invention, the structural components illustrated herein are “receiverside” 12 and “transmitter side” 14 when data is sent drawn to scale. It is to be expressly understood, however, that from the component 14 to component 12, for example, when the drawings are for the purpose of illustration and descrip sending information through link 16. US 2011/O 142067 A1 Jun. 16, 2011 0015 For example, in a device, such as for example a transmitter side 12 of link 10 (corresponding to link 1 in FIG. server part optimized for embedded systems, the transmitter 2) includes software (S/W) controlled bias register or regis side 12 within the device services two request queues, one of ters 22, credit sharing or division logic 24 and a data traffic which is a local data traffic queue and the other is a route management engine 26. The data traffic management engine through data traffic queue. Local data traffic is data traffic that 26 includes local data traffic credit repository 26A, route is generated by a processor or processors within the device, through (RTTH) data traffic credit repository 26B, and a data Such as for example data generated by a processor or proces multiplexer (MUX) 26C. Local data traffic queue 28A origi sors within the device. Route-through data traffic is data nating from the transmitter side 12 within the device 20 and traffic that is generated externally to the device, and is simply route-through (RTTH) data traffic queue 28B routed through passing through the device, as explained further in detail in the transmitter side 12 within the device 20 are directed the following paragraphs.