The Fundamentals of EDA for the Financial Community 2013

The Fundamentals of EDA For the Financial Community 2013

• Initially Electronic Design tools were developed by the Electronic OEMs – Most importantly, semiconductor vendors

• What became known as the EDA Industry began in the mid-1960s when companies outsourced commercial “development” of In-House tools

• Unlike all other software industries, semiconductor companies did not outsource design tool “research” – A limiting factor on EDA vendor profits

• The driving force of EDA is Moore’s Law – Every two semiconductor nodes, design tools need significant upgrades

• Periodically, semiconductor vendors produce so many transistors (per IC) that it causes an Inflection Point as we move from one level of abstraction to the next

1964 – 1971 1971 – 1987 Transistor Level Gate Level Methodology Methodology Applicon, Calma & Daisy, Mentor & Computer Vision Valid Main revenue source: Main revenue source: Semiconductor Layout PCB Design (IC CAD)

1987 - 2011 2011 – 2020?

RTL ESL Methodology Methodology Cadence, Mentor & ?????? Synopsys Main revenue source: Main revenue source: Semiconductor Design Embedded Software (CAE & IC CAD) Development Tools

EDA’s Customers

• Power Users – Engineers who push state-of-the-art

• Upper Mainstream – Engineers who lag Power Users by 1-2 silicon nodes

• Lower Mainstream – Engineers whose competitive advantage is not the IC (they usually use FPGAs)

• Late Adopter – Engineers who do low-end (or specialty) designs using low-cost EDA tools

(see Definitions under Research at www.garysmithEDA.com)

Silicon Node EDA Growth In nm in $MM $7.5

Inflection $6.5 Point $5.5

$4.5

$3.5

$2.5

$1.5

Inflection Point $0.5

$0.0

Source: Gary Smith EDA December 2013

Millions of Gates Available Gates 3,500 3,281 3,000 2,731 2,500

2,000

1,500 1,322 1,000 353 658 500 228 35 69 138 177 - 180 nm 130 nm 90 nm 65 nm 45 nm 35 nm 22 nm 16 nm 11 nm 8nm

Source: Gary Smith EDA / ITRS 2013

(in Millions of Dollars)

Super Computer Class Servers Class Computer Super

RTL Functional Verif. Tool Suite Tool Verif. Functional RTL

SMP Processing ParallelSMP bench Test Intelligent Prototype Virtual Silicon

Reusable Platform Blocks Platform Reusable

Very large blockreuse large Very Many Core SW Dev tools SWCore Many Dev Automation System Design

Executable Specification Executable

IC Implementation Tool Set Tool Implementation IC

AMP ProcessingAMP Parallel

Software Virtual Prototype Virtual Software Transaction Level ModelingLevel Transaction $250 $200

$150 115 86 88 86 $100 64 39 66 59 60 28 57 48 $50 43 44 36 71 79 51 51 25 34 35 52 49 67 58 41 43

$0 21 14 19 26 16 21 28 38

2000 2004 2006 2008 2010 2014 2016 2018 2020 2022 2024 2028 2002 2012 2026

Total HW Engineering Costs + EDA Tool Costs Total SW Engineering Costs + ESDA Tool Costs

Source: Gary Smith EDA December 2013 / ITRS 2013

• Negative - Lack of research control limits growth/profits

• Positive - Move from node-to-node drives growth

• EDA revenue is driven by Semiconductor “R&D” budgets

• Seat Count growth is generally ~5% per year

EDA Growth 45% 40% 35% 30% 25% 20% 15% 10% 5% 0% -5% 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 2010 2012 -10%

Source: Gary Smith EDA December 2013

$3,500$3,500 $3,310$3,310 $3,000 $3,000 $2,903 $2,903 CAE $2,500 $2,566 CAE $2,500 $2,612 $2,566 $2,612 $2,281 $2,301$2,301 $2,281 $2,000 $2,000 $2,035 $1,875 $2,035 IC CAD $1,758$1,758 $1,875 IC CAD $1,500$1,500 $1,555$1,555 $1,000$1,000 PCB $788 $676 PCB $500 $714$714 $788 $676 $500 $597$597 $632$632 $0$0 $ millions 20102010 20112011 20122012 20132013 20142014

At the start of the RTL Inflection Point, the three major EDA vendors had the following Franchise Positions:

1. Cadence – Verilog, DRC, ASIC Layout & Custom Layout

2. Synopsys – Logic Synthesis

3. Mentor – (none)

Cadence Mentor Synopsys

• Lost Verilog to an • Gained DRC • Held onto its RTL open standard in franchise in 2005 Franchise 1995 • Contending for • Did not move up • Lost DRC to ISS ESL market along that position into in 1994 which, in with Cadence ESL (High Level turn, lost it to Synthesis) Mentor in 1997

• Lost ASIC Layout to Avant! in 1997 • Contending for ESL market along with Mentor

• At the start of 2013, there were 84 Sub-Applications

• Sub-Applications are where competitive battles are fought

Download our WallCharts at www.garysmithEDA.com

17,435 129,346

Design Architect’s Design Workbench Silicon (SWVP 1) Software Prototyping Virtual Virtual System Prototype Prototype V (hardware) V (SWVP 2) (SVP 1) Validation e e r D r D Middleware i e i Apps Code Emulation e 262,074 f s f & s i 578,677 i i Acceleration i c g c Firmware (hardware) g a n a n 64,673 t t i i Silicon Software o Demo o Virtual Virtual n (hardware) n Design Prototype Prototype (SVP 2) (SWVP 3) Verification Total SWVP 3 = 326,747 Small number Could be same Engineers

Architect's Workbench $60.4

High Level Synthesis $10.8 Transaction-Based Acceleration & Emulation $305.0

Multicore Development Tools $51.9

Software Virtual Prototype $92.6

* ALL DOLLAR FIGURES IN MILLIONS

Intel - CoFluent 3%

MathWorks 97%

Synopsys 6%

Bluespec 19% Forte Design (Cadence) Cadence 31% Design Systems 17% Calypto (Mentor) 27%

Aldec 0.2%

Synopsys 19% Cadence Design Systems Mentor 47% Graphics 33%

Mentor Graphics ARM35% – 100% ARM 65%

Imperas 8% Intel (Virtutech) 13% Mentor Graphics 1%

Synopsys 78%

Design Libraries $54.8

Interop Tools $95.2

Enterprise & CIS Tools $79.8

Analog Design $89.6

RF Design & Simulation $217.9 Analog Simulation $150.5

Power Design $56.3 Timing and Signal Integrity $95.0

Rapid Prototyping $58.0

ATPG $101.7 Synthesis $299.7

Formal Analysis $47.6

Formal Verification $100.3

Mixed Signal Sim $69.4 Mixed Language Sim $451.8

* ALL DOLLAR FIGURES IN MILLIONS

Cadence National 6% Instruments 12%

Ansys Agilent 14% EEsoft 68%

Cadence Design Systems Mentor Graphics 11% 3% Oasys 2%

Synopsys 84%

Aldec 1% AXIOM Design Automation 2%

Cadence Synopsys Design Systems 40% 30%

Mentor Graphics 27%

DFY $73.0

RET $217.8

T-CAD $104.1

Physical Libraries $94.9 IC SPICE $127.9 Signal-Integrity $70.9 Power $82.1 Extraction $116.9

DRC $225.0

Custom $237.3 ASIC Layout $633.2

* ALL DOLLAR FIGURES IN MILLIONS

Atoptech 2%

Cadence Design Systems 26% Synopsys 68% Mentor Graphics 4%

Tanner Research 3%

Silvaco Synopsys 3% 19% Cadence Sagantec Design Systems 8% 54% MicroMagic 1% Mentor Graphics 6% Jedat 6%

Tanner Research 1% Cadence Design Systems 17% Simucad Design Synopsys Automation 20% 1%

Mentor Graphics 61%

Cadence Design Systems 2%

Synopsys Mentor 50% Graphics 48%

* ALL DOLLAR FIGURES IN MILLIONS

Altium 5.3% Ansys 6.3%

Others 13% Cadence Zuken Design 18.4% Systems 21% Mentor Graphics 36%

1963-86 1981-86 1987-2013

Transistor Level Gate Level (RTL) Register Transfer Methodology Methodology Methodology

Bundled Bundled Unbundled Hardware/ Hardware/ (software only) Software Software Moved from (perpetual (perpetual perpetual to license license three-year (variable) for software) for software) license/ratable model

• New tools need to be in place at least a year before the lead node (EDA generation is every two silicon nodes)

• Power Users provide research (often with leading Universities) and produce the first tools – Sets the tool’s price points

• EDA vendors generally target a year or two after the node when there is a sizeable demand for the new tools – Allows start-ups to introduce new commercial tools before large EDA vendors (passing on R&D through large EDA vendors’ acquisition business model)

• Now moving to EDA-driven research due to move to Fabless semiconductor companies without large CAD groups

• The return of the Design Gap – New tools are needed every two process nodes

• The move to ESL and a new revenue stream

• It’s the Software, Stupid

• Mentor has already moved into embedded design tools

• EDA vendors are acquiring IP vendors

• EDA vendors are adopting Parallel Processing to handle today’s hundred million plus gate designs

• Synopsys, Cadence and Mentor are becoming involved in Design Tool “Research”

*Mechatronics +++