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Technological Solution Beyond Mosfet and Binary Logic

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Technological Solution Beyond Mosfet and Binary Logic TECHNOLOGICAL SOLUTION BEYOND MOSFET AND BINARY LOGIC DEVICES A Thesis in Electrical Engineering Presented to the Faculty of University of Missouri Kansas City in partial fulfilment of the requirements for the degree MASTER OF SCIENCE By JILL ARVINDBHAI PATEL Kansas City, Missouri 2018 © 2018 JILL ARVINDBHAI PATEL ALL RIGHTS RESERVED TECHNOLOGICAL SOLUTIONS BEYOND MOSFET AND BINARY LOGIC DEVICES Jill Arvindbhai Patel Candidate for the Master of Science Degree University of Missouri–Kansas City, 2018 ABSTRACT Today’s technology is based on the binary number system-based circuitry, which is the outcome of the simple on and off switching mechanism of the prevailing transistors. Consideration of higher radix number system can eradicate or lessen many limitations of binary number system such as the saturation of Moore’s law. The most substantial potential benefits of higher radix approaches are the decrease of wiring complexity. Excessive scaling of the technologies has led the researchers beyond Binary Logic and MOSFET technology. TFET considered as one of the most promising options for low-power application for beyond MOSFET technologies. Graphene Nano Ribbon, due to its high-carrier mobility, tunable bandgap and its outstanding electrostatic control of device gate becomes ideal choice for channel material of TFET. This paper proposes double gated ultra-thin body (UTB) TFET device model using Graphene nano ribbon as the channel material. In this paper evaluation of the model by performing the comparative analysis with InAs as the channel material in terms of Ec-Ev on and off state and Id-Vg characteristics is presented. The feasibility of multi valued logic system in real-world rests on two serious aspects, such as, the easiness of mathematical approach for implementing the multivalued logic into today’s technology and the sufficiency of synthesis techniques. In this paper, we have focused on the different technology available for implementing multivalued logic especially ternary logic. Ternary logic devices are expected to lead to an exponential increase of the information handling capability, which binary logic cannot support. Memory capacitor or memcapacitor is an emerging device that exhibits hysteresis behavior, which can be manipulated by external parameters, such as, the applied electric field or voltage. One of the unique properties of the memcapacitor is that by using the percolation approach, we can achieve Metal-Insulator-Transition (MIT) phenomenon, which can be utilized to obtain a staggered hysteresis loop. For multivalued logic devices staggered hysteresis behavior is the critical requirement. In this paper, we propose a new conceptual design of a ternary logic device by vertically stacking dielectric material interleaved with layers of graphene nanoribbon (GNR) between two external metal plates. The proposed device structure displays the memcapacitive behavior with the fast switching metal-to-insulator transition in picosecond scale. The device model is later extended into a vertical-cascaded version, which acts as a ternary device. APPROVAL PAGE The faculty listed below, appointed by the Dean of the School of Computing and Engineering, have examined a thesis titled “Technological Solution beyond MOSFET and Binary Logic Device,” presented by Jill Arvindbhai Patel candidate for the Master of Science degree, and certify that in their opinion it is worthy of acceptance. Supervisory Committee Masud Chowdhury, Ph.D., Committee Chair Department of Computer Science & Electrical Engineering Ahmed Hassan, Ph.D. Department of Computer Science & Electrical Engineering Siddiki Mahbube, Ph.D. Department of Computer Science & Electrical Engineering CONTENTS ABSTRACT ....................................................................................................................... iii ILLUSTRATIONS ..................................................................................................................... viii TABLES ..........................................................................................................................................x ACKNOWLEDGEMENTS .............................................................................................. xi Chapter 1 INTRODUCTION .......................................................................................................11 2 MULTI VALUED LOGIC ...........................................................................................12 2.1 Definition and Numeric Representation ..................................................................... 12 3 OVERVIEW OF DIFFERENT MVL TECHNOLOGIES ...........................................15 3.1 Ternary logic using cmos ........................................................................................15 3.2 Resonant tunneling diode (rtd) based ternary logic ................................................16 3.3 Ternary logic using single electron transistor ........................................................19 3.4 Fin field effect transistor based ternary logic .........................................................21 3.5 Ternary logic using quantum dot gate field effect transistor ..................................22 3.6 Ternary logic using cmos and memristor................................................................24 3.7 Ternary logic using cntfet .......................................................................................25 4 GRAPHENE MEMCAPACITOR BASED TERNARY LOGIC DEVICE .................28 4.1 Introduction ..................................................................................................................... 28 4.2 Fundamental concepts and the technological background of proposed device ...... 29 4.3 Proposed ternary device ................................................................................................ 34 4.4 Analysis of the electrical behavior of the proposed mvl device .............................36 4.5 Comparative analysis .............................................................................................37 5 GRAPHENE NANO RIBBON BASED TFET ...........................................................40 5.1 Introduction ..................................................................................................................... 40 5.2 Tfet device structure and operation.........................................................................41 5.3 Graphene nano ribbon as channel material .................................................................... 43 5.4 Proposed device structure ............................................................................................... 45 5.3 Result and analysis .......................................................................................................... 45 6 CONCLUSION AND FUTURE WORK .....................................................................49 REFERENCES ..................................................................................................................50 VITA ..................................................................................................................................53 LIST OF FIGURES Figure Page Figure. 1: a) STI b) PTI and c) NTI 15 Figure. 2 Ternary inverter and NAND gate 16 Figure. 3. Transfer characteristics with 2 resistors and 1 resistor 16 Figure. 4 Resonant Tunneling Diode operation showing the Quantum well 17 Figure.5 RTD I-V Characteristics 17 Figure. 6 (a) Circuit diagram of a down literal MOBILE 18 Figure. 7 (a)Circuit configuration of an up literal MOBILE 18 Figure. 8 Circuit configurations of ternary inverter 18 Figure. 9 Single Electron Transistor 19 Figure.10 Left to right: energy levels of source of set 20 Figure. 11 FinFET structure 21 Figure. 12 Voltage Transfer Curve of FINFET 21 Figure. 13 FINFET based STI 22 Figure. 14 Structural diagrams of QDGFET 23 Figure. 15 IDS Vs VGS in QDGFET 23 Figure .16 STI using QDGFET 23 Figure. 17 Transfer characteristics of QDGFET based STI 24 Figure. 18. Memristive device symbol 25 Figure. 19 Ternary inverter using CMOS and Memristor 25 Figure. 20 Fundamental structure of CNTFET (a) cross-sectional view (b) top view 26 Figure. 21 Proposed design CNTFET based inverter and its’ transfer characteristics 26 Figure. 22 Design of CNTFET based inverter and its transfer characteristics 27 Figure. 23. a) Armchair b) Zigzag GNR 30 Figure. 24. Evidence of the percolation-driven MIT in GNR 31 Figure. 25. MIT material based memcapacitance model 32 Figure. 26 Energy band diagram of the binary device structure 33 Figure. 27 Conductivity of GNR as a function the percolation 34 Figure. 28. Proposed device structure and its equivalent capacitance model 35 Figure. 29 Hysteresis curve showing the percolation states 36 Figure. 30 Energy band diagram of the proposed ternary device structure 37 Figure. 31. Current (I) –Voltage (V) curve for a typical MOSFET 40 Figure. 32 A schematic of an n-channel TFET architecture 41 Figure. 33 The band diagrams of the n-channel TFET in the (a)OFF and (b)ON states 42 Figure.34. Structure of GNR with different edges 43 Figure. 35. Energy band structure E(k) and density of states D(E) of armchair ribbons 44 Figure. 36 Energy band structure E(k) and density of states D(E) of zigzag ribbons. 44 Figure. 37 Proposed device structures 45 Figure. 38 Ec-Ev off for (a)VDD=0.5, (b) VDD=1.0, (c) VDD=1.5 for InAs 46 Figure.39. Ec-Ev on for (a)VDD=0.5, (b) VDD=1.0, (c) VDD=1.5 for InAs 46 Figure. 40. Id-Vg on for (a)VDD=0.5, (b) VDD=1.0, (c) VDD=1.5
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