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Semiconductor Transistors for Logic and Memory

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Semiconductor Transistors for Logic and Memory 1 MTLE-6120: Advanced Electronic Properties of Materials Semiconductor transistors for logic and memory Contents: I Aside: vacuum tubes I Bipolar junction transistors (BJT) I Junction field effect transistors (JFET) I Metal oxide semiconductor (MOS) capacitor and FET I Complementary MOS (CMOS) logic circuits I Memory: registers, dynamic RAM and flash Reading: I Kasap 6.6 - 6.8 2 Vacuum tube diodes I Thermionic emission from cathode I Electrons collected at anode with positive bias I Anode not heated: cannot emit electrons ) no reverse current I Nominally similar characteristics to pn-junction diode Images: Wiki: Vacuum tubes 3 Vacuum tube triodes I Control plate / grid between cathode and anode I Negative bias repels electrons; reduces current I Small changes in voltage ) large changes in current I Acts as a switch or amplifier Images: Wiki: Vacuum tubes 4 Vacuum tube computers I Each triode in own separate tube I ENIAC computer in 1946: 17468 such tubes I Key characteristic required: three terminal device where third terminal controls current between first two I In principle: computer made entirely of hydrualically or pneumatically-controlled valves! Images: Wiki: Vacuum tubes 5 Bipolar Junction Transistor (BJT) I Heavily doped emitter E (like cathode in triode) I Thin lightly-doped base B (like control plate / grid) I Lightly-doped collector C (like anode) I Either pnp (shown above) or npn (polarities reversed) I Which one does the vacuum tube triode correspond to? 6 BJT: junction potentials I Two pn-junctions: E-B and C-B I Normal (active) operation: forward-bias E-B and reverse-bias C-B I E-B junction: depletion region mostly in base I C-B junction: comparitively symmetrical I Potential drop across depletion regions; negligible field in interiors 2 ni eVEB Hole concentration at B-end of E-B junction: pn(0) = exp I Nd kB T I Hole concentration at B-end of C-B junction: pn(WB) ≈ 0 7 BJT: current flow 2 pn0 eADhni eVEB Diffusion current across base: IE ≈ IC = eADh = exp I WB NdWB kB T I Current out of n-type base has to be electrons: two factors in α ≡ IC =IE 1 I Electron current in E-B: small due to asymmetric doping γ = N W µ 1+ d B e NaWE µh 2 WB =(2Dh) Recombination: small for thin lightly-doped base αT = 1 − I τh I Current transfer ratio α = γαT & 0:99 for typical BJTs α 2 3 I Current gain β ≡ IC =IB = 1−α ∼ 10 − 10 8 BJT: IV characteristics I Ideal characteristic: IC = IE independent of VCB I Leakage current in reverse-biased C-B junction, ICB0 I At high VCB, IC = αIE + ICB0 and IB = (1 − α)IE − ICB0 I But slope of IC vs VCB increases for finite IE (beyond ICB0) I Early effect: C-B depletion width increases with VCB I This reduces WB, making hole diffusion easier, and therefore IE " 9 BJT: common base amplifier eVEB Small changes in E-B potential strongly affect IC ≈ IE = IE0 exp I kB T I Convert ‘amplified’ current to voltage using resistor I Collector potential VCB = −VCC + RC IC I Voltage gain (controlled by selecting IE and RC ): @VCB @IC IERC = RC = @VEB @VEB kBT 10 BJT: common emitter amplifier I Note npn-transistor: polarities reversed I Current amplifier: input IB amplified by β to output IC I With leakage current, IB = (1 − α)IE − ICB0 and I I = I − I = βI + CB0 C E B B 1 − α | {z } ICE0 I Operate at VCE > VBE, else saturation: IC limited by IE 11 Junction Field-effect Transistor (JFET) I n-JFET: narrow n channel between p+ gates (reversed for p-JFET) I Width of n channel determined by depletion regions I Basic idea: control channel width and conduction using gates I Always operate with channel potential > gate ) reverse bias 12 JFET: channel IV characteristics I First consider applied VDS with VGS = 0 I Voltage of channel-gate junction increases from S to D I Correspondingly increasing depletion width narrows channel I Increase VDS, current ID increases, but channel narrows sat I At VDS , channel pinches off at D end, ID saturates 13 JFET: gate effects I Apply negative gate potential: VDG increases I Narrower depletion region, earlier pinch off sat sat I VDS = VP + VGS, where pinchoff voltage VP = VDS at VGS = 0 I Therefore, gate potential controls channel current and effective resistance off I Strong-enough VGS shuts off channel completely ) VGS off 2 I Empirical behaviour: IDS = IDSS 1 − VGS=VGS 14 JFET amplifier I Amplifier: gate voltage controls channel current I Convert channel current to voltage through resistor RD I Vaguely similar to common-emitter amplifier I Set operating `quiescent' point at center of operating range I Signal amplitudes small enough to stay in range I Voltage gain @VDS RD@IDS 2IDSSRD VGS = = off 1 − off @VGS @VGS VGS VGS 15 Metal-oxide-semiconductor (MOS) capacitor Metal Oxide Semiconductor Metal Oxide Semiconductor Metal Oxide Semiconductor I Metal and SC separated by an insulating oxide: why don't the bands bend? I Apply potential: linear variation in oxide, typical bending in SC I Vacuum level (potential) continuous, D? continuous I For p-SC and positive Vmetal, CB bends towards EF I For Vmetal > Vth (threshold), CB closer than VB to EF I Inversion region: n > p in p-type semiconductor I Analogous case with reversed potentials for n-type semiconductors 16 Metal-Oxide-SC Field-effect Transistor (MOSFET) I Enhancement n-channel MOSFET: metal-p capacitor surrounded by n+ I MOS inversion: generates an n channel at surface I Comparison with n-JFET: existing channel suppressed by gate junction I Analogous depletion n-MOSFET: replace p above with light n I Flip n $ p and polarities ) enhancement and depletion p-MOSFETs 17 MOSFET: gate response I For VGS < Vth, n+ contacts separated by depletion layer I No channel ) ID = 0 irrespective of VDS I One VGS > Vth, inversion layer forms an n-channel I For low VDS, channel behaves like an Ohmic resistor 18 MOSFET: drain response I Increasing VDS causes reduction in VGD I Channel begins to narrow near drain; current starts to level off sat I At VDS = VDS = VGS − Vth, channel pinches off at drain end I Beyond this potential, ID does not increase with increasing VDS 19 MOSFET: IV characteristics sat I Saturation drain voltage VDS = VGS − Vth 2 I Saturation drain current IDS = K(VGS − Vth) (1 + λVDS) Cµe I Coefficient K ∼ 2L2 , where C = MOS capacitance, L = channel length I Coefficient λ due to Early effect (exactly like in BJT, JFET) I Similar characteristics to JFET ) similar amplifier circuits I Switching: VGS > Vth ) RDS small (on) vs VGS < Vth ) RDS large (off) off on I On-off ratio RDS=RDS, switching time ∼ RC 20 Complementary MOS (CMOS) logic I Complementary MOS: combine p and n-MOS transistors I Inverter / NOT gate: Vin < Vth ) Vout = Vdd, Vin > Vth ) Vout = Vss I Digital logic: for input 0 and 1, output 1 and 0 respectively I NOR (NOT OR) gate: output 0 (NOT 1) if any input 1 I NAND (NOT AND) gate: output 0 (NOT 1) if all inputs 1 I Any logic or arithmetic operation using just three gates! 21 Arithmetic circuits I XOR (exclusive OR) gate: output 1 if exactly one input 1 I 1-bit adder: sum bit = XOR, carry bit = AND I 8-bit adder: chain bit additions together I N-bit adder: requires / N log2 N gates I N-bit multiplier: adder of N numbers with N-bits each 22 Example: Xeon Phi 7210 I 64 compute cores I Each core: 8× 64-bit multipliers I Net: 1012 64-bit math operations per second I 8 × 109 CMOS transistors in 8 cm2 of Si! 23 Bistable latches (flip-flops) I When R = S = 0: latch stores previous value I Feedback loop between two inverters I S = 1 sets value to 1, R = 1 resets it to 0 I Volatile memory: data lost when circuit powered off I Mechanism used in registers and static RAM I Minimum 8 transistors / bit as shown above (low-density, high power) 24 Dynamic RAM I Bit = whether capacitor is charged I Transistor in off state: capacitor isolated; retains charge I To read, transistor in specific row and column switched on I Reading destroys state; must be written back I State lost due to leakage ) refresh circuitry I Volatile: charge retention only ∼ 100 ms I 1 transistor / bit: high-density, low power I 8GB DDR4 memory: 8 × 109 transistors in < 10 cm2 Si 25 Flash memory / SSD: floating-gate transistors I Floating gate transistor: bit = whether floating gate is charged I Charge on floating gate affects Vth I Read bit by checking if transistor is on at specified VGS I Write bit by hot-electron injection from channel I Erase bit by Fowler-Nordheim tunneling to upper gate I NOR-flash: closer to random-access; erase only in large blocks I NAND-flash: all access in large pages / blocks (eg. SSD).
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