Lab 10: Picoblaze – an Embedded Microcontroller

Lab 10: PicoBlaze – an embedded microcontroller EE-459/500 HDL Based Digital Design with Programmable Logic Electrical Engineering Department, University at Buffalo Last update: Cristinel Ababei, November 2 2012

1. Objective

The objective of this lab is to utilize PicoBlaze - an embedded into the FPGA fabric 8-bit microcontroller - to implement a simple circuit that takes as input two 4-bit binary numbers, a and b (set via the slide switches of the Atlys board), and computes a2+b2, result which is displayed on the 8 LEDs of the Atlys board. As part of this lab, you will learn assembly language, which is utilized to code the algorithm that PicoBlaze must execute.

2. Preparation

As part of this lab preparation you must fully read chapters 14 and 15 of Pong. P. Chu’s book [1]. This lab is created based on those two chapters. In addition, you should read additional materials included in the downloadable archive with all the files for this lab [2,3]. Please allocate enough time to do this especially if you do not have prior experience with microcontroller architectures and/or assembly languages.

The PicoBlaze processor is a compact 8-bit microcontroller core for Xilinx FPGA devices. It is freely provided as a cell-level HDL description (referred to also as a soft-core) and can be synthesized along with other logic as part of a bigger digital design. It is optimized for efficiency and occupies very little area. It is recommended to be utilized for simple data-processing and control applications. Single or multiple copies of the PicoBlaze processor can be easily integrated into larger systems to add flexibility to FPGA-based designs. The PicoBlaze design was originally named KCPSM which stands for “Constant(K) Coded Programmable State Machine” (formerly “Ken Chapman's PSM”). Ken Chapman is the Xilinx systems designer who devised and implemented the microcontroller.

You should also know that there is also MicroBlaze – another soft processor core designed for Xilinx FPGAs from Xilinx. However, it is not free, and you would need Xilinx’s EDK (Embedded Development Kit) tool to be able to build MicroBlaze embedded processor systems in Xilinx FPGAs.

PicoBlaze is based on a RISC architecture of 8-bits and can reach speeds up to 100 MIPS on the Virtex-4 FPGA's family. The processors have an 8-bit address and data port for access to a wide range of peripherals. The latest version (available for download on Xilinx’s website for registered users) is KCPSM6. Its main characteristics include: - Only 26 Slices plus program memory (BRAM). - Performance 52 MIPS to 120 MIPs depending on device family and clock rate. - Supports programs up to 4K instructions. - 32 General Purpose Registers arranged in 2 banks. - 256 General Purpose Input Ports. - 256 General Purpose Output Ports. - 16 Constant-Optimised Output Ports. - 64-bytes of scratch pad memory expandable to 128 and 256-bytes (additional 2 and 6 Slices).

- Fully automatic CALL/RETURN stack supporting nested subroutines to 30 levels. - Interrupt with user definable interrupt vector and maximum response time of 4 clock cycles. - Power saving features including 'sleep' mode. - Superset of KCPSM3 with high degree of code compatibility.

3. Lab Description

In this lab, we design a digital system that is uses a PicoBlaze microcontroller to compute a2+b2. a and b are two 4-bit numbers input via the slide switches of the Atlys board. The result is displayed on the 8 LEDs of the Atlys board. To do this, we follow the steps described below and illustrated in Fig.1.

Figure 1 Block diagram of example1 design

Step 1: Determine the software-hardware partition

Decide about the structure of the design. In this example, the functionality of our design is very simple, so we only need a single instance of the PicoBlaze microcontroller. Basically it’s an all software implementation.

Step 2: Develop the assembly program for the software portion

Because of its simplicity, PicoBlaze cannot effectively support high-level programming languages (such as C) and the code is generally developed in assembly language. Developing a complete assembly program consists of the following steps: -1-Derive the pseudocode of the main program. -2-Identify tasks in the main program and define them as subroutines. In needed, continue refining the complex subroutines and divide them into smaller subroutines. -3-Determine the register and data RAM use. -4-Write the assembly code for the subroutines.

The main program usually has the following structure: call initialization_routine forever: call task_1_routine call task_2_routine ... call task_n_routine jump forever

The result of steps 1,2,4 is the assembly program in file example1_sio_rom.psm that you find in the example1/ folder of the downloadable archive of this lab. Please read it thoroughly to see what and how it does achieve al the tasks. The structure of the main program is: call clear_data_ram forever: call read_switch call square call write_led jump forever

Step 3 above is unique for assembly code development because we must manually allocate the data storage in assembly code. In this example, the allocation of the data RAM is done as shown in Fig.2.

Figure 2 Allocation of data RAM 3

Step 3: Compiling with KCSPM6

The assembly code (file example1_sio_rom.psm in our example) is placed in the same folder (say example1/ in our case) with the assembler, which is kcpsm6.exe that is part of the PicoBlaze files downloaded from Xilinx. Also in the same folder we must place the file ROM_form.vhd (also part of the PicoBlaze files downloaded from Xilinx). This is a template used by kcpsm6.exe. Invoke a DOS window, navigate to the project directory, and run the program. Type: kcpsm6 example1_sio_rom.psm

After successful compilation, several files are created. The one that we need is the one that contains the block RAM VHDL entity that we’ll plug into our top-level design. In this example this file is example1_sio_rom.vhd.

Step 4: Create the ISE WebPack project and test

Use the following source files to create a new ISE project and then implement the top-level design. kcpsm6.vhd – the VHDL file of the PicoBlaze microcontroller (comes with PicoBlaze files from Xilinx) example1_sio_rom.vhd – the instruction ROM entity; contains basically our program to be executed example1_top_level.vhd – top-level description of our design example1_top_level.ucf – you should know what this is

Generate bitstream file and download it to the FPGA. Test operation and comment.

4. Lab Assignment

Use PicoBlaze microcontroller to design a circuit that implement a Binary-to-BCD converter. Write the assembly code, compile, create a top-level design, implement, and test on Atlys board. Use 8 slide switches to input an 8-bit binary number. The BCD code should drive the 8 LEDs.

Optional: Read also chapters 16 and 17 of P.P. Chu’s book and then implement some more complex design of your choice.

5. Credits and references

[1] Pong P. Chu, FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version, Wiley 2008. [2] Ken Chapman, PicoBlaze for Spartan-6, Virtex-6 and 7-Series (KCPSM6), USER GUIDE (comes with PicoBlaze files from Xilinx). [3] Ken Chapman, PicoBlaze 8-Bit Microcontroller for Virtex-E and Spartan-II/IIE Devices. Xilinx Application Note. http://www.xilinx.com/support/documentation/application_notes/xapp213.pdf