July 10, 2015 Revision 6.02 Document Number: MD00090 Privileged Resource Architecture Privileged Resource Vol. III: MIPS32® / microMIPS32™ III: MIPS32® / Vol. MIPS® Architecture For Programmers Programmers Architecture For MIPS® any warranty of any kind. any kind. of any warranty ged Resource Architecture, Rev. 6.02 ect to change noticewithout ‘as is’, and is supplied without l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. . This publication contains proprietary information which is subj information proprietary contains publication . This 2 MIPS® Architecture Vo For Programmers Template: nB1.03, Built with tags: 2B ARCH MIPS32 2B ARCH nB1.03, with tags: Built Template: Public Contents

Chapter 1: About This Book ...... 13 1.1: Typographical Conventions ...... 14 1.1.1: Italic Text...... 14 1.1.2: Bold Text...... 14 1.1.3: Courier Text ...... 14 1.2: UNPREDICTABLE and UNDEFINED ...... 14 1.2.1: UNPREDICTABLE...... 14 1.2.2: UNDEFINED ...... 15 1.2.3: UNSTABLE ...... 15 1.3: Special Symbols in Pseudocode Notation...... 15 1.4: For More Information ...... 18

Chapter 2: The MIPS32 and microMIPS32 Privileged Resource Architecture ...... 19 2.1: Introduction...... 19 2.2: The MIPS Model ...... 19 2.2.1: CP0 - The System Coprocessor ...... 19 2.2.2: CP0 Registers...... 19

Chapter 3: MIPS32 and microMIPS32 Operating Modes...... 21 3.1: Debug Mode ...... 21 3.2: Kernel Mode ...... 21 3.3: Supervisor Mode ...... 21 3.4: User Mode ...... 22 3.5: Other Modes...... 22 3.5.1: 64-bit Floating-Point Operations Enable ...... 22 3.5.2: 64-bit FPR Enable...... 22 3.5.3: Coprocessor 0 Enable...... 23 3.5.4: ISA Mode ...... 23

Chapter 4: ...... 25 4.1: Differences between Releases of the Architecture...... 25 4.1.1: Virtual Memory...... 25 4.1.2: Protection of Virtual Memory Pages...... 25 4.1.3: Context Register ...... 25 4.1.4: Segmentation Control ...... 26 4.1.5: Enhanced Virtual Addressing...... 26 4.2: Terminology...... 26 4.2.1: Address Space...... 26 4.2.2: Segment and Segment Size ...... 26 4.2.3: Physical Address Size (PABITS) ...... 26 4.3: Virtual Address Spaces ...... 26 4.4: Compliance...... 29 4.5: Access Control as a Function of Address and Operating Mode...... 30 4.6: Address Translation and Cacheability and Coherency Attributes for the kseg0 and kseg1 Segments..... 30 4.7: Address Translation for the kuseg Segment when StatusERL = 1...... 31 4.8: Special Behavior for the kseg3 Segment when DebugDM = 1...... 31

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4.9: TLB-Based Virtual Address Translation ...... 31 4.9.1: Address Space Identifiers (ASID) ...... 32 4.9.2: TLB Organization ...... 32 4.9.3: TLB Initialization...... 33 4.9.4: Address Translation ...... 36 4.10: Segmentation Control ...... 40 4.10.1: Exception Behavior under Segmentation Control ...... 43 4.11: Enhanced Virtual Addressing ...... 48 4.11.1: EVA Segmentation Control Configuration...... 48 4.11.2: Enhanced Virtual Address (EVA) Instructions...... 50 4.12: Hardware Walker ...... 52 4.12.1: Multi-Level Page Table support ...... 53 4.12.2: PTE and Directory Entry Format...... 57 4.12.3: Hardware page table walking process ...... 60

Chapter 5: Common Device Memory Map...... 67 5.1: CDMMBase Register...... 67 5.2: CDMM - Access Control and Device Register Blocks ...... 68 5.2.1: Access Control and Status Registers...... 69

Chapter 6: and Exceptions...... 71 6.1: Interrupts ...... 71 6.1.1: Modes...... 72 6.1.2: Generation of Exception Vector Offsets for Vectored Interrupts...... 81 6.2: Exceptions ...... 82 6.2.1: Exception Priority ...... 83 6.2.2: Exception Vector Locations...... 84 6.2.3: General Exception Processing...... 86 6.2.4: EJTAG Debug Exception ...... 89 6.2.5: Reset Exception...... 89 6.2.6: Soft Reset Exception...... 90 6.2.7: Non Maskable Interrupt (NMI) Exception...... 91 6.2.8: Machine Check Exception...... 92 6.2.9: Address Error Exception ...... 92 6.2.10: TLB Refill Exception...... 93 6.2.11: Execute-Inhibit Exception...... 94 6.2.12: Read-Inhibit Exception...... 94 6.2.13: TLB Invalid Exception ...... 95 6.2.14: TLB Modified Exception ...... 96 6.2.15: Cache Error Exception...... 97 6.2.16: Bus Error Exception ...... 97 6.2.17: Integer Overflow Exception...... 98 6.2.18: Trap Exception...... 98 6.2.19: Exception ...... 98 6.2.20: Breakpoint Exception ...... 99 6.2.21: Reserved Instruction Exception ...... 99 6.2.22: Coprocessor Unusable Exception...... 100 6.2.23: Floating-Point Exception ...... 100 6.2.24: Coprocessor 2 Exception...... 101 6.2.25: Watch Exception ...... 101 6.2.26: Interrupt Exception...... 102

4 MIPS® Architecture For Programmers Vol. III: MIPS32® / microMIPS32™ Privileged Resource Architecture, Rev. 6.02 Chapter 7: GPR Shadow Registers ...... 103 7.1: Introduction to Shadow Sets...... 103 7.2: Support Instructions...... 104

Chapter 8: CP0 Hazards ...... 105 8.1: Introduction...... 105 8.2: Types of Hazards ...... 105 8.2.1: Possible Execution Hazards ...... 105 8.2.2: Possible Instruction Hazards...... 107 8.3: Hazard Clearing Instructions and Events ...... 107 8.3.1: MIPS32 Instruction Encoding...... 108 8.3.2: microMIPS32 Instruction Encoding...... 109

Chapter 9: Coprocessor 0 Registers ...... 111 9.1: Coprocessor 0 Register Summary ...... 111 9.2: Notation ...... 117 9.3: Writing CPU Registers...... 117 9.4: (CP0 Register 0, Select 0)...... 119 9.5: VPControl (CP0 Register 0, Select 4) ...... 121 9.6: Random Register (CP0 Register 1, Select 0)...... 123 9.7: EntryLo0, EntryLo1 (CP0 Registers 2 and 3, Select 0) ...... 125 9.8: Global Number Register (COP0 Register 3, Select 1) ...... 135 9.9: Context Register (CP0 Register 4, Select 0) ...... 137 9.10: ContextConfig Register (CP0 Register 4, Select 1)...... 141 9.11: UserLocal Register (CP0 Register 4, Select 2) ...... 143 9.12: Debug ContextID (CP0 Register 4, Select 4) ...... 145 9.13: PageMask Register (CP0 Register 5, Select 0) ...... 147 9.14: PageGrain Register (CP0 Register 5, Select 1) ...... 151 9.15: SegCtl0 (CP0 Register 5, Select 2) ...... 157 9.16: SegCtl1 (CP0 Register 5, Select 3) ...... 157 9.17: SegCtl2 (CP0 Register 5, Select 4) ...... 157 9.18: PWBase Register (CP0 Register 5, Select 5) ...... 161 9.19: PWField Register (CP0 Register 5, Select 6)...... 161 9.20: PWSize Register (CP0 Register 5, Select 7)...... 164 9.21: Wired Register (CP0 Register 6, Select 0) ...... 169 9.22: PWCtl Register (CP0 Register 6, Select 6) ...... 171 9.23: HWREna Register (CP0 Register 7, Select 0) ...... 175 9.24: BadVAddr Register (CP0 Register 8, Select 0) ...... 177 9.25: BadInstr Register (CP0 Register 8, Select 1) ...... 179 9.26: BadInstrP Register (CP0 Register 8, Select 2)...... 181 9.27: Count Register (CP0 Register 9, Select 0)...... 183 9.28: Reserved for Implementations (CP0 Register 9, Selects 6 and 7) ...... 183 9.29: EntryHi Register (CP0 Register 10, Select 0)...... 185 9.30: Compare Register (CP0 Register 11, Select 0)...... 187 9.31: Reserved for Implementations (CP0 Register 11, Selects 6 and 7) ...... 187 9.32: (CP Register 12, Select 0) ...... 189 9.33: IntCtl Register (CP0 Register 12, Select 1) ...... 199 9.34: SRSCtl Register (CP0 Register 12, Select 2)...... 203 9.35: SRSMap Register (CP0 Register 12, Select 3) ...... 207 9.36: Cause Register (CP0 Register 13, Select 0) ...... 209 9.37: NestedExc (CP0 Register 13, Select 5) ...... 215 9.38: Exception (CP0 Register 14, Select 0) ...... 217 9.38.1: Special Handling of the EPC Register in Processors that Implement MIPS16e ASE or microMIPS32

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Base Architecture...... 217 9.39: Nested Exception Program Counter (CP0 Register 14, Select 2) ...... 219 9.40: Identification (CP0 Register 15, Select 0) ...... 221 9.41: EBase Register (CP0 Register 15, Select 1)...... 223 9.42: CDMMBase Register (CP0 Register 15, Select 2) ...... 227 9.43: CMGCRBase Register (CP0 Register 15, Select 3)...... 229 9.44: BEVVA Register (CP0 Register 15, Select 4) ...... 231 9.45: Configuration Register (CP0 Register 16, Select 0) ...... 233 9.46: Configuration Register 1 (CP0 Register 16, Select 1) ...... 237 9.47: Configuration Register 2 (CP0 Register 16, Select 2) ...... 241 9.48: Configuration Register 3 (CP0 Register 16, Select 3) ...... 245 9.49: Configuration Register 4 (CP0 Register 16, Select 4) ...... 253 9.50: Configuration Register 5 (CP0 Register 16, Select 5) ...... 259 9.51: Reserved for Implementations (CP0 Register 16, Selects 6 and 7) ...... 267 9.52: Load Linked Address (CP0 Register 17, Select 0) ...... 269 9.53: Memory Accessibility Attribute Register (CP0 Register 17, Select 1) ...... 271 9.54: Memory Accessibility Attribute Register Index (CP0 Register 17, Select 2)...... 277 9.55: WatchLo Register (CP0 Register 18) ...... 279 9.56: WatchHi Register (CP0 Register 19)...... 281 9.57: Reserved for Implementations (CP0 Register 22, all Select values)...... 283 9.58: Debug Register (CP0 Register 23, Select 0)...... 285 9.59: Debug2 Register (CP0 Register 23, Select 6)...... 287 9.60: DEPC Register (CP0 Register 24) ...... 289 9.60.1: Special Handling of the DEPC Register in Processors That Implement the MIPS16e ASE or microMIPS32 Base Architecture ...... 289 9.61: Performance Counter Register (CP0 Register 25) ...... 291 9.62: ErrCtl Register (CP0 Register 26, Select 0) ...... 295 9.63: CacheErr Register (CP0 Register 27, Select 0) ...... 297 9.64: TagLo Register (CP0 Register 28, Select 0, 2) ...... 299 9.65: DataLo Register (CP0 Register 28, Select 1, 3)...... 301 9.66: TagHi Register (CP0 Register 29, Select 0, 2)...... 303 9.67: DataHi Register (CP0 Register 29, Select 1, 3) ...... 305 9.68: ErrorEPC (CP0 Register 30, Select 0) ...... 307 9.68.1: Special Handling of the ErrorEPC Register in Processors That Implement the MIPS16e ASE or microMIPS32 Base Architecture ...... 307 9.69: DESAVE Register (CP0 Register 31)...... 309 9.70: KScratchn Registers (CP0 Register 31, Selects 2 to 7) ...... 311

Appendix A: Alternative MMU Organizations ...... 313 A.1: Fixed Mapping MMU ...... 313 A.1.1: Fixed Address Translation...... 313 A.1.2: Cacheability Attributes...... 316 A.1.3: Changes to the CP0 Register Interface...... 317 A.2: Block Address Translation ...... 317 A.2.1: BAT Organization ...... 317 A.2.2: Address Translation...... 318 A.2.3: Changes to the CP0 Register Interface...... 319 A.3: Dual Variable-Page-Size and Fixed-Page-Size TLBs...... 319 A.3.1: MMU Organization...... 319 A.3.2: Programming Interface ...... 321 A.3.3: Changes to the TLB Instructions ...... 322 A.3.4: Changes to the COP0 Registers ...... 323 A.3.5: Software Compatibility...... 324

6 MIPS® Architecture For Programmers Vol. III: MIPS32® / microMIPS32™ Privileged Resource Architecture, Rev. 6.02 Appendix B: Revision History ...... 327

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Figures

Figure 4.1: Virtual Address Space ...... 27 Figure 4.2: References as a Function of Operating Mode ...... 29 Figure 4.3: References as a Function of Operating Mode ...... 29 Figure 4.4: Contents of a TLB Entry ...... 32 Figure 4.5: Legacy addressability ...... 49 Figure 4.6: EVA addressability...... 49 Figure 4.7: Legacy to EVA address configuration...... 50 Figure 4.8: Page Table Walk Process ...... 54 Figure 4.9: Page Table Walk Process & COP0 Control fields ...... 55 Figure 4.10: 4-byte Leaf PTE...... 58 Figure 4.11: 4-byte Non-Leaf PTE Options...... 58 Figure 4.12: 4-Byte Rotated PTE Formats...... 58 Figure 4.13: 8-byte Leaf PTE...... 59 Figure 4.14: 8-Byte Non-leaf PTE Options ...... 59 Figure 4.15: 8-Byte Rotated PTE Formats...... 59 Figure 5.1: Example Organization of the CDMM ...... 69 Figure 5.2: Access Control and Status Register ...... 69 Figure 6.1: Interrupt Generation for Vectored Interrupt Mode...... 77 Figure 6.2: Interrupt Generation for External Interrupt Controller Interrupt Mode...... 80 Figure 9.1: Index Register Format ...... 119 Figure 9.2: VPControl Register Format...... 121 Figure 9.3: Random Register Format ...... 123 Figure 9-4: EntryLo0, EntryLo1 Register Format in Release 1 of the Architecture...... 125 Figure 9-5: EntryLo0, EntryLo1 Register Format in Release 2 of the Architecture...... 126 Figure 9-6: EntryLo0, EntryLo1 Register Format in Release 3 of the Architecture ...... 128 Figure 9-7: EntryLo0, EntryLo1 Register Format in Release 5 ...... 129 Figure 9.8: Global Number Register Format...... 135 Figure 9.9: Context Register Format when Config3CTXTC=0 and Config3SM=0...... 137 Figure 9.10: Context Register Format when Config3CTXTC=1 or Config3SM=1...... 138 Figure 9.11: ContextConfig Register Format ...... 142 Figure 9.12: UserLocal Register Format...... 143 Figure 9.13: Debug ContextID Register Format ...... 145 Figure 9.14: PageMask Register Format ...... 147 Figure 9-15: PageGrain Register Format...... 151 Figure 9.16: SegCtl0 Register Format (CP0 Register 5, Select 2)...... 157 Figure 9.17: SegCtl1 Register Format (CP0 Register 5, Select 3)...... 158 Figure 9.18: SegCtl2 Register Format (CP0 Register 5, Select 4)...... 158 Figure 9.19: PWBase Register Format ...... 161 Figure 9.20: PWField Register Format ...... 163 Figure 9.21: PWSize Register Format ...... 166 Figure 9.22: Wired And Random Entries In The TLB ...... 169 Figure 9.23: Wired Register Format...... 170 Figure 9.24: PWCtl Register Format...... 172 Figure 9.25: HWREna Register Format ...... 175 Figure 9.26: BadVAddr Register Format...... 177 Figure 9.27: BadInstr Register Format...... 179 Figure 9.28: BadInstrP Register Format ...... 181

8 MIPS® Architecture For Programmers Vol. III: MIPS32® / microMIPS32™ Privileged Resource Architecture, Rev. 6.02 Figure 9.29: Count Register Format ...... 183 Figure 9.30: EntryHi Register Format ...... 185 Figure 9.31: Compare Register Format ...... 187 Figure 9.32: Status Register Format for Pre-Release 6...... 189 Figure 9.33: Status Register Format for Release 6 ...... 189 Figure 9.34: IntCtl Register Format...... 199 Figure 9.35: SRSCtl Register Format ...... 203 Figure 9.36: SRSMap Register Format...... 207 Figure 9.37: Cause Register Format...... 209 Figure 9.38: NestedExc Register Format...... 215 Figure 9.39: EPC Register Format...... 217 Figure 9.40: NestedEPC Register Format ...... 219 Figure 9.41: PRId Register Format ...... 221 Figure 9.42: EBase Register Format ...... 223 Figure 9.43: EBase Register Format ...... 224 Figure 9.44: CDMMBase Register ...... 227 Figure 9.45: CMGCRBase Register...... 229 Figure 9.46: BEVVA Register Format ...... 231 Figure 9.47: Config Register Format...... 233 Figure 9.48: Config1 Register Format...... 237 Figure 9.49: Config2 Register Format...... 241 Figure 9-50: Config3 Register Format ...... 245 Figure 9.51: Config4 Register Format (Pre-Release 6) ...... 253 Figure 9.52: Config4 Register Format (Release 6) ...... 253 Figure 9.53: Config5 Register Format...... 259 Figure 9-54: LLAddr Register Format (pre Release 5)...... 269 Figure 9-55: LLAddr Register Format (Release 5 and after)...... 269 Figure 9-56: MAAR Register Format ...... 273 Figure 9.57: MAARI Index Register Format...... 277 Figure 9.58: WatchLo Register Format...... 279 Figure 9.59: WatchHi Register Format ...... 281 Figure 9.60: Performance Counter Format ...... 291 Figure 9.61: Performance Counter Counter Register Format...... 294 Figure 9-62: Example TagLo Register Format...... 299 Figure 9.63: ErrorEPC Register Format...... 307 Figure 9.64: KScratchn Register Format ...... 311 Figure A.1: Memory Mapping when ERL = 0 ...... 315 Figure A.2: Memory Mapping when ERL = 1 ...... 316 Figure A.3: Config Register Additions...... 317 Figure A.4: Contents of a BAT Entry...... 318

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Tables

Table 1.1: Symbols Used in Instruction Operation Statements...... 15 Table 4.1: Virtual Memory Address Spaces...... 28 Table 4.2: Address Space Access as a Function of Operating Mode...... 30 Table 4.3: Address Translation, Cacheability and Coherency Attributes for the kseg0 and kseg1 Segments ...... 31 Table 4.4: Physical Address Generation...... 40 Table 4.5: Segment Configuration for 3GB EVA ...... 50 Table 4.6: EVA Load/Store Instructions...... 51 Table 4.7: Address translation behavior for EVA load/store instructions ...... 51 Table 4.8: Address translation behavior for ordinary load/store instructions ...... 52 Table 5.1: Access Control and Status Register Field Descriptions...... 69 Table 6.1: Interrupt Modes...... 72 Table 6.2: Request for Interrupt Service in Interrupt Compatibility Mode ...... 73 Table 6.3: Relative Interrupt Priority for Vectored Interrupt Mode...... 76 Table 6.4: Exception Vector Offsets for Vectored Interrupts...... 81 Table 6.5: Interrupt State Changes Made Visible by EHB ...... 82 Table 6.6: Priority of Exceptions ...... 83 Table 6.7: Exception Type Characteristics ...... 84 Table 6.8: Exception Vector Base Addresses...... 85 Table 6.9: Exception Vector Offsets ...... 85 Table 6.10: Exception Vectors ...... 86 Table 6.11: Value Stored in EPC, ErrorEPC, or DEPC on an Exception...... 87 Table 7.1: Instructions Supporting Shadow Sets ...... 104 Table 8.1: Possible Execution Hazards ...... 105 Table 8.2: Possible Instruction Hazards ...... 107 Table 8.3: Hazard Clearing Instructions...... 107 Table 9.1: Coprocessor 0 Registers in Numerical Order ...... 111 Table 9.2: Read/Write Notation...... 117 Table 9.3: Index Register Field Descriptions ...... 119 Table 9.4: VPControl Register Field Descriptions...... 121 Table 9.5: Random Register Field Descriptions...... 123 Table 9.6: EntryLo0, EntryLo1 Register Field Descriptions in Release 1 of the Architecture ...... 126 Table 9.7: EntryLo0, EntryLo1 Register Field Descriptions in Release 2 of the Architecture ...... 127 Table 9.8: EntryLo Field Widths as a Function of PABITS ...... 127 Table 9.9: EntryLo0, EntryLo1 Register Field Descriptions in Release 3 of the Architecture ...... 128 Table 9.10: EntryLo0, EntryLo1 Register Field Descriptions in Release 5 of the Architecture ...... 130 Table 9.11: EntryLo Field Widths as a Function of PABITS in Release 5...... 132 Table 9.12: Cacheability and Coherency Attributes...... 133 Table 9.13: Global Number Register Field Descriptions...... 135 Table 9.14: Deriving Unique VPNum ...... 136 Table 9.15: Context Register Field Descriptions when Config3CTXTC=0 and Config3SM=0...... 137 Table 9.16: Context Register Field Descriptions when Config3CTXTC=1 or Config3SM=1...... 138 Table 9.17: ContextConfig Register Field Descriptions ...... 142 Table 9.18: Recommended ContextConfig Values...... 142 Table 9.19: UserLocal Register Field Descriptions...... 143 Table 9.20: Debug ContextID Register Field Descriptions...... 145 Table 9.21: PageMask Register Field Descriptions ...... 147 Table 9.22: Values for the Mask and MaskX1 Fields of the PageMask Register ...... 148

10 MIPS® Architecture For Programmers Vol. III: MIPS32® / microMIPS32™ Privileged Resource Architecture, Rev. 6.02 Table 9.23: PageGrain Register Field Descriptions...... 151 Table 9.24: SegCtl0 Register Field Descriptions ...... 157 Table 9.25: SegCtl1 Register Field Descriptions ...... 158 Table 9.26: SegCtl2 Register Field Descriptions ...... 158 Table 9.27: CFG (Segment Configuration) Field Description...... 158 Table 9.28: Segment Configuration Access Control Modes ...... 159 Table 9.29: Segment Configuration legacy reset state ...... 159 Table 9.30: Segment Configuration partitioning of MIPS32 address space...... 160 Table 9.31: PWBase Register Field Descriptions ...... 161 Table 9.32: PWField Register Field Descriptions...... 163 Table 9.33: PWSize Register Field Descriptions ...... 166 Table 9.34: PS/PTEW Usage ...... 167 Table 9.35: Wired Register Field Descriptions...... 170 Table 9.36: PWCtl Register Field Descriptions...... 172 Table 9.37: HugePg Field and Huge Page configurations...... 173 Table 9.38: Huge Page representation in Directory Levels ...... 173 Table 9.39: HWREna Register Field Descriptions ...... 175 Table 9.40: RDHWR Register Numbers ...... 176 Table 9.41: BadVAddr Register Field Descriptions...... 177 Table 9.42: BadInstr Register Field Descriptions...... 179 Table 9.43: BadInstrP Register Field Descriptions ...... 181 Table 9.44: Count Register Field Descriptions ...... 183 Table 9.45: EntryHi Register Field Descriptions ...... 185 Table 9.46: Compare Register Field Descriptions ...... 187 Table 9.47: Status Register Field Descriptions...... 190 Table 9.48: IntCtl Register Field Descriptions...... 199 Table 9.49: SRSCtl Register Field Descriptions ...... 203 Table 9.50: Sources for new SRSCtlCSS on an Exception or Interrupt ...... 204 Table 9.51: SRSMap Register Field Descriptions...... 207 Table 9.52: Cause Register Field Descriptions...... 209 Table 9.53: Cause Register ExcCode Field...... 212 Table 9.54: NestedExc Register Field Descriptions...... 215 Table 9.55: EPC Register Field Descriptions...... 217 Table 9.56: NestedEPC Register Field Descriptions ...... 219 Table 9.57: PRId Register Field Descriptions ...... 221 Table 9.58: EBase Register Field Descriptions ...... 224 Table 9.59: EBase Register Field Descriptions ...... 224 Table 9.60: Conditions Under Which EBase15..12 Must Be Zero ...... 225 Table 9.61: CDMMBase Register Field Descriptions...... 227 Table 9.62: CMGCRBase Register Field Descriptions ...... 229 Table 9.63: BEVVA Register Field Descriptions ...... 231 Table 9.64: Config Register Field Descriptions...... 233 Table 9.65: Config1 Register Field Descriptions...... 237 Table 9.66: Config2 Register Field Descriptions...... 241 Table 9.67: Config3 Register Field Descriptions...... 245 Table 9.68: Config4 Register Field Descriptions...... 253 Table 9.69: Config5 Register Field Descriptions...... 260 Table 9.70: SegCtl0K Segment CCA Determination ...... 265 Table 9.71: LLAddr Register Field Descriptions (pre Release 5)...... 269 Table 9.72: LLAddr Register Field Descriptions (Release 5 and after)...... 270 Table 9.73: MAAR Register Field Descriptions...... 273 Table 9.74: Valid Determination for MAAR Pair...... 275 Table 9.75: Speculate Determination for MAAR Pair...... 275

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Table 9.76: MAARI Index Register Field Descriptions...... 277 Table 9.77: WatchLo Register Field Descriptions...... 279 Table 9.78: WatchHi Register Field Descriptions...... 281 Table 9.79: Example Performance Counter Usage of the PerfCnt CP0 Register...... 291 Table 9.80: Performance Counter Control Register Field Descriptions ...... 292 Table 9.81: Performance Counter Counter Register Field Descriptions...... 294 Table 9.82: Example TagLo Register Field Descriptions...... 299 Table 9.83: ErrorEPC Register Field Descriptions...... 307 Table 9.84: KScratchn Register Field Descriptions...... 311 Table A.1: Physical Address Generation from Virtual Addresses...... 313 Table A.2: Config Register Field Descriptions ...... 317 Table A.3: BAT Entry Assignments...... 318

12 MIPS® Architecture For Programmers Vol. III: MIPS32® / microMIPS32™ Privileged Resource Architecture, Rev. 6.02

chitecture 32® Architecture and the and 32® Architecture Privileged Resource Architecture Architecture Privileged Resource not be implemented at the same be not the MIPS® Ar MIPS® the ocessor implementation to the MIPS64® Architecture and ed Resource Architecture, Rev. 6.02Architecture, ed Resource 13 e MIPS® Architecture itecture the microMIPS32™ instruction set the microMIPS32™ instruction Privileged Privileged Resource Architecture which defines and fic ExtensionMIPS32® to the Architecture. Beginning ecific Extension to the MIPS ecific Extension to the MIPS® Architecture MIPS® Arch document set nor the microMIPS32™ document set. With document set nor the microMIPS32™ document set. With e document set, and provides an introduction to the n-Specific Extension to n-Specific Extension n-Specific Extension to the MIPS® Architecture included in a MIPS® pr is the preferred solution for smaller code size. itecture Module to th eachinstruction in the MIPS32® instruction set Vol. III: MIPS32® / microMIPS32™ Vol. Module to the P Module tothe is is deprecated. MDMX and MSA can riptions riptions of each instruction in III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Architecture . Architecture microMIPS64™. It is not applicable to the MIPS32® Architecture, MDMX of the Release 5 microMIPS32™ governs the behaviorprivileged of theresources microMIPS of the Architecture, 3 with Release time. MIPS32® Architecture microMIPS32™ •describes the MIPS® DS IV-e Volume • describes the MIPS® MT IV-f Volume •MIPS16e™ Application-Speci the describes IV-a Volume • describesExtension MDMX the ™ Application-Specific IV-b Volume • describesApplication-SpSmartMIPS® the IV-d Volume •describes the MIPS-3D® Applicatio IV-c Volume •desc detailed II-B provides Volume •MIPS32®the III describes microMIPS32™ and Volume • describesMCUApplicatioMIPS® the IV-h Volume • II-A provides detailed descriptions of Volume •describes I-B conventions used throughoutthe document set, and providesan introduction the to Volume • Module describes to the theMIPS® MIPS® Virtualization Architecture IV-i Volume • describesSIMDArchMIPS® the IV-j Volume The MIPS® For Programmers Architecture the followingconsists of documents: • I-A describes conventions used throughout th Volume MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For About This Book About Chapter 1 Chapter

, S, D register). , such as as , such bits, which are dress bits used by an that internal state operations can cause Status register es of code and instructiones indicates numbers 5 through operations executed in user 5..1 ged Resource Architecture, Rev. 6.02 ective (for instance, ad ective (for instance, UNPREDICTABLE contents of memorycontents of or results mustnot depend on any datasource floating point instruction formats UNPREDICTABLE uncached ent processor mode. on the and for exampl screen, fonts in this book. and results or operations. behavior, as defined below. behavior, UNDEFINED are used throughout thisbook to describethe behavior of the pro- , write, or modify the the modify or write, , om a hardware perspective (for instance, om a hardware perspective cached courier and UNPREDICTABLE is For instance, is indicated by an ellipsis. and results or results operationshave several implementationrestrictions: accessible in the curr accessible behavior or operations. Conversely, both privileged and behaviorUNDEFINED or operations. Conversely, bold and registers), and various various and registers), and , behavior or operationsonlyof canresult executingas theinstructions occur in , that are important from a software persp , that are important defined ble only to hardware) processor mode. For example, italic UNPREDICTABLE and UNDEFINED that are important fr important that are registers operations must not read operations must UNPREDICTABLE , fields UNDEFINED operationscan causeresultgenerated not. a to be or UNPREDICTABLE fields and , bits emphasis UNPREDICTABLE fixed-widthtextusedis displayed font thatfor is PS is inaccessible in the current UNPREDICTABLE (memory or internal state) that is in or internal state) (memory software, programmable and fields and not programmable but accessi programmable not 1 • • Implementations of operations generating arbitrary exceptions. arbitrary exceptions. pseudocode. a privilegeda theor withMode,usable mode(i.e., in Kernel Mode or Debug CP0 bit set in the UNPREDICTABLE The terms cessor in certain cases. Courier •is used for for used •is •is used for bits for used •is •that is being term a represents •is used for for used •is This section describes the use of describes This section • as such types, the memory access used for is • used is for ranges of numbers; the range Unprivileged softwarecause can never unprivileged software can cause • used to emphasize is 1.2.1 UNPREDICTABLE 1.1.3 Courier Text 1.1.2 Bold Text 1.1.1 Text Italic 14microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers 1.2 and UNDEFINED UNPREDICTABLE 1.1 Conventions Typographical About This Book This About

is less y e 100 256). (decimal restore restore the processor to an onment inwhich execution e 100 (decimal 256). If the "b#" 256). If (decimal e 100 Kernel Mode or Debug Mode or in or Debug Kernel Mode e hexadecimal valu ation bit (rightmost is 0) is used. If ed Resource Architecture, Rev. 6.02Architecture, ed Resource 15 . 1.3 Special SymbolsPseudocode in Notation toenter a state from which thereno is exit other x they can create an envir on, subtraction. y of the reset signals must of the reset signals y Meaning as pseudocode in a high-level language notation resembling . Little-endian bit not x ltiplication (both used for either). for used (both ltiplication arithmetic: additi arithmetic: y (zero length) bit string. length) bit y (zero rnal state that is only accessible in accessible that is only rnal state of bit string z cimal value 100, 2#100 100, 2#100 represents decimal value the the represents instance 10#100 b. For represents the binary value 100 (decimal 4). 0b100 example: 2. For th represents example: 0x100 16. For copies of the single-bit value the copies of y operations or behaviorcause can dataloss. ble in the current processor mode. ss-than comparison. III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: through through n in base n in base n in base y operationsnot mustor haltprocessor. hang the UNDEFINED , this expression is an empt z -bit string formed by y Table 1.1 Table Statements Operation Instruction in Used Symbols Tests for equality, inequality. for equality, Tests concatenation. string Bit complement or floating-point 2’s than than Assignment. bits of Selection mu complement or floating-point 2’s A 10. is base the default is omitted, prefix division. Floating-point le complement 2’s comparison. complement greater-than 2’s binary value 16#100 represents 100 (decimal and the hexadecimal 4), valu lists the special symbols used in thesymbolsin pseudocode lists the specialused notation.    y another process. UNPREDICTABLE mode must not access memory or an inte an memory or access not mode must   , ,   y z x  div complement integer division. 2’s 0bn A constant value b#n A constant value 0xn A constant value   x *, mod modulo. complement 2’s Symbol • Algorithmic descriptions of an operation are described Pascal. Table 1.1 valueresults in a legal transientvalue thatwas at some correcttimeprior to thesam- UNSTABLE an of A sampling results mustnot depend on any data source (memory pling. Implementationsoperations of generating UNSTABLE which is inaccessi internal state) or UNDEFINED operations or behavior can have no impoact, or than poweringthan down The assertion the of an processor (hang). operational state. operations ormustcause operations behavior notUNDEFINED processor the can no longer continue.can no longer 1.2.3 UNSTABLE 1.2.2 UNDEFINED 1.3 Symbols in Pseudocode Notation Special MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

is RE LLbit the endianness of the the endianness CPU can be computed as be computed CPU can y exception return instruc- return y exception lable in User mode only. It mode only. in User lable as (SR can be computed ic read-modify-write. ic read-modify-write. . ged Resource Architecture, Rev. 6.02 1 for big-endian). In In User mode, this endi- 1 for big-endian). COC[1] . , x] register. Thus, BigEndian register. onal store. It is cleared (b onal is always zero. In Release 2 of the Architecture, tions that provide atom tions that provide ructions. This feature is avai is feature This ructions. CSS x Status register. Thus, ReverseEndian Thus, register. x. Meaning copies of the CPU general-purpose registers can be imple- of the registers copies CPU general-purpose GPR[0] . ore to the is no ore location longer atomic. s Status into the corresponding 32-bit GPR number. GPR 32-bit corresponding into the has the same value as x general-purpose registers. general-purpose bit in the bit in the , register s RE . . and StoreMemory pseudocode function descriptions), and the endian- and descriptions), function pseudocode and StoreMemory tested by the conditi by the tested x SGPR[ SRSCtl x. x bit of the

x . The content of x RE unit 1), general register unit 1), general in zeros at left-hand-side). in zeros n or equal comparison. and store instructions (0 for little-endian, little-endian, (0 for instructions store and in zeros at right-hand-side). in zeros gured 1 Specifies at chip big-endian). for reset (0 for little-endian, endianness of load and store inst and load endianness of refers to GPR set condition condition signal. , control register , general register x,register select , general (32 or 64), of the CPU of the 64), or (32 z 2, general register z z erand register erand register state used to specify operation for instruc to specify operation state used SGPR[s,x] virtual s complement less-tha s complement memory interface (see LoadMemory memory interface ness of Kernel mode execution. and Supervisor setting the be switched by anness can set when a linked load occurs and is linked a set when when a st operation, CPU other tions) during is implemented by setting the the by setting is implemented (BigEndianMem XOR (BigEndianMem XOR ReverseEndian). Translation of GPR number the MIPS16e Translation Bitwise logical OR. logical Bitwise 2’ unit Coprocessor Logical shift left (shift register CPU general-purpose 2’s complement greater-than-or-equal comparison. greater-than-or-equal complement 2’s for notation is a short-hand GPR[x] and User mode). and User Bit of mented. op Floating-point Floating-point Floating-point condition code CC. FCC[0] Floating-point (coprocessor (coprocessor Floating-point unit Coprocessor Coprocessor unit Coprocessor Logical shift right (shift Logical shift right Table 1.1Table (Continued) Statements Operation in Instruction Used Symbols   or << >> not Bitwise inversion. norxor NOR. logical Bitwise XOR. logical Bitwise and Bitwise logical AND. &&AND. Logical (non-bitwise) LLbit Xlat[x] FPR[x] FPR[x] GPR[x] COC[z] Symbol CCR[z,x] GPRLENlength, in bits The FCC[CC] SGPR[s,x] multiple Architecture, the of 2 on Release From CPR[z,x,s] CP2CPR[x] unit Coprocessor CP2CCR[x] unit Coprocessor 2, control register ReverseEndian Signal to reverse the BigEndianCPU endianness for load The BigEndianMem Endian mode as confi 16microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers About This Book This About

regis- Status during the PC address of the instruc- is bit is a 1, the processor is bit is a 1, the processor s the instruction time dur- time s the instruction state.The value isfalseif quences of statements for next instruction. Such an next instruction. Such time is determined by assign- tion. Within one pseudocode one pseudocode tion. Within ograms must not depend on a must not depend ograms pseudocode appears to occur. pseudocode appears to occur. h the is processor executing. register. ed in the delay slot of a branch of the delay slot in ed bytes. appears to occur “at the same the same “at to occur appears static 1 36 during an instruction time by any + I ion or the microMIPS base architec- the microMIPS or ion Status = 2 h are significant during a memory ref- symbol PABITS. If 36 physical address symbol PABITS. rn from this pseudocode function; the from this pseudocode rn that writesthe result registersection in a struction, this is the is the this struction, r as the type of exception, and the argument and the argument r as the type of exception, e stated, all effects of the current instruction current instruction the of effects e stated, all PABITS ed Resource Architecture, Rev. 6.02Architecture, ed Resource 17 struction, or into a Coprocessor 0 register on an an on register 0 into a Coprocessor or struction, is computed from the FR bit in the in the the FR bit from is computed ble indirectly, such as when the processorstoresa indirectly, ble ons as a label. It indicate ons as a label. 1.3 Special SymbolsPseudocode in Notation instruction. No label is equivalent to a time label of of label time a to is equivalent No label instruction. Meaning ither earlier or later (during ither earlier or later (during the instruction time of by 2 either (in the case of a 16-bit MIPS16e instruc- for the following instruc I immediately or jump, but immediately follows a branch which is not order. However, between between se However, order. not available until after the tion operation is written in sections labeled with the the with labeled in sections is written operation tion there is no defined order. Pr there is no defined order. , in which the effect of that , in which the effect had thirty-two 32-bit FPRs. If th I Meaning determines the mode in whic If no value is assigned to PC value is If no statethe of instruction,thenot ility mode in which the processor references the the if it FPRs as were processor references in which the mode ility FP32RegisterMode xecute.” Unless otherwis Unless xecute.” ction operation description ction operation description ll 32-bit address, all bits of whic bits of 32-bit address, all ll ing the exception paramete for the current instruction labelled for the current dynamic the Program Counter address was execut is computed from FR in the from the bit is computed al address bits implemented by the by bits implemented address al the physical is address space 2 description lines and functi and lines description ssor 0 register on an exception. register on ssor 0 ruction time. A taken branch assigns the target address to the to the address the target assigns A branch taken time. ruction specific argument. does not retu Control specific argument. 01 32-bit MIPS instructions. instructions. microMIPS or MIIPS16e tion such sections. between the point of the call. of the the point on. In this case, eudocode statements labeled eudocode value.instruction During the an in time of is a single-bit register that Encoding Operation III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: during an instruction time. time. during an instruction FP32RegistersMode 1. ISA Mode + s whether the FPU has or 64-bit 32-bit floating point registers the (FPRs). FPU has 32 64-bit FPRs I Program Counter Program . Sometimes, effects of an instructionSometimes,.appear of effects to occur e Causes an exception Causes an exception to be signaled us parameter as an exception- signaled at exception is executed in the delay slot of a branch or jump. Indicates whether the instruction at or jump. This the condition reflects a branch or jump occurs to an instruction whose PC operates with thirty-two 64-bit FPRs. 64-bit thirty-two with operates The value of ter. If this bit is a 0, the processor operates as if it it if as operates processor the 0, is a bit this If ter. in in which 64-bit data types are in any FPR. stored a compatib MIPS64 implementations have implementati MIPS32 a This iss a prefix to a prefix This iss ing to ing which “e the pseudocode appears time” as the effect of ps of the effect as time” appear to occur during the instruction time of the current of the current time the instruction occur during appear to I another instruction). When this happens, the this happens, instruc another When instruction). instruction current the to relative time instruction example,For an instructionhave can a result thatis has the of the instruction portion instru different instructions that occur “at the same time,” time,” same the “at occur that instructions different particular order of evalua labeled labeled of pseudocode statements The effect in place take of the statements effects the sequence, next instruction during the that occurs the instruction The address of tion word. a value to PC ing pseudocode statement,pseudocode is it automatically incremented tion) or 4 before the next inst before the or 4 tion) instruction time of the instruction in the branch delay slot. delay branch the in of the instruction time instruction the restart stores processor as when the such indirectly, visible is only PC the value MIPS Architecture, In the address into a GPR on a jump-and-link in or branch-and-link exception. The PC value contains a fu The The bits are implemented, the size of combined value of the upper bits of PC and the ISA Mode into a GPR on a jump-and-link or branch-and-link on a jump-and-link or branch-and-link Mode into a GPR the upper bits of PC and the ISA value of combined Coproce a into or instruction, In the MIPS Architecture, the ISA Mode value is only visi only ISA Mode value is the the MIPS Architecture, In erence. the tures, Table 1.1Table (Continued) Statements Operation in Instruction Used Symbols :, n: :, I PC I- I+n laySlot PABITS Represents the number of physic Symbol ISA ModeExtens Specific In processors Application that implement the MIPS16e tion, argument) tion, FP32RegistersMode Indicate InstructionInBranchDe- SignalException(excep- MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

. [email protected] ged Resource Architecture, Rev. 6.02 chitecturethis document, or send email to http://www mips.com Various MIPS RISC processorMIPS RISC manuals and additional informationproductsbefound about at the MIPS MIPS can Various URL: Forcomments or questions on the MIPS32® Ar 18microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers 1.4 More Information For About This Book This About

Chapter 9, components of the components s, as well as specific well as s, as ous instructions such as the system copro- the as such s the mechanismsmanage to the e effects of some e effects nts are visible nts are visible only to the operating ed as such in the architecture docu- such ed as CP0 is through vari e CP0 registers are described in ed Resource Architecture, Rev. 6.02Architecture, ed Resource 19 0, the system coprocessor, is required. CP0 is the CP0 is required. is 0, the system coprocessor, r extendsr the functionalityISA, while of the MIPS the CPU. Some , the CPU. Some coprocessors, the interaction with them makeupmuch the PRA.of ontrol of the processor state and modes. state and of the processor ontrol l, with one exception: CP ed Resource Architecture (PRA) provide Architecture (PRA) ed Resource critical resources. The interface to critical resources. The interface andard parts of the ISA and are specifi the ISA of andard parts caches, exceptions, and user contexts. contexts. Th caches, and user exceptions, coprocessors. coprocessors. A coprocesso out, Many other componeare user-visible. III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: opcode, including register CP0 the ability the to movefrom, data to, and COP0 ments. Coprocessors are generallyments. Coprocessors are optiona ISA interface to the PRA and provides full c “Coprocessor 0 Registers” on page“Coprocessor 111. cessor and the floating-point unit,are st The CP0 registers provide the The CP0 registers provide the interface between the the ISA and PRA. Th resources of the CPU: virtual memory, virtual memory, resources of the CPU: sharing the instructionfetch andexecution control logic of ing system: exception handling, memory handling, operating system: exception an to support of the functions necessary abstraction provides an CP0 management, scheduling, and control of The MIPS ISA provides for upto four The MIPS32 and microMIPS32 Privileg MIPS32 microMIPS32 and The PRA, such as the virtual memory lay PRA,memory such as the virtual to and system kernel systems programmers. encoded with the functionsthat modify The CP0 registers CP0 state. and 2.2.2 CP0 Registers 2.2.1 CP0 - The System Coprocessor MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 2.2 Model MIPS Coprocessor The 2.1 Introduction Architecture Architecture The MIPS32 and microMIPS32 Privileged Resource Resource Privileged microMIPS32 and The MIPS32 Chapter 2 Chapter

ged Resource Architecture, Rev. 6.02 20microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers The MIPS32 and microMIPS32 Privileged Resource Architecture

reg- Debug form virtual ties of the processor, as processor, ties of the as a flat, uni as a three conditions are false, ailable to Kernel Mode oper- Kernel ailable to ext switch between processes. ext switch between enabled by 64-bit operations ocessor implements Debug implements ocessor Supervisor Mode and EJTAG Debug Mode and EJTAG Supervisor upt, exception, or error. The processor upt, exception, or error. ed Resource Architecture, Rev. 6.02Architecture, ed Resource 21 ided by the ISA, as well by the ISA, as ided register is 0 (if the pr mer can access the full capabili full the mer can access ions that previously were ss to all resources that are av to all resources ss Mode when all of the previous the when all of Mode Debug system environment,system and cont cessor implements Debug Mode). cessor implements bit in bit the two operating modes: User Mode and Kernel Mode. In User Mode, the DM wer-up, or as the result of an interr wer-up, plementationtwo additional of modes: register contains 0b00. III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: ecture added support for 64-bit coprocessors (and, in particular, 64-bitfloating-pointadded ecture support for coprocessors 64-bit (and,inparticular, Status registeris 1. register is 1. register is 0 (if register the pro Status Status Debug field in the CP0 the CP0 field in bit inthe bit in the bit in the DM ERL KSU EXL • The The processorisoperatingThe Supervisor in Mode (if that optional mode is implemented theby processor) when all of the following are true: • The The processor is in Kernel Mode is The processor when the For processors that implement EJTAG, the processor is operating in Debug Mode if the DM bit in the CP0 For processors that implement EJTAG, units)Thus, with certainCPUs. 32-bit floating-point instruct The MIPS32 and microMIPS32 PRA requires that are prov CPU and FPU registers the programmer can access Mode, program the system In Kernel space. memory address as changewell thevirtual memory mapping, control the The MIPS PRA also supports the im specification for a description of Debug Mode. Mode. See the EJTAG Release 2 of the MIPS32 Archit on a MIPS64 processorenablednew64-bit by noware floating-point operations. Release 3 introduced the micro- instructionMIPS set, allowing all microMIPS processors to implementfloating-pointa 64-bit unit. Mode), and any of the following is true: • The The processor enters Kernel Mode at po enters Kernel Mode processor The Supervisor leaves Kernel Mode and enters User Mode or • The ister is 1. If the processor is in Debug Mode, it has full acce in Debug Mode, it has full is 1. If the processor is ister usuallyERET instruction.result of an as the ations. MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 3.3 Mode Supervisor 3.2 Mode Kernel 3.1 Mode Debug MIPS32 and microMIPS32 Operating Modes Operating and microMIPS32 MIPS32 Chapter 3 Chapter

bit in the the in bit F64 are contained in even- processors. From Release 3 From Release processors. r. In Release 2 of the Architecture, r. bit is 1, the FPRs are interpreted as 1, the FPRs are is bit ged Resource Architecture, Rev. 6.02 uding all microMIPS processors. As of of As processors. microMIPS all uding FR point operations are never {{Verify}} point operations are never {{Verify}} e, 64-bit data types =1 is required; that is, the64-bit FPU, with the FR bit is 0, the FPRs are interpretedare thebit as thirty-two FPRs is 0, 32- FR register. If the If register. , 64-bit floating-point operations are enabled if the F64 for both MIPS32 and MIPS64 and MIPS64 MIPS32 both for Status under the followingconditions: =0 32-bit FPU register model32-bit FPUregister =0 continues to be required. cessor implements Debug Mode). Debug cessor implements FR bit inthe FR also implementfloating-point the Release datatype. 3 introduced the are supported for all processors, incl all processors, for supported are when all of the following are true: the following are of all when FPRs are supportedprocesso in a MIPS64 register are both 0. register are register are both 0. Status Status oating-point is implemented, then UNPREDICTABLE register contains 0b10. contains register register contains 0b01. contains register contain a 32-bit data type (W, S). In this cas In this S). (W, data type a 32-bit contain register is 0 (if register the pro int Operations Enable Status Status Debug bits in the bits in the ERL ERL register is 1. FIR field in the field in field in the field in and and bit in the bit is 0, and an odd register is referenced by an instructionregister is datatypewhoseis 0, and an oddbits. bitis64 bit is 0, 64-bit operations bit is 0, 64-bit operations are enabled, and a floating-point instruction is executed whose datatype is L or FR EXL DM KSU KSU EXL FR register is 1. The processor must The register is 1. PS. FIR microMIPS instruction set; on all microMIPS processors bit in the in the bit enabled in a MIPS32 processor. MIPS32 enabled in a =1 64-bit=1model, FPU register The is required. • The bit registers, any of which can of which any registers, bit odd pairs of registers. Release1 of the Architecture , 64-bit In • The • The The operation of the processor is operation The • The thirty-twothatregisters can containIf the 64-bittype. any data • In an implementation of Release 2 or later of the , 64-bit floating-point operations are enabled if the FR Access to 64-bit FPRs is controlled by the to Access Instructions that are implementedbya 64-bit floating-pointlegalunitare the under following any of conditions: •Architecture, 64-bit floating- the an implementation of Release 1 of In The processor is operating in User Mode is operating in User The processor • The • The • The 64-bit FPRs are supported in a 64-bit floating-point unit, fl if Architecture, Release 5 of the and later of theand later Architecture, of 64-bit FPRs 3.5.2 FPR Enable 64-bit 3.5.1 Floating-Po 64-bit 22microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers 3.5 Modes Other 3.4 Mode User MIPS32 MIPS32 and microMIPS32 Operating Modes

3.5 Modes Other For processors that Mode Switch” for a Switch” for Mode processors that implement processors as GPR31 when writtenas GPR31 when a by zero selects MIPS32. zero selects , Section 5.3, “ISA ed Resource Architecture, Rev. 6.02Architecture, ed Resource 23 instruction set family, microMIPS32. Devices can instruction set family, 1 selects microMIPS32. For use when decodinguse when normallyThis bit instructions. is not a jump target address, such a jump target a branch of second the and microMIPS32) or onlymicroMIPS32)and one branch. III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: gister for a JR instruction. a JR instruction. gister for register is 1. t the MIPS32 ISA, the ISA Mode bit value of Status ASE, the ISA Mode bit value of 1 selects MIPS16e. A processor is not allowed to implement both not allowed to A processor is MIPS16e. selects ASE, the ISA Mode bit value of 1 bit in the the in bit ™ Volume II-B: Introduction to the microMIPS32 Instruction to the Set II-B: microMIPS32 Introduction Volume CU0 implement the microMIPS32 ISA, the ISA Mode bit value of the MIPS16e JAL instruction, or the source re For that implemen processors MIPS16e and microMIPS. read Please Release 3 of the Architecture introduced introduced of the Architecture Release 3 branches (MIPS32 implement both ISA specify to used is whichISA Mode bit ISA branch to The visible to software. Its value is saved to any GPR used as Access to Coprocessorto Access 0 registersare enabled under anyfollowing of the conditions: • Theisrunning processorKernel in Mode or Debug above.as defined Mode, • The detailed description of ISA mode switching between the ISA branches and the ISA Mode bit. 3.5.4 ISA Mode 3.5.3 Coprocessor 0 Enable MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

ged Resource Architecture, Rev. 6.02 24microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers MIPS32 MIPS32 and microMIPS32 Operating Modes

(Read Inhibit) (Read RI is expected to be in to be is expected bits. bits. ). XI ). / thin a linear array contain- bit. RI MaskX ESP register can be used more gen- register ecificationnot do overlap. VPN2X table entry (PTE) array. In Releases table entry (PTE) array. ntaining a address pointer to an arbi- ntaining a address field to the left by two bits, when 1 kB Context SP PageGrain ed Resource Architecture, Rev. 6.02Architecture, ed Resource 25 ler than 4 kB. Such usage the SmartMIPS™ ASE specification, but bits the SmartMIPS™ ASE specification, but Config3 modified original from the SmartMIPS definition. For nded, or suggested, to replace the default 4 kB page size; to or suggested, nded, 16-byte structure 16-byte inmemory wi bits can be separately implemented. For 3 ver- the Release by the SmartMIPS ASE sp XI Release 3 version of the Release 3 bit; it is enabledbythe and rol bits are added to each TLB entry. These bits, These bits, entry. each TLB added to bits are rol SP SP RI registers to shift the for two lower-order physical address bits. physical for two lower-order register is a read/write register co a read/write register register is memory, such as an entry in the page memory, (and subsequent optional releases), support for 1 kB pages was added for Config3 are used when a TLB access does not obey the TLB used when a are EntryLo1 eases of the Architecture eases of the Context register to enable writes to, and use of, bits 12..11 ( to enablewritesregister to, and use of, bits 12..11 e minimumas with optionalsize was 4 kB, page pages supportfor as large III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: and register to enable writes to, and use of, bits 12..11 ( bits 12..11 of, use and to, enable writes to register register. This register is also used by register. odd virtual page pair. The virtual page pair. odd is feature, each of the EntryHi PageMask EntryLo0 , allow more types of protection to be used for virtual pages, including write-only pages and PageGrain (Execute Inhibit) used by Release 2 of the Architecture and those used those Architecture and used by Release 2 of the page support is enabled, to create space is enabled,page support XI 1 and 2, this pointerdefined was to referencea fixed-sized ing an entry for each even/ • Modification of the trary power-of-two aligneddatastructure in trary power-of-two erally. erally. • Modification of the non-executable pages. This feature originatedSmartMIPS in thebeen ASE but has the Release 3 version of th and In Release In Release 3 of the Architecture, the conjunction with a default page size of 4 kB and is not inte is not default page size of 4 kB and conjunction with a In Release 3 of the Architecture, two optional cont 256Architecture the 2 of Release MB. In In Release In Release 1 of the Architecture, th require access to pages smal access to that require use in specific embedded applications sion of this feature, new exception codes of this feature, new exception codes sion • Modification of the rather, toaugment it. rather, Support for 1 kB pages involves thefollowing changes: • Additionthe of Support for 1 kB pages is denoted by the 4.1.3 Context Register 4.1.2 Pages of Virtual 4.1.1 Memory Virtual MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 4.1 between Rel Differences Virtual Memory Virtual Chapter 4 Chapter

. is a configuration igurations. Six Seg- Figure 4.1 bytes. The format of the 32-bit Address Space in Space Address 32-bit 36 . As such,if 36 physical = 2 and 0 fields to calculate the value the to calculate fields and 0 bytes. Software can determine the determine Software can bytes. PAB IT S PABITS ged Resource Architecture, Rev. 6.02 36 (EVA) feature. EVA feature. EVA (EVA) PFN lowing direct access to user-mode memory to user-mode lowing direct access the Release version of 3 the base architec- fied by Segment Conf set of memory regions specified by Segment of memory regions specified set med to define two address ranges, a three-GB two address define med to five segments, as shown in as shown five segments, registers, then reading the value back. Bits read as hing a virtual address to the region specified in a in Seg- specified region the to address a virtual hing -kernel access modes, and a one-GB address range with range one-GB address and a modes, access -kernel re instructions al EntryLo1 or e physical address to 2 size EntryLo0 ess Space that has self-consistent reference and access behavior. Segments ess Space that has self-consistent reference and access behavior. of the physical address space would be 2 of the physical address space would be entation Control is program is entation Control optional Enhanced Virtual Addressing optional Enhanced Virtual y mapping the virtual address space. space. address y mapping the virtual address space is divided into divided is address space set of kernel mode load/sto kernel mode set of and attributes of each region are also speci also region are and attributes of each e virtual address space is definable as the definable as space is virtual address e ure includes an optional programmable segmentation feature. This improves the flexibil- e SmartMIPS ASE. Thisoptionale feature is in registers implicitly limits th bytes in size, depending bytes insize, onthe specific Segment. is the range of all possible addresses that can be generated. There is one that can be of all possible addresses the range is 31 field allow software to determine the boundary between the EntryLo1 or 2 or PFN 29 is a defined subset of an Addr subset defined is a and Address Space Address Segment are either 2 ture. range with mapped-user, mapped-supervisor, and unmapped mapped-supervisor, range with mapped-user, mode. mapped-kernel access bits were implemented, the size address The MIPS32/microMIPS32 virtual The numberphysicaladdressThe of bits implemented isrepresented by the symbol EntryLo0 A An ment Configuration. Thus, th ment Configuration. In Release 3 of the Architecture has an In Release 3 of the Architect space. virtual address of the MIPS ity SegmentationControl, address translationbegins by matc With behavior The Configurations. This feature originated in th This feature value of PABITS by writing all ones to the by writingto ones all ofvalue PABITS “1” from the of PABITS. of Segmentation Control and a Segmentation of Segm In EVA, mode. from kernel space the MIPS32 Architecture. ment Configurations are defined, full ment Configurations 4.2.3 Physical Address (PABITS) Size 4.2.1 Address Space 4.2.2 Segment Size and Segment 4.1.5 Addressing Enhanced Virtual 4.1.4 Control Segmentation 26microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers 4.3 Address Spaces Virtual 4.2 Terminology Virtual Memory Virtual

cal address zero, and with a 4.3 Virtual AddressSpaces . A “Mapped” address is translated “Mapped” address A . ed Resource Architecture, Rev. 6.02Architecture, ed Resource 27 to this Segment bypass all levels of the cache hierarchy User Mapped Kernel Mapped nmapped”is not address translated through the TLBand Kernel Unmapped Supervisor Mapped Kernel Unmapped Uncached assified as “Mapped” or “Unmapped” “Mapped” or assified as thout interference from the caches. caches. the thout interference from useg ksseg kseg3 kseg1 kseg0 Figure 4.1Figure Space Address Virtual III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: st portion of the physical address at physi space, starting st 0xE000 0000 0xDFFF FFFF 0x8000 0000 0x7FFF FFFF 0xC000 0000 0xBFFF FFFF 0xA000 0000 0x9FFF FFFF 0xFFFF FFFF 0x0000 0000 ze of the unmapped Segment. ze

through the TLBor other address translation“U An unit. provides a window into the lowe Each Segment of an Address Space is cl size corresponding to the size corresponding si The kseg1 Segment is classified as “Uncached”. References to memory wi and allow direct access MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

one of the of one ciated with ciated with bytes bytes bytes bytes bytes Size 29 29 29 29 31 t is referenced. For exam- Actual 2 2 2 2 2 Segment ated with a mode is accessible if the is accessible mode with a ated ged Resource Architecture, Rev. 6.02 Segment is not accessible if the proces- accessible Segment is not Kernel Kernel Mode(s) ent. For example, a Segment associated a Segment associated ent. For example, Supervisor Reference Legal from Legal an Address Space an Address is asso User User Kernel Kernel Kernel Kernel Kernel Kernel ssor is operating in each of the operating modes. the operating operating in each of is ssor e mode from which the Segmen is running in User Mode, and such a reference results in er mode, while the Segment name “kuseg” denotes a refer- er mode, while the Segment name “kuseg” r example, a Segment associated with User Mode is acces- is with User Mode associated a Segment r example, Supervisor Supervisor with Mode Associated r form. Each r form. Each of Segment upervisor, or Kernel). A Segment associ A or Kernel). upervisor, through through through through through 0x8000 0000 0x8000 0xFFFF FFFF 0xFFFF 0000 0xE000 0xBFFF FFFF 0xBFFF 0000 0xA000 FFFF 0x9FFF 0x7FFF FFFF 0x7FFF 0000 0x0000 0xDFFF FFFF 0xDFFF 0000 0xC000 ode than that associated with the Segm with the that associated ode than Table 4.1Table Spaces Address Memory Virtual suseg ksseg kuseg Name(s) Range Address Segment 31..29 shows the Address Space as seen when the proce seen when the Space as the Address shows 0b111 kseg3 0b110 sseg 0b101 kseg1 0b100 kseg0 0b0xx useg lists the same tabula information in lists the same VA processor processor is running in that or a more privileged mode. Fo sible when the processor is running in User, Supervisor, or Kernel Modes. A or Kernel Modes. Supervisor, User, in is running when the processor sible three processor operating modes (User, S three processor operating modes (User, sor is running in a less privilegedm ence Legal from Mode(s)” column in Table 4-2 lists the modes 4-2 lists from which an Address Error Exception. The “Reference Legal from Mode(s)” columnin Table be referenced legally. can each Segment If a Segment has more than one name, each name denotes th with Supervisor Modeis not accessible processor when the ple, the Segment name “useg” denotes a reference from us ence to the same Segment from kernel mode. kernel from ence to the same Segment Figure 4.2 Table 4.1 28microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Virtual Memory Virtual

4.4 Compliance Uncached User Mapped Kernel Mapped Kernel Kernel Unmapped Kernel Unmapped Supervisor Mapped Supervisor Kernel Mode References Mode Kernel ksseg kuseg kseg3 kseg1 kseg0 ion also must implement the kseg3 implement ion also must 0xFFFF FFFF 0000 0xE000 0xDFFF FFFF 0000 0xC000 0xBFFF FFFF 0x8000 0000 0x8000 0000 0x0000 0xA000 0000 0x9FFF FFFF 0x7FFF FFFF ed Resource Architecture, Rev. 6.02Architecture, ed Resource 29 References User Mapped Address Error Address Error Supervisor Mapped Supervisor sor using TLB-based address translat sseg Supervisor Mode Supervisor suseg 0xC000 0000 0xC000 0xFFFF FFFF 0xFFFF 0000 0xE000 FFFF 0xDFFF FFFF 0xBFFF 0x8000 0000 0x8000 0000 0x0000 0x7FFF FFFF 0x7FFF III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Figure Figure 4.3 Mode Operating of a Function as References Figure 4.2Figure Mode Operating of as a Function References User Mapped Address Error Address User Mode References User Mode useg Segment. A MIPS32/microMIPS32 compliant processor must implementfollowing the Segments: • useg/kuseg •kseg0 •kseg1 A MIPS32/microMIPS32-compliant proces 0xFFFF FFFF 0xFFFF 0x8000 0000 0x8000 FFFF 0x7FFF 0000 0x0000 MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 4.4 Compliance

=1 = 1. = =0. . . . rency attribute of DM ERL ERL for special for d coherency attribute for d coherency bytes of physicalmemory; ace as a function the of pro- Section 4.7 Section 4.6 Section 4.6 29 See See See See See Section 4.8 Mapped if Status ged Resource Architecture, Rev. 6.02 See See behavior when Debug behavior cacheability and cohe and cacheability register. The cacheability an register. Mode Kernel Mode Supervisor y and Coherency Attributes for the Config Action whenAction Referenced from Operating Mode Mapped Mapped if Status Unmapped User Mode User Address Error Mapped Mapped or other address translation unit. The unit. translation address other or behavior is listed for each reference. each reference. listed for is behavior and other special TLB Refill vector ection of sseg useg suseg ksseg kseg3 Error Address Error Address Mapped kuseg kseg0 Error Address Error Address Unmapped kseg1 Error Address Error Address Uncached Unmapped, Name(s) Segment Table 4.2Table Mode of Operating as a Function Access Space Address through through through through through lists the action taken by the processor for each section of the 32-bit Address Sp Address the 32-bit of section for each the processor by taken lists the action 0xDFFF FFFF 0xDFFF 0000 0xC000 0xFFFF FFFF 0xFFFF 0000 0xE000 0x9FFF FFFF 0x9FFF 0000 0x8000 FFFF 0x7FFF 0000 0x0000 0xBFFF FFFF 0xBFFF 0000 0xA000 Virtual AddressVirtual Range The kseg0 and kseg1 Unmapped Segments provide a window into the least significant 2 Table 4.2 cessor’s operating mode. The sel operating mode. cessor’s these are not translated using the TLB using translated these are not the kseg0 Segment is supplied by the K0field of the CP0 30microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers 4.6 and Cacheabilit Translation Address kseg0 and kseg1 Segments 4.5 Mode and Operating of Address a Function Control as Access Virtual Memory Virtual

= 1 ERL

0000 0xFF20 = 1 0xFF20 0000 ERL Register. = 1 Uncached done, as well of as the source as done, DM From K0 field of Config From K0 field TAG specification for details onthis TAG e error exception code to operate e error exception uncached Segment, similar to the to similar Segment, uncached ed Resource Architecture, Rev. 6.02Architecture, ed Resource 31 anslation” on page descriptions of alterna- 317 for through through 1 Address Cache Attribute ation mechanism. Sufficient TLB entries must be imple- TLB entries mustation mechanism. Sufficient 0x0000 0000 0x0000 0000 0x0000 0x1FFF FFFF 0x1FFF FFFF 0x1FFF GeneratesPhysical and not assume that the entire region between mory-mapped region in Debug Mode. A MIPS32/microMIPS32 describes howthistransformation is register. This allows the cach This register. EJTAG blocktreat must the virtual address range EJTAG 4.7 Status when Segment kuseg the for Translation Address Status e kuseg Segment when Status e kuseg Segment when les can apply in some cases. See the EJ Table 4.3 op on load and store instructions.loadop on and store e kseg3 Segment when Debug e kseg3 Segment when III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: through through also implements EJTAG must: also implements EJTAG 0x9FFF FFFF 0x9FFF 0000 0x8000 0xBFFF FFFF 0xBFFF 0000 0xA000 bit is set intheset bit is is included in the special memory-mapped region. memory-mapped the special in is included , inclusive, as a special me special a , inclusive, as ERL 0xFFFF FFFF 0xFF3F FFFF 0xFF3F kseg0 kseg1 and A.1 page MMU” on “Fixed Mapping A.2 313 and Address Tr “Block Segment Name Address Virtual Range tive MMU organizations. uncached using GPR R0 as a base register to save other GPRs before use. to save other GPRs before register a base GPR R0 as using uncached This sectiondescribes the TLB-based virtual address transl lo mented to avoid a TLB exception If EJTAG is implemented on the processor, the is implemented on the processor, If EJTAG To support the cache error handler, the Segment an unmapped, the kuseg becomes support the cache error handler, To that compliant implementation •range as given, the address explicitly range-check the cacheability and coherency attributes and coherency the cacheability Segment. for each if the kseg1 Segment, the kseg1 Segment is always Uncached. Uncached. always is Segment the kseg1 through •Debug mode. mappingthis region for onlyEJTAG in specialthe enable EJTAG Even in Debug mode, normal memory ru mapping. 1. See Table 4.3Table Segments kseg1 and Cacheability Address kseg0 the for Translation, Attributes and Coherency 4.9 Address Translation Virtual TLB-Based 4.8 for th Behavior Special 4.7 for th Translation Address MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

. EntryLo1 Table 9.12 , and e ASID comparison e ASID V1 V0 EntryLo0 D1 D0 , cludes thevirtual page l page number/2 since each each page number/2 since l XI0 XI1 ASID EntryHi , RI0 RI1 TLB entry maps pair aligned an of . Similarly, odd page entries come . Similarly, ged Resource Architecture, Rev. 6.02 which over-rides whichth over-rides C0 C1 ach entry contains two logical compo- two ach entry contains G e 1 of the Architecture. the e 1 of PageMask EntryLo0 TLB to enable more secure access of memory of secure access enable more TLBto

ation section contains a pair of entries, each of each of entries, a pair contains ation section Maskx VPN2X ASIDs to each process, and the TLB keeps track of keeps the TLB and each process, ASIDs to The comparison section in section The comparison tensions to the right that are required to support 1 kB rrespondstheoddand pair. to the even pages of , VPNX, which is the virtua , e G(lobal) bit, a recommended and maskthatfield allows Mask eld (C) for which the valid encodings are given in encodings are given the valid eld (C) for which the fields in the CP0 implementation of Releas implementation e entry. The physical transl e entry. ical translation section. ical translation section. operating system operating assigns this, the TLB includes a global (G) bit includes this, the TLB n section for each TLB entry because each because entry for each TLB n section PFN0 PFN1 VPN2 cal translation entries cal translation entries co the TLB (such as PFN0) come from as PFN0) come the TLB (such Figure 4.4Figure a TLB Entry of Contents ure, the RI and XI bits were added to the bits were added XI the RI and ure, try correspond exactly to try . Optional Release 3 features added for additional security. additional for added 3 features Release Optional addresses. physical to larger 2 required suport Optional Release features Optional Release 2 features to support 1 kB pages. Release 2 features required Optional R shows the logical arrangement of a TLB entry, includingoptional the supportadded2 of the in Release theshows logical a TLB arrangemententry, of PFNX PFNX EntryLo1 mapping different page sizes with a singl page sizes different mapping number (VPN2 and, in Release 2 and subsequent releases (VPN2 and, in Release 2 and number ththe ASID, entry maps twopages)the physical entry, of which contains the physicalnumber page framevalid a dirty(V) bit,(PFN), a (D) bit, optionally read-inhibitexe- and fi cache coherency and a bits, & XI) cute-inhibit (RI There are two entries in the translatio The fields of the TLB en virtual pages, and the pair of physi In Revision 3 of the architect no-execute and access write-only, pages. These bits (along with the Dirty bit) allow the implementation of read-only, policies for mapped pages. Figure 4.4 denote ex fields Light grey Architecture for 1 kB page sizes. page sizes. This extensionpresent is notan in registers. The even page entries in from each ASID during address translation. In certain circumstances, the operating system may want to associate the same may want to associate system certain circumstances, the operating translation. In each ASID during address addressvirtualall with processes; for during translation. E fully-associative structure for translating virtual addresses. TLB is a The nents:a comparison section, and a phys The TLB-based translation mechanism supports mechanism translation TLB-based The Address Space Identifiers to uniquely identify the same virtual The processes. different across address 4.9.2 Organization TLB 4.9.1 (ASID) Identifiers Address Space 32microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Virtual Memory Virtual

. =0x0 IE Config4 must beable must to handle ocess. In processors that ocess. In processors other implementations. The inates, the possibility of the exception. the inates, Architecture that report multiple TLB port multipleoneither matches TLB a lease 1 of the Architecture. the 1 of lease ed Resource Architecture, Rev. 6.02Architecture, ed Resource 33 4.9 TLB-Based Virtual Address Translation the TLB during the power-up pr power-up the during TLB the ty such an of exception on ssor implementations limited are to reporting multiple TLB most implementationsmost of Re ) or a TLB read (TLB access or TLBR or TLBP instructions). In Release Release or TLBP instructions). In or TLBR (TLB access ) or a TLB read Binitialization routine that, on implementations2(and subse- of Release tion algorithm that minimizes, elim or minimizes, that algorithm tion inatesthe possibility reporting of a machine check during TLB initialization. on of implementations 1 of Release the cessor implementations can detect and re implementations can cessor III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: va += Page_Size; va += mtc0mtc0 C0_EntryLo0 zero, C0_EntryLo1 zero, */ valid bits PFN and out /* Clear * InitTLB * all entries that state, guaranteeing to a power-up the TLB Initialize * and invalid. are unique * * * Arguments: ** * Returns: a0** =* Restrictions: No value of C0_Config1) field MMUSize index (from TLB Maximum ** * Algorithm: space in unmapped called must be routine This *** va = kseg0_base; * { 0, entry--) entry >= max_TLB_index; (entry = for { (TLB_Probe_Hit(va)) while PFN values are off, bits that valid so and EntryLo1 EntryLo0 Clear PageMask, * is used. page size default and the are zero, * */ *} **} * * Notes: 0, 0, 0); va, TLB_Write(entry, *** -* appropriate to the expand code below in the used Hazard macros The * the 1 of of Release an implementation in of SSNOPs number */ of 2 of Release in an implementation an ehb and to Architecture, 105 for on page Hazards,” , “CP0 See Architecture. the information. additional more /* InitTLB: /* 2 (and subsequent releases) of theArchitecture, proce write;of onlymatchesa TLB true on this is also TLB write (TLBWI or TLBWR instructions TLBWR (TLBWI or TLB write The following code example shows a TL of the Architecture, elim quent releases) equivalent effect an This example has exceptions only minimizes on a TLB write and the probabili followingexampleisdonot for processors that implementTLB invalidate instructions, that is: In Release In Release 1 of the Architecture, pro In many processor implementations, software must initialize detect multipledetect TLB matches, and signal assumption, this throughsoftware machine-check a such an exception or initializa use a TLB 4.9.3Initialization TLB MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

=1), =1), SC Config3 register. If this bit is is bit this If register. he VPN2 field) of the TLB the TLB of field) he VPN2 ged Resource Architecture, Rev. 6.02 esses to be writtenVPN2 to the field of the TLB entry ented. Instead, use the TLB ented. Instead, feature. The TLB invalidate ble Entry held in the TLB entry is valid. This Valid bit theble Entry heldin TLB entry This is valid. Valid whether the virtual address (t whether the virtual tion Control is implemented and is required for FTLB/ ny unmapped address regions. For thisreason, theabove /* Clear out mask register * mask register out /* Clear */ == 0x8000.0000 /* A_K0BASE */ candidate VA /* Write */ R1/2) in (ssnop/ehb hazard EntryHi /* Clear */ a match for check TLB to the /* Probe */ in R1/2) (ssnop/ehb hazard Index /* Clear */ match check for flag to back /* Read */ an entry duplicate about to if /* Branch */ index as next TLB this /* Use */ in R1/2) (ssnop/ehb hazard Index /* Clear */ TLB entry the /* Write to do */ entries more TLB if /* Branch index the TLB /* Decrement caller */ to /* Return esses. When esses. Segmentation Control is implemented ( visible throughthe EntryHi the EHINV field of field is marked as invalid, the entry is ignoredmatchinvalid, fieldthe on address for entry is is marked as VPN2 ), there are three ways to initialize a TLB entry: the TLBINV, TLBINVF, and TLBINVF, there are three), ways to initializeTLB entry: the TLBINV, a IE entry has been initialized. Config4 mtc0 C0_EntryHi t0, mtc0 C0_PageMask zero, TLBP_Write_Hazard() tlbp TLBP_Read_Hazard() mfc0bgez C0_Index t1, addiu 10b t1, (1<

ed Resource Architecture, Rev. 6.02Architecture, ed Resource 35 4.9 TLB-Based Virtual Address Translation /* Clear out PFN and valid bits */ valid bits PFN and out /* Clear */ mask register out /* Clear field */ VPN2 bit, Clear EHINV /* Set */ index as next TLB this /* Use */ in R1/2) (ssnop/ehb hazard Index /* Clear */ TLB entry the /* Write to do */ entries more TLB if /* Branch index the TLB /* Decrement caller */ to /* Return bit set. EHINV EntryHi III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: implementinvalidate TLB the instructions, to code initializethe TLB is much simpler: entry with entry with the mtc0mtc0 C0_EntryLo0 zero, mtc0 C0_EntryLo1 zero, ori C0_PageMask zero, mtc0 zero, 0x400 t0, C0_EntryHi t0, mtc0TLBW_Write_Hazard() C0_Index a0, tlbwi bneaddiu zero, 10b a0, -1 a0, mtc0mtc0 C0_Index zero, jr C0_EntryHi zero, nop ra * Clear PageMask, EntryLo0 and EntryLo1 so that valid bits are off, PFN values are off, bits that valid so and EntryLo1 EntryLo0 Clear PageMask, * is used. page size default and the are zero, * */ for all constant state leave the to simply and EntryHi Clear Index * * returns */ * InitTLB * entries all that guaranteeing state, to a power-up the TLB Initialize * and invalid. unique are * * * Arguments: ** * Returns: a0** =* Restrictions: No value of C0_Config1) field MMUSize index (from TLB Maximum ** Algorithm: * space in unmapped called be must routine This * * Notes: with EntryHi.EHINV=1 entry Each TLB Write *** -* appropriate to the expand code below in the used Hazard macros The * the 1 of of Release an implementation in of SSNOPs number */ of 2 of Release in an implementation an ehb and to Architecture, 105 for on page Hazards,” , “CP0 See Architecture. the information. additional more InitTLB: /* 10: /* /* For Release 3 processors that 3 processors that For Release each TLB write just MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

). This SP stored within the register at the time Config3 the final physical address eld in the TLB entry, or the eld in theTLB entry, d the reference was a store, a itecture thatitecture includes 1 kB PageMask form the virtual page form the virtual page ion fetch, a TLB invalid (or C, V, and D bits (and optionally RI C, V, its that are in the set Mask fields. offield the VPN2 ds in each entry by ignoring each bit in each entry ds quent releases) implementa- quent releases) implementa- ged Resource Architecture, Rev. 6.02 ent process ASID are presented to the are ASID ent process Comment try and no dirtyand exception, the PFN s s a load, a TLB Invalid (or TLBRI) excep- of the two PFN entries is read is a function register is register is not implemented, the TLB operation is bits of the address to form s. For clarity in the discussion below, take the follow- clarityFor in the discussions. below, ed. If the dirty an bit is off tions that 1 support kB pages the concatenate fields to VPN2 and VPN2X number for a 1 kB page. kB a 1 for number tions that 1 support kB pages the concatenate care Mask and fields to form the MaskX don’t mask for 1 kB pages. register) matches the register) matches ASID fi equent releases) of the Arch of the releases) equent PageMask nd the reference was an instruct was reference nd the EntryHi separated intosets of pseudo two code: fferent page size, as page size, as determined by the fferent its is determined by the Mask fiel ght of the section masked with the Mask entry. masked with the ght of the section  MaskX 2 (and subse Release itten with the encoding for a 4 kB page. kB 4 for a the encoding itten with VPN2 field corresponding to those b ID presented, the corresponding PFN, lease 1 of the Architecture, or an implementation of Release 2 (and subse- Release of implementation Architecture, or an lease 1 of the ge number match the corresponding bits Mask VPN2  VPN2X (and subse Release 2 ed, the virtualtheand curr page number multaneously formatch, a which occurs when all of thefollowing conditions are true: e translation section of the TLB entry. Which of the e translation section TLB entry. Mask VPN2 Term Used BelowTerm Release 2 Substitution This lets each entry each entry This lets of the TLB support a di in the virtualin the page number and the TLB TLB entry. The “appropriate” number of b “appropriate” number of The TLB entry. G bit is set in the TLB entry. set in theis G bit that the TLB entry was written. If the recommended instanceis called the “4 kB TLB Lookup”. page support. calledis This instance the “1 kB TLB Lookup”. as if the PageMask register had been wr register if the PageMask as quent releases) of thequent Architecture of not releases) does that includedenoted 1 kB page supportby(as • Theof appropriate bitsvirtual the pa 2.an implementation One used by subs of Release 2 (and TLB. All entries are checked si are checked entries TLB. All • The current process ASID (as obtained from the When an address translation is is request When an address translation ing terms in the ing terms the new general sense to include 2 features: Release Release 2 of the Architecture introducedof the Architecture Release 2 support for 1 kB page The valid and dirty bits (and optionally RI and XI bits) determine the final success of the translation. If the valid bit is the entryoff, is not valid, and a TLB Invalid exception is rais If a TLB entry matches the address If a TLB entry matches the address and AS th from read are and XI bits) of the virtual address bit immediately to the ri 1.an implementation One used by of Re TLB Modified exception is raised. If there match is an address with a valid en TLB exception is raised. If there Modified offset-within-page the appended to are the cache coherency bits with attributes.wa If and the reference the RI bit set, is and is implemented tionraised. If theXIis bit implemented is andset, a is TLBXI) exception is raised. thelookup TLB processes have been For clarity, 4.9.4 Address Translation 36microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Virtual Memory Virtual

))) and Mask ed Resource Architecture, Rev. 6.02Architecture, ed Resource 37 and not (TLB[i] and 4.9 TLB-Based Virtual Address Translation 31..13 )) then ASID )) = (va )) ) then ) then ) SM SM Mask ) then ) = 0) = 0) SM IEC = EntryHi = ASID RI0 XI0 RI1 XI1 or Config3 or Config3 UNDEFINED PFN1 PFN0 III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: RXI RXI V1 C1 D1 V0 C0 D0 or Config3 SignalException(TLBInvalid, reftype) SignalException(TLBInvalid, reftype) SignalException(TLBRI, = 0 then = 0 TLB[i] TLB[i] TLB[i] TLB[i] RXI Mask and not (TLB[i] and # PC relative loads are allowed where execute is allowed execute where allowed are loads relative # PC if (PageGrain else endif VPN2 or (TLB[i] ri  ri  and (IsPCRelativeLoad(PC)) = 0) if (xi else xi  xi  endif G EvenOddBit if (ri = 1) and (reftype = load) then = load) and (reftype (ri = 1) if endif  TLB[i] pfn v  TLB[i] c  TLB[i] d  TLB[i] if (Config3 endif reftype) SignalException(TLBInvalid, v  TLB[i] c  TLB[i] d  TLB[i] if (Config3 12 /* 4KB page */ /* 4KB 12  EvenOddBit 0000 0000: 0000 0b0000 */ page /* 16KB 14  EvenOddBit 0000 0011: 0000 0b0000 */ page /* 64KB 16  EvenOddBit 0000 11xx: 0000 0b0000 */ page /* 256KB 18  EvenOddBit 0011 xxxx: 0000 0b0000 page */ 20 /* 1MB  EvenOddBit 11xx xxxx: 0000 0b0000 page */ 22 /* 4MB  EvenOddBit xxxx xxxx: 0011 0b0000 */ page 24 /* 16MB  EvenOddBit xxxx xxxx: 11xx 0b0000 */ page 26 /* 64MB  EvenOddBit xxxx xxxx: xxxx 0b0011 */ page 28 /* 256MB  EvenOddBit xxxx xxxx: xxxx 0b11xx otherwise: endif pfn  TLB[i] pfn else endif v = 0 then if endif if (Config3 endcase if va # EvenOddBit selects between even and odd halves of the TLB as a function of a function the TLB as of halves odd even and between selects # EvenOddBit need sizes all page Not entry. TLB matching in the page size # the to ‘x’ uses an below case so the all processors, on implemented # be would select implementation actual cases. The don’t-care # denote sizes the page with compatible that is a way bit in even-odd # the implemented. # actually TLB[i] case (TLB[i] if ((TLB[i] found  0 found i in 0...TLBEntries-1 for The 4 kB TLB Lookup pseudo code is: MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

))) and Mask ged Resource Architecture, Rev. 6.02 and not (TLB[i] and 31..13 EvenOddBit-1..0 )) then PABITS-1..12 ASID )) = (va )) || va ) then ) SM Mask = 0) = 0) = EntryHi = IEC ASID RI0 XI0 or Config3 UNDEFINED corresponds to pa to corresponds PFN0 PFN1 RXI V0 C0 D0 V1 = 0 then = 0 TLB[i] TLB[i] Mask and not (TLB[i] and PageGrain SignalException(TLBInvalid, reftype) SignalException(TLBInvalid, reftype) SignalException(TLBXI, -1-12..EvenOddBit-12 PABITS VPN2 or (TLB[i] ri  xi  if ( else endif G EvenOddBit PABITS-1-12..0 pfn v  TLB[i] c  TLB[i] d  TLB[i] if (Config3 endif  TLB[i] pfn v  TLB[i] 10 /* 1KB page */ 1KB page  10 /* 00: EvenOddBit 0000 0000 0000 0b0000 */ 4KB page  12 /* 11: EvenOddBit 0000 0000 0000 0b0000 */ 16KB page  14 /* xx: EvenOddBit 0000 0011 0000 0b0000 */ 64KB page  16 /* xx: EvenOddBit 0000 11xx 0000 0b0000 */ 256KB page  18 /* xx: EvenOddBit 0011 xxxx 0000 0b0000 */ 1MB page  20 /* xx: EvenOddBit 11xx xxxx 0000 0b0000 */ 4MB page  22 /* xx: EvenOddBit xxxx xxxx 0011 0b0000 */ 16MB page  24 /* xx: EvenOddBit xxxx xxxx 11xx 0b0000 */ 64MB page  26 /* xx: EvenOddBit xxxx xxxx xxxx 0b0011 */ 256MB page  28 /* xx: EvenOddBit xxxx xxxx xxxx 0b11xx otherwise: if (xi = 1) and (reftype = fetch) then = fetch) and (reftype (xi = 1) if pfn  TLB[i] pfn endif SignalException(TLBModified) else endcase if va pa   1 found break # EvenOddBit selects between even and odd halves of the TLB as a function of a function as the TLB of odd halves even and between selects # EvenOddBit need sizes all pages entry. Not TLB matching in the page size # the ‘x’ to uses an below so the case all processors, on implemented # be would select implementation actual cases. The don’t-care # denote sizes the page with compatible that is a way bit in even-odd # the implemented. # actually TLB[i] case endif then = store) (reftype (d = 0) and if endif # pfn (TLB[i] if ((TLB[i] endif reftype) SignalException(TLBMiss, found  0 found i in 0...TLBEntries-1 for endfor if found = 0 then endif The 1 kB TLB Lookup pseudo code is: 38microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Virtual Memory Virtual

or Gener- EntryLo0 (PABITS-1)..0 e page size of the TLB entry that entry of the TLB e page size ected PFN and the offset-in-page bits bits theected PFNand offset-in-page or Release 2 (and sub- 2 (and Release or entation without support without entation ed Resource Architecture, Rev. 6.02Architecture, ed Resource 39 indicates which virtual address bit is used to 4.9 TLB-Based Virtual Address Translation Comment EvenOddBit-1..0 PABITS-1..10 Release 1 implementation, Release 1 sequent releases) implem for 1 kB pages || va ) then ) SM ) then ) = 0) = 0) SM ess is generated as a function of tha function of ess is generated as IEC -1 12 = 0) = 0) cal address is generated from the sel generated is cal address IEC PABITS RI1 XI1 PA or Config3 corresponds to pa to corresponds III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: RXI C1 D1 or Config3 SignalException(TLBInvalid, reftype) SignalException(TLBInvalid, reftype) SignalException(TLBRI, e “Even/Odd Select” column of Table 4.4 e “Even/Odd TLB[i] TLB[i] RXI # PC relative loads are allowed where execute is allowed execute where are allowed loads relative # PC if (PageGrain SignalException(TLBInvalid, reftype) SignalException(TLBInvalid, reftype) SignalException(TLBXI, else endif -1-10..EvenOddBit-10 PABITS -1)-12 0 ri  and (IsPCRelativeLoad(PC)) = 0) if (xi else xi  else endif endif if (PageGrain PABITS-1-10..0 pfn if (ri = 1) and (reftype = load) then = load) and (reftype (ri = 1) if if (Config3 endif reftype) SignalException(TLBInvalid, d  TLB[i] endif SignalException(TLBModified) endif then = fetch) and (reftype (xi = 1) if c  TLB[i] (PA B I T S PFN Range Range PA pa   1 found break endif v = 0 then if endif if (Config3 endif then = store) (reftype (d = 0) and if endif # pfn PFN demonstrates how demonstrates the physical addr endif reftype) SignalException(TLBMiss, registers, has one of two and ranges: bit endfor if found = 0 then endif EntryLo1 Table 4.4 matches the virtual address. Th The “PA select betweenthe even (EntryLo0) odd (EntryLo1) or matching entrythe inentry. TLB ated From” columns specify how the physi how the ated From” columns specify virtualin the column, address. In thisthe physical PFN is page number as loaded into the TLB from the MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

 21 0 23 0 25 0 27 0 9 0 11 0 13 0 15 0 17 0 es of segments are segments of es  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA

ble controls for these -1)-10 0 -1)-10 2 -1)-10 4 -1)-10 6 -1)-10 8 -1)-10 10 -1)-10 12 -1)-10 14 -1)-10 16 -1)-10 18 (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS at address space, or used to alter the or used to alter space, at address ged Resource Architecture, Rev. 6.02 fied by Segment Configurations. Six Segment Configurations. fied by PFN PFN PFN PFN PFN PFN PFN PFN PFN PFN Release 2 (and subsequent) e set of by memory regions specified Seg- with 1 kB PageSupport Enabled Comment Generated From: Generated tributes with programma tributes -1)..0 21 0 23 0 25 0 27 0 hing a virtual address to the region specified in a in Seg- specified region the to address a virtual hing 11 0 19 0 13 0 15 0 17 0 xed while kseg0/1 have their cacheability and mappa-  VA  VA  VA  VA  VA  VA  VA  VA  VA (PABITS

PA e MIPS32 virtual address space. e MIPS32 virtual address releases) implementa- releases) subsequent (and Release 2 enabled pages kB 1 support for with tion -1)-12 0 -1)-12 8 -1)-12 2 -1)-12 4 -1)-12 6 -1)-12 10 -1)-12 12 -1)-12 14 -1)-12 16 subsequent) Not Applicable (Release 1) or(Release 1) (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS -1 10 ws into the physical address space. Disabled (Release 2& used to implement to implement a fully used translated fl virtualin themap MIPS CPUfrom address prevents being a fully virtual- PFN PFN PFN PFN PFN PFN PFN PFN PFN attributes of each region are also speci attributes PABITS 1 kB Page Support Unavailable1 kB Page Support its mappability attribute fi PA Table 4.4Table Generation Address Physical ual address space is therefore definable as th definable as therefore space is ual address defined, fully mapping the virtual address space. virtual address defined, fully mapping the proves the flexibility of th 28 12 14 16 18 20 22 24 26 10 VA VA VA VA VA VA VA VA VA Select and cacheability attribut memory map, the mappability and cacheability 32 virtual address -1)-10 0 Even/Odd Even/Odd (PA B I T S fixed. Segmentation Control at replaces these fixed PFN Range Range PA PFN 1 kB VA 4 kB 1 MB 4 MB 64 kB 16 kB 16 MB 16 MB 64 256 kB 256 MB Page Size ment Configuration. The virt ment Configuration. The attributes. Control The Segmentation system can be ized. Another use of Segmentation Control is to remove the unmapped segments from the virtual address map. Future supportfor CPU virtualization wouldSegmentation require Control. SegmentationControl, address translationbegins by matc With bility attributes bility attributes The existence of the unmapped segments In the traditional MIPS mostly fixed. Foruseghas example, windo uncached and relative size of cached ment Configurations. The behavior and ment Configurations. Segment Configurations are As an optionalAs an alternative memoryfixed to segmentation,programmable a segmentation control feature has been 3. This im to Release added 40microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers 4.10 Control Segmentation Virtual Memory Virtual

for an

4.10 Segmentation Control e. Coprocessor 0 registers 0 registers Coprocessor e. backward compatible with compatible backward MT contains additional control and configu- or under Segmentation Control” ed Resource Architecture, Rev. 6.02Architecture, ed Resource 41 Config Config5 Table 9.28 onfigurations are always activ are always onfigurations =1 Table 9.29 Table ERL registers,andreset the BEVexceptions may use another segment which Section 4.10.1 “Exception Behavi Status SegCtl* n Controln is described below: III: MIPS32® / microMIPS32™ Privileg / MIPS32® III:  SegCtl0.CFG0  SegCtl0.CFG1  SegCtl1.CFG2  SegCtl1.CFG3  SegCtl2.CFG4  SegCtl2.CFG4  SegCtl2.CFG5  SegCtl2.CFG5 contain six Segment Configurations. mapping disabledis n access control modes are specified in modes control n access 7:6:5: CFG 4: CFG 3: CFG 2: CFG 1: CFG 0: CFG CFG CFG Index  vAddr[31:29] Index  vAddr pAddr Index case endcase * vAddr* Address - Virtual pLevel* KERNEL USER, SUPER, level - - Privilege IorD* LorS* or DATA - INSTRUCTION type - Access * or STORE - LOAD type - Access * Outputs mapped is mapped * - segment pAddr* unmapped) when (valid address - physical CCA* * unmapped) when (valid attribute - cache Error Address Exceptions: * */ subroutine SegmentLookup(vAddr, pLevel, IorD, LorS) : LorS) IorD, pLevel, SegmentLookup(vAddr, subroutine /* Inputs Besides the segments controlled by explanationexceptions on how interact with programmable segmentation. On reset, SegmentConfiguration default is implementationspecific. A configuration MIPS32 legacy fixed segmentation is defined by Segment configuratio Operation of MIPS32Segmentatio • Cache attribute when mapping is disabled • uncached when to unmapped, Force •when address Physical If SegmentationIf Control is implemented, the Segment C SegCtl0, SegCtl1, and SegCtl2 is active only in kernel mode. Please read kernel mode. only in is active ration fields. are: of The attributes a Segment Configuration • modes supervisor and kernel, user, from permissions Access • Enable mappingtranslation) (addressthe using MMU specified in MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

ged Resource Architecture, Rev. 6.02 =1) then =1) # uncached # unmapped ERL  TLBLookup(vAddr) CFG.AM   CFG.EU  CFG.PA  CFG.C  C isMapped(AM, pLevel,IorD, LorS) pLevel,IorD, isMapped(AM,  2  0 PA >> 1  PA >> pAddr[35:30]  PA pAddr[35:29] CCA mapped CCA  mapped bit. low order drop the (1GB) segment, a large # in if (Index < 4) then else endif (CCA,pAddr) UK:MK:MSK:MUSK: KERNEL) !=  (pLevel seg_err MUSUK: KERNEL) !=  (pLevel seg_err USER) =  (pLevel seg_err USK:  0 seg_err  0 seg_err UUSK:default:USER) =  (pLevel seg_err  UNDEFINED seg_err  0 seg_err LorS) segmentError(IorD, UK:MK:MSK:MUSK:  0 mapped MUSUK:  1 mapped  1 mapped USK:  1 mapped KERNEL) !=  (pLevel mapped UUSK:  0 mapped  0 mapped AM PA C checkAM(AM,pLevel,IorD,LorS) ERL=1 when region - Error-Unmapped case # Special and (Status (EU = 1) if else endif use unmapped address for # Physical if (mapped = 0) then else endif CCA) pAddr, (mapped, return AM case endcase != 0) then (seg_err if endif AM case EU endsub check mode # Access LorS) IorD, pLevel, checkAM(AM, subroutine endsub LorS) pLevel,IorD, isMapped(AM, subroutine 42microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Virtual Memory Virtual

. =0 BEV 4.3 on page 26 se virtual address. Instead virtual address. se Status 4.10 Segmentation Control implementation-specific. In Section 9.48 “Configuration these terms are used: used: are these terms of the virtual memory system. memory virtual of the ed Resource Architecture, Rev. 6.02Architecture, ed Resource 43 register. See register. Config3 e for the Reset/BEV vector ba for the vector location when the vector location for vector base are considered fixed at virtualfixed address 0xBFC0.0000physical and address . EBase nder Segmentation Control, EFINED they are dealt with by the rest are they gment is DSEG which is part of the EJTAG debug architecture and is only gmentDSEG whichpart is is of the EJTAG . =1 RegisterSelect 2)” 5, III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: gment with these properties: gment with these properties: ProbeEn indicated by the SC field in the the SC field in by indicated fic execution modes. fic execution ECR reftype  LOAD reftype  STORE reftype reftype  FETCH reftype then (LorS = LOAD) if else endif default:  UND mapped endcase mapped return if (IorD = INSTRUCTION) then else endif reftype) SignalException(AddrError, •only active Is speci in endsub LorS) segmentError(IorD, subroutine endsub • managedhardware, by not software programmable. Totally • Intercepts memory requests before Section 9.15Section (CP0 “SegCtl0 the virtual addresses and physical addresses for Reset/BEV Non-Reset Exceptions - exceptions which would use Legacy Memory map - A MIPS32 Virtual/Physical memoryas described system Section by Legacy Memory map - A MIPS32 Virtual/Physical For thissection discussing exceptionu behavior Inthelegacy memory map, the Reset/BEV vector base is 0x1FC0.0000. In contrast, Segmentation Control does not define a fixed valu The presence of this facility is See Overlay Segment - A memory se inactive DebugMode. and A pre-existing example of an overlay se overlay of an A pre-existing example Register3)”Select 3 (CP0 Register 16, Debug modebehavior is retained in dseg. 4.10.1.1 Terminology 4.10.1.2 Control Segmentation under Addresses Base and BEV Vector Reset 4.10.1 Control Exception under Behavior Segmentation MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

=kernel). KSU mappability attri- Status =1 or thin KSEG1, which ensures t for the Reset/BEV vectorReset/BEVt for the are implementation-specific. ERL ged Resource Architecture, Rev. 6.02 Status ly choose much larger sizes for the ly choose much larger ed and unmapped, overlay segments and unmapped, ed the cacheability and =1 or out accessing the caches and TLB during during caches and TLB the out accessing ERL rantee these conditions: rantee these conditions: Status or does not have to be derived from the virtual address EV vector location, it must deal with memory requests for reset and BEV exceptions. set/BEV vector region are wi set/BEV vector ception is taken, the overlay segmentmemorythe handles t at least one overlay segmen t at least one overlay e virtual address space as well as the physical address as the physical well space as virtual address e size of this overlay segment overlay segment size of this ry and potentially other IO devices. IO devices. other ry and potentially if the system can gua system the if as uncached and unmapped for kernel mode. mode. kernel for as uncached and unmapped reset and exceptions whilekernel mode. in cache-ability and mappability attribute. y segment does not have to be derived from the virtual address of the overlay the virtual address from to be derived y segment does not have kB insize. Implementations would like y aligned both in th without reserving one segment as uncach e overlay segment attributes e overlay attributes over-rides segment set/BEV regions to be accessed with regions to be accessed set/BEV uncached and unmapped for kernel mode. and uncached ssible while in kernel-mode ( Cacheability and Map-ability en no special support is needed is support en no special reset and BEV exceptions. That is, when a reset or BEV ex is, That reset and BEV exceptions. that vector region and th for requests location.there is only If segment one overlay for the Reset/B must be naturall overlay segments The as uncached and unmapped. as Segments for Overlay 2 - Requirements Solution startingThe starting virtualaddress, physical address and of the overla space. The physical address otherallowed. mappingsare by droppingVA[31:29], at least 2 be must overlay segment The overlay segment to access non-volatile memo overlay segment to access acce be must overlay segment The Solution 2 - Option A - Two Overlay Segments for KSEG0/1 legacy behavior KSEG0/1 legacy for Segments Overlay A - Two 2 - Option Solution by dropping VA[31:29], otherallowed. mappingsare by droppingVA[31:29], Reset and BEV exceptions - Re to the memory map, the memory accesses legacy the In and unmapped. uncached region are always to this the accesses uncached and is region which a memory to vector exceptions reset and BEV requires that the The architecture unmapped. available always Segment Unmapped and 1 - Uncached Solution can be satisfied This architecture requirement Segmentation Control for are introduced in re allow the segments overlay These butes of the regular segment control register. SolutionnotIf implemented, 1 is CPU mustthe implemen SegmentationphysicaltheControl, address of Reset/BEV vect To meet the architecture requirement the architecture meet To 1.up always powers the segments One of 2.as always kept That segment is 3.alwaysthe in reside above The reset and BEV vectors mentioned segment. If these conditions are met, th and BEV exceptions Reset for Segments 2 - Overlay Solution Not all systems may want to maintain the conditions for Solution 1, since Segmentation Control allows for any of the segments to be programmed with any valid 44microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Virtual Memory Virtual

seg-

CFG3 (virtual

must be reset

CFG3 K0 SEGCTL1 lent to legacy KSEG1 Config cacheability of their SEGCTL1 cacheability attribute from attribute cacheability rammable through the leg- rammable through vector physical address address vector physical 4.10 Segmentation Control =0. If the overlay segment K t would give t would give cached and unmapped the have been initialized. caches Code cached views made available through available through made cached views Config5 fields fields to control ed Resource Architecture, Rev. 6.02Architecture, ed Resource 45 KU must be set by hardware byset must be to uncached CCA (virtual addresses equiva (virtual addresses EG0 segment)overlaythe and other segment register is onlyregister is meant for systems using legacy CFG2 Config fixed by hardware or prog or by hardware fixed is enabled coming out of reset, locationresides mustcome of out mem- reset treating

and Config K0 ddress maps, the recommendation is to disable the legacy the is to disable maps, the recommendation ddress r the overlay segment to get get its to segment overlay r the ay segment for the Reset/BEV for ay segment the cache coherency of the overlay segment would the be em. one After reset, overlay segment would be given K23 K23 SEGCTL1 Config register. If the BEV/Reset vector resides in a overlayvector BEV/Resetinsegment If the resides a register. Config , to the same physical address space. physical address same to the K0 rlap in the virtual address space. Config is modified, code executionshould not be within the of reset. This is whenin effect viors, oneviors, overlay segment would be locatedwithin the addresses which memory accesses as unmapped. as unmapped. memory accesses ectors while the other overlay ectors while segmen K0 Config the boot firmware to be run cached after gments is to mimic the cached and un the cached and mimic to is gments (see next section). next section). (see register field. Config register. ) within the register field, then that register field register field, then that register III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: coherency fields within the the within fields coherency meet these requirements: meet these KU Config , Config Config Config K23 (virtual addresses equivalentlegacyto KS

, K0 CFG3 SEGCTL1 acy register fields in ory accesses as uncached. ory accesses • segment can be of each overlay coherency The cache • must Both overlay segments treat • size. the same segments are of The two overlay • ove segments cannot The two overlay •segments must point The two overlay • The overlay segment in which the BEV/Reset vector KSEG0in segments and KSEG1 memory the legacy syst uncached and uncached unmapped access to these v access vectors. access to the The two overlay segments must addresses which belong to to belong which would be located within the addresses virtual address maps. For systems using non-legacy virtual a coherency fields withinthe resides in one of these segments, it is optionally allowed fo changingthrough writing the value upon reset. The use of these register fields allows should not be executing within the overlay segment while to the uncached CCA value. When When uncached CCA value. to the segment). Fields Register Control Coherency legacy using Segments B - Overly 2 - Option Solution Segmentation Controlallows legacy the For example, if the Reset/BEVoverlay segmentsresides within thesegment controlled by addresses equivalenttoand legacy KSEG0 segment) An implementationmay optionallysecondsupport a overl region. of The purpose two overlay se ment. of these legacy NOTE: This use which controlledis by that belong to To mimic the legacy KSEG0/KSEG1 beha KSEG0/KSEG1 the legacy mimic To the appropriate field ( respective non-legacy segments coming out respective non-legacy segments MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

KU Config =Kernel or and KSU K23 Config Status , K0 these memory requests as ers. For such transitional ers. For such eability attribute of the overlay eability attribute e the BEV vector base address base e the BEV vector =0 and ( Config DM ited from legacy systems, but the vir- legacy systems, but ited from ged Resource Architecture, Rev. 6.02 source of the vector base address is address the vector base of source Debug ector must use uncached and unmapped and unmapped must use uncached ector to more an address for the appropriate non-leg- ess (EffectiveBEV_VA). ess (EffectiveBEV_VA). it=1, is allowed to relocat the overlay deals with segment K e Segmentation Controlregist register field to control the cach

Config5 ors are located at virtual address (EffectiveBEV_VA + 0x200+ off- + ors are located(EffectiveBEV_VA address at virtual Config located at virtual addr located at virtual ed to new non-legacy address map. which the physical address map was inher the non-Reset the non-Reset BEV exceptions vector offsets are unchanged while the vector offsets the following names are used: =1)). EXL lowed for the appropriate Status bit can be used for this purpose. If thisbit purpose. can be used for exceptions. K =1 during other exceptions, the vect =0 and the overlaythe=0 andinresides a segment is controlled thatthe by one of K =1 or BEV ERL Config5 new location. • vector reset/BEV address of the - the virtual EffectiveBEV_VA Status Config5 behavior coming out of reset. Both overlay segments must use unmapped coherency. comingbehaviorBoth of out reset. overlay segmentsunmapped must use coherency. If If implemented,If the second overlaytimesameas the firstsegmentthe BEV/Reset overlayat is active segment. If there are two overlay segments, v the one which contains the reset/BEV register fields, it is al it is register fields, set). Segments 2 - Overlay Option for Requirements there is onlyIf one overlay segment for BEV/Reset, then unmapped and uncached. The overlay segment is active in Kernel mode ( active in Kernel and uncached. The overlay segment is unmapped Status Solution 1 or Solution 2 - Option C - Relocation of non-Reset BEV exception vectors after Reset after vectors BEV exception non-Reset of C - Relocation Solution 2 - 1 or Option Solution in be transitional devices There might for non-reset This feature wouldfashion: be used in this 1.boots Device up usinglocation legacy resetvirtual (e.g. address 0xBFC0.0000) 2. Segmentation are programm Registers changed. For Reset/Soft-Reset/NMI, the reset vector is 3.exceptions Non-Reset BEV would nowuse this movedto new location BEV vector base using this capability. Forof the rest this section, the system, a legacy to As compared If segment. tual addresstualset up by programmingis usedbemap to th devices, it might be useful to relocate relocate to useful be it might devices, map.addressacy virtualcapability Such is allowed by Segmentation Control. The 4.10.1.3 Control Segmentation under BEV Exceptions 46microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Virtual Memory Virtual

=1 and and Figure En K23 Config , register are now also register are now also =1 and ECR K0 l the cacheability attribute 4.10 Segmentation Control Ebase Config ProbeTrap e region. uncached kseg1 ECR =1. A second overlay is segment virtual address is the same as in the in is the same as virtual address DM source of the vector base address is is address base the vector source of comes uncached and unmapped when and unmapped comes uncached the followingadditions. [31:12] || 0x000 + offset). These virtual[31:12] || 0x000 + offset). ese memory requests as uncached. as memory requests ese ed Resource Architecture, Rev. 6.02Architecture, ed Resource 47 Debug Ebase register field to contro field to register

ception vector in th =1 and Config Debug overlay segment, which covers the Virtual address Debug segment, overlay which covers Virtual the to be located anywhere in the address space. See address to be located anywhere in the ProbeEn ecedence over the other overlay segments. overlay other over the ecedence base architecture, with base ent that is controlled by one the of ECR This overlay segment is active when This overlay segment is bit. When EU=1, the segment be segment the bit. When EU=1, system (except system nowtheupper 2 bits of the located at virtual address ( located at virtual address vector offset is unchanged while the vector offset behavior requires thatof bit 29 the exceptionis set truewhen vector th deals with the overlay segment ese memory requests ese memory requests as unmapped. cated at (EffectiveBEV_VA + 0x480). cated at (EffectiveBEV_VA III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: =1 segment is active when is segment En register is present. This places the ex present. This is register ation contains an EU EBase =0 and the overlay resides in a segm K =1 and ECR and =1 =0 =1. This DSEG overlay segment takes pr takes overlay segment =1. This DSEG register fields, it is allowed for the appropriate it is fields, register 5 =0, then exception vectors are then exception =0, register is modified to allow exception vectors modified to allow exception register is DM KU =0 and the =1. On reset, this bit is set for segments covering the range 0x00000000 to 0x7FFFFFFF, tokuseg match segments coveringfor bitreset, this=1. On is set 0x00000000 the range 0x7FFFFFFF, to BEV Config BEV ERL ProbTrap ProbTrap EBase As compared to a legacy system, the system, a legacy As compared to changed. exceptionThe debug lo vector is Segments 2 - Overlay Option for Requirements The sole debugoverlay not allowed for Debug exceptions. th deals with The overlay segment If of the overlay Otherwise, segment. Debug Config The debug exceptionThe debug located vector is at virtual addressThis 0xFF20.0200. legacy system. The memory requests to that region are handled by the region of 0xFF20.0000 to 0xFF3F.FFFF. region of 0xFF20.0000 to 0xFF3F.FFFF. Status ECR ECR If behavior. On a Cache Error exception, the legacy Status Status writable. memoryThe requests to that region handled are appropriatethe by programmable segment. Register) (EBase Placement Vector Exception Extended The addresses addresses are the same as those in the legacy 9.43. the as defined in CacheError Exception operates The Each Segment Configur 4.10.1.4Control Segmentation under Exceptions Debug 4.10.1.5Control Segmentation under Exceptions EBase 4.10.1.6 Control Segmentation under Error Exceptions Cache MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

EBase Section access to user memory access to user memory chitecture provide the ability chitecture provide ken directly fromken directly the ged Resource Architecture, Rev. 6.02 and to access user address space from address space user and to access addressable memory addressable to 2.0GB as ctions allowing direct ctions allowing e exception e exception is ta vector instructions to the MIPS ar mmed to define two address ranges, a 3 GB rangemmedto with defineranges, two address =1) then configuration of Segmentation Control (refer to CV 0x100  2 then  28..12  0x100 ongside SegmentConfiguration EU fieldscode that to ensure from is executed 32-bit virtual address space limited user space limited 32-bit virtual address at exceed prior fixed segmentation limits ignored, resulting PC always in kseg1 */ in kseg1 always PC resulting ignored, EBase the 32-bit virtual address space. the 32-bit virtual address 31..12  =1) and (Config5 =1) and sor and unmapped-kernel access modes and sor and unmapped-kernel access modes a 1 GB address range with mapped-kernel 2 31..29 31..29 ent of a Cache Error exception. ent of a Cache SC EBase 101 . = 1 then 0xA000 0000 + 0x100 0000 + 0xA000 /* Use full value of EBase */ value of Use full /* PC  /* EBase PC  =1 allowsto this behavior be overridden - th BEV CV 0xBFC0 0200 + 0x100 0200 + 0xBFC0 else endif PC  if (Config3 Figure 4.5 else endif PC  if ArchitectureRevision if ArchitectureRevision Config5 if Status endif else kernel mode. feature is a Addressing (EVA) The Enhanced Virtual 4.10 “Segmentation load/store instru of kernel mode Control” ) and a set Segmentation Control is progra kernelfrommode. In EVA, mapped-user, mapped-supervi mapped-user, access mode. access to configure virtual address ranges th ranges to configure virtual address • UnmappedKernel Supervisor, Mapped Mapped 3.0GB User, • Mapped Kernel 1.0GB the legacy fixed segmentation of The EVA is a 2 section partitioning of partitioning a 2 section is EVA shown in The addition of Segmentation Control and kernel load/store Setting register. This feature should be used al This feature register. ev region in the an uncached The exception vector is computed as follows: vector is exception The 4.11.1 Control Configuration Segmentation EVA 48microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers 4.11 Addressing Virtual Enhanced Virtual Memory Virtual

1 1 1 0 1 0 CFG5 EU CFG4 CFG3 CFG2 CFG1 CFG0

r as are programmed o is v l r l e e e mentation Control” on

n n CFG r p r e u e S K K , d r d e e s e p p address access user virtual to p U p a d a e M m 3 3 3 3 3 p 3 p n C

a U ged Resource Architecture, Rev. 6.02

M of each fields EU physical address space by using these space by using physical address and 0.0 GB 2.5 GB 1.0 GB 3.0 GB 2.0 GB 3.5 GB EVA Segmentation Control configuration Control Segmentation EVA 4.0 GB d (CFG (defined in “Seg d (CFG (defined PA, C , om user space can be conveniently changed by replac- by conveniently changed be om user space can itchingbut(kernel to user) is an alternative modesis this e used to allow the kernel allow the e used to AM PA 0x007 0x005 0x004 0x002 0x000 0x006 Segment Configuration fiel AM MK MK MUSUK MUSUK MUSUK MUSUK Address (EVA) Instructions Address (EVA) ontrol to implement EVA, the the EVA, to implement ontrol Table 4.5Table 3GB EVA for Configuration Segment Figure 4.7 Figure configuration address EVA to Legacy kseg1 kseg0 useg ksseg kseg3 Virtual Address Space Address Virtual Legacy 32-bit statically partitioned statically Legacy 32-bit nel Supervisor, Supervisor, Unmapped Kernel Region 0.0 GB 4.0 GB 3.0 GB 3.5 GB 2.5 GB 2.0 GB 01 1GB Mapped Ker- 23 3GB Mapped User, 4 5 page 40)) must be initialized to define the overall memory map to support a unmapped3GB (mapped user/supervisor, kernel) memory segment. C configure Segmentation To follows in the following table. the following in follows EVA defines a number of new load/store instructions that ar instructions of new load/store a number defines EVA normaling load/store instructions withSw these instructions. space while executing in kernel mode executing in kernel while space space to kernel from user address data For example, the kernel can copy fr Kernel system-calls addresses. instructions with user virtual To support the EVA configuration, each EVA the support To CFG Description 4.11.2 Enhanced Virtual 50microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Virtual Memory Virtual

= Kernel, = User StatusKSU ere is penalty a performance COP0 Unusable Excpt COP0 Unusable Excpt register field.

4.11 Enhanced Virtual Addressing EVA mode (defined by ed Resource Architecture, Rev. 6.02Architecture, ed Resource 51 Config5 rown ifinstructionrown the executedother in is than Kernel Supervisor pped) performed by EVA load/store instructions accord- instructions load/store performed by EVA pped) Prefetch EVA Load Byte Load EVA Store Byte EVA Store possible, else unmapped. More simply, a TLB based a TLB based possible,else unmapped. More simply, Load Word EVA Word Load used by the kernel. Further, th kernel.used by the Further, Store Word EVA Word Store Load-Linked EVA Load-Linked COP0 Unusable COP0 Unusable Excpt COP0 Unusable Excpt Instruction Name Load Halfword EVA Load Halfword Store Halfword EVA Halfword Store Load Word Left EVA Left Word Load Store Word Left EVA Word Store Load Word Right EVA Load Word Store Word Right EVA Word Store Store Conditional EVA Conditional Store Load Byte Unsigned EVA Byte Unsigned Load ce manual for further information on the EVA Load/Store Load/Store informationfurther ce manual for on the EVA Load Halfword Unsigned EVA Load Halfword Perform Cache Operation EVA access mode is access mode is not allowed. igured with (AM). a User access mode and processor execution Kernel e instructions are indicated by the are indicated e instructions III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: SBE SCE LLE SHE LBE Table 4.6Table Instructions Load/Store EVA LHE LWE SWE Address Error Excpt Address Error Excpt Address Error LBUE LHUE LWLE SWLE LWRE SWRE PREFE CACHEE Instruction Mnemonic Table 4.7Table Address load/store translation instructions behavior for EVA UK MK lists the type of address translation (mapped/unma lists the type of address lists kernel load/store instructions. lists kernel load/store address translation is preferred. • The address translation selected will be mapped if • OnlyKernel usable from execution mode. •conf usable on a memory segment Only AM- Access Mode in context-switching. instructions load/storeare as follows: LimitationsEVA of the on use Referen Architectural MIPS of the II to Volume Refer instructions. The availability of thes Table 4.7 ing to Segmentation Control access mode (AM) Table 4.6 an issue the if same virtual address is being simultaneously mode. An Address mode. An Address Error exception is thrown if the Supervisoror User). A Coprocessor 0 unusable exception is th MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

= Ker- = StatusKSU User User e entry format, as follows: e entry format, m is effective when the OS m is effective used. Unfortunately, modern modern Unfortunately, used. used to replace the software replace used to Address Error Excpt Error Address Excpt Error Address Address Error Excpt Error Address Excpt Error Address COP0 Unusable Excpt COP0 Unusable COP0 Unusable Excpt COP0 Unusable Excpt COP0 Unusable Excpt COP0 Unusable Excpt memory. Hardware acceleration memory. =1. ged Resource Architecture, Rev. 6.02 PW Config3 apped unmapped register can provide the address of a TLB entry - entry a TLB of the address register can provide mapped unmapped ge sizes, and store TLB entries inbyte 8, 16TLB entries and 32-sizes, and store ge s enhancements to page tabl page to s enhancements m is only used for this fast-path handler. This hardware m is only used for this fast-path handler. Supervisor Supervisor Base This mechanis Base address. pped) performedpped) by ordinary load/store instructions Address Error Excpt Address Error Excpt Address Error rown if the access mode is not allowed in the current exe- in mode is not allowed if the access rown Context Entry (PTE) is located in located Entry (PTE) is COP0 Unusable COP0 Unusable Excpt COP0 Unusable Excpt COP0 Unusable Excpt COP0 Unusable Excpt COP0 Unusable Excpt ze, and a 4k physical page size is 4k physical page ze, and a and processor execution mode (defined by mode and processor execution chitecture. The mechanism can be chitecture. The mechanism leaf levels of the Page Table hierarchy), and Base Page Size for the (Pagefor thePage Size hierarchy), Base and oflevels the Page Table leaf Kernel Kernel mapped mapped Walking feature is denoted when Walking unmapped unmapped Address Error Excpt Address Error Excpt Address Error Address Error exception is th Address Error exception an optional feature an optional in the feature ar Table 4.7Table Address load/store translation instructions behavior for EVA UK MK mapped USK USK MSK MSK UUSK unmapped unm UUSK unmapped MUSK mapped mapped mapped MUSK mapped Table 4.8Table instructions load/store ordinary for behavior translation Address MUSUK unmapped mapped mapped lists the type of address translation lists the type (mapped/unma of address MUSUK erarchy). This is the baselineThis hi definition.erarchy). Inferred size Entry (PTE) levels (leafthe PageTable levels of Table supported at non-leafare PTEs levels. AM- Access Mode AM - Access Mode cution mode. 2. A reservedThisis addedfield forbeen fieldextensions.future to PTEs. has 1. HugePage support indirectories (non- The Hardware Page Table Walker feature additionally include feature Walker Table Hardware Page The nel, Supervisor or User). An nel, Supervisor or User). mechanismtheis not Invalid TLB used for handler (or slow-pathhandler). MIPS PrivilegedThe Resource Architecture (PRA) mechanisms includes intendedfor rapid handlingexcep- of TLB tionsin software. Followinga TLB-related exception, the Page Table Walking is the process by which a Page Table Table Page by which a the process is Walking Table Page handler for the TLB Refill condition. This hardware mechanis Table 4.8 according to Segmentation Control access mode (AM) is walking for page table calculated from the faulting virtual address and a Page Table calculated from the faulting virtual address and a Page Table page table is single level,TLB entry the is 16 bytes in si operatingpa systems use multi-levelpagetables,use different byte forms. Page the Hardware existence of The 52microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers 4.12 Walker Table Hardware Page Virtual Memory Virtual

PWCtl Context pairs in the Page Table Table in the Page pairs tional if Huge Pages are sup- Pages tional if Huge ectories. A Directory consists ectories. A Directory consists acent directory entry is used acent directory entry d to the size of the page (which is of the size d to the 4.12 HardwarePageTable Walker EntryLo1

physical are both addresses derived configureseparation thePage between and =1 ed Resource Architecture, Rev. 6.02Architecture, ed Resource 53 register specifies the per-VPE page table register the per-VPE specifies DPH EntryLo0/1 her Directory or to a Page Table. Table. a Page Directory or to her EntryLo0 EntryLo0 PWCtl PWBase =1. If an ImplementationsupportsHuge Pages inthe port Huge Pages in the directory levels, then the Adja-inthe then the directory levels, port Huge Pages ges which have ges which physical adjacent virtual and addresses. dress space. This is the default method that is supported r the even page and the adj the even page and the r lowest (leaf) elements of which are Page Tables. A Page Page Tables. of which are (leaf) elements lowest ngle directory entry. The memory region is divided evenly ngle directory entry. . The Dual Page method is op . The Dual Page Page Tables are knownas Dir Page Tables since the since Hugepg be adjacent to each other. If since each PFN to be adjacent does not have to each other. mechanism forindependent refillingTLB, the of the PWCtl within the directory entry is aligne is within the directory entry The physicaladdressalignedThe held withinthe to entry is directory 2 x cal address. They may also have differing page page physical have differing They may also not address. in virtual, but . Adjacent Pages a multi-level page table structure. Page Table Walker. These registers also registers These Walker. Table Page r in a Directory is either to anot III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: andshifting post-loadPTEs. of registers specify address generationThe levelsof four for up to page table. pport the Adjacent Page method ge Table support ge Table PWSize and PWField for the odd page. The physicalheld address knownpowerThis method Dual Pagesa of 4). is as an implementationsupporttochooses HugePages in the directory levels,the thenPage method Dual is an addi- tional option. from one entry and to behave adjacent in the physical ad by thisspecification. If animplementation chooses tosup methodcent Page implemented. must be used fo one directory entry is this case, For Table. Page between the even page and the odd page the and between the even page Since the even page and the odd page are derived from a single directory entry, they will theyboth inherit the same Sincefromderivedthe the even page and a singleare odd pagedirectory entry, attributes and but all one of the address bits from the si size of theThis is distincta power4).(which page from is of which are only guaranteed to be adjacent guaranteed to be only are which attributes. This methodis knownas The next figure shows example of an Table is an array of Page Table Entries. Levels above the Entries. Levels above Table is an array of Page Table of an array of pointers. Each pointe Examples of power-of-4 regions (start withregionsmultiplykBand1 (start ofof times):Examples number power-of-4 by 4 a MB,4 256 MB, 1 MB, 161GB.256 MB, MB, 64 MB, regionskB (start withofExamples 2x power-of-4 1 and multiplyof by4a number times; thenmultiple by 2) 5122GB.512128 MB, MB, MB, 32 MB, 8 MB, 2 MB, HugePage Support is optionalandindicated is by 2.the Page in Base a manner as page, it is handled in exactly the same power-of-4 Page is itself a a Huge Where base. The register. Four additional coprocessor 0 registers are added. The Table Entries (PTEs) in memory memory in (PTEs) Entries Table A multi-levelthe - tree structure page table system forms a The hardware page table walking system specifies a specifies walking system table hardware page The register controlsthe behavior of the A Huge Page may logically mayA HugePage in two be specified ways: 1. A Huge pa Page composed of two is a region power-of-4 directory levels, it must su ported. The implementationported. The Dual Pagemethod of indicated is by 4.12.1 Multi-Level Pa MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

. This is the Global. This is . This is the Upper Upper the is . This GDI UDI PWField PWField ged Resource Architecture, Rev. 6.02 exceptions such as Address Error, Pre- exceptionsAddress Error, such as detected, abort. detected, abort. register e if entry is PTE. If PTEVld bit is set, write Huge e if entry is PTE. If PTEVld bit is set, write Huge e if entry is PTE. If PTEVld bit is set, write Huge pointer, after multiplying (shifting)by the nativepointer, pointer, after multiplying (shifting)by the nativepointer, tableaborted walk, the HW walkingprocess is do-code at end of this section). Page Walking is com- Page Walking this section). do-code at end of do-code at end of this section). Page Walking is com- Page Walking this section). do-code at end of do-code at end of this section). Page Walking is com- Page Walking this section). do-code at end of hardwarethe is walk, HW walking page table process PWBase ge table walk reads from mapped regions of the Virtual ge table walkmappedof reads fromregions the Virtual =0, skip to the next step. =0, skipnext to the step. =0, skipnext tothe step. an exception is an exception is MDW GDW UDW a location within the Upper Directory. ddress in the temporary pointer, of returned the nativesize. The pointer theddress in temporary pointer, ddress in the temporary pointer, ofreturned The the nativesize. pointer theddress in temporary pointer, PWSize PWSize PWSize be taken. This includes synchronous mporary pointer. If mporary pointer. mporary pointer. If mporary pointer. ways treated as 32 bit addresses. treated as ways bitsthe from faulting with address, least-significant bit bits from bits faulting the address, with least-significantbit UDW GDW B followingTLB write. a s exceptionis detectedthe during hardware page PWSize PWSize Page into (detailsread TLB pseu left out for brevity, Hugeafter plete Page is written to TLB. Pageinto TLB (detailsread pseu left out for brevity, after Hugeplete Page is written to TLB. Pageinto TLB (detailsread pseu left out for brevity, after Hugeplete Page is written to TLB. pointer size. The result isresult a pointersize.pointera location to The within the Global Directory. Directory index (Gindex).Logical OR onto the temporary value is placed into the te pointer size. The result is a pointeris result to size.pointer The Directory index (Uindex).LogicalOR onto the temporary value is placed into the te • Extract • Extract •from the a a memory read Perform •from the a a memory read Perform • Huge If Pages are supported, check PTEVld bit to determin • Huge If Pages are supported, check PTEVld bit to determin • Huge If Pages are supported, check PTEVld bit to determin 2. The native pointer size is set to 4 bytes (32 bits). 3.thedisabled Globalby If Directory is If a synchronousIf exception conditionduring is detected the aborted and a TLB Refill exception will cise DebugDatacise Breakexceptions and other TLB resultingto from mapped accesses regions. If an asynchronou and the asynchronous exception is taken. This includes asynchronous exceptions such as NMI, Cache Error, and asynchronousand the exception taken. includesis This exceptions asynchronous such as NMI, Cache Error, Interrupts.alsoincludes It theasynchronous MachineCheck exception whichfrom results multiple matchingentries beingin present the TL Implementations are not requiredto support hardware pa Address space. If an implementation does an implementationspace. If notAddress support reads from mapped regions, an attempted access during a page TLB Refill exceptionwalkprocesswill to be aborted, and a tablethe be taken. will cause Pointers within Directories are al Hardware pagetable walking as follows: is performed 1.the of A temporarycontents loaded pointer with the is 4.disabledbythe is Upper Directory If 5.the Middle If disabled Directory by is 56microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Virtual Memory Virtual

and EntryLo1 , . This is the Middle MDI This is the Page Table This is the Page Table PTI by the hardware page tablehardware by the placed right of the RI bit in PWField 4.12 HardwarePageTable Walker PWField e Page Table Entry. If an exception is Entry. Table e Page feature requires the RI bit to be placed placed be to the RI bit feature requires -1. of entries inof entriesdefinition: the baseline Direc- values. These operations are used to operations values. These ed Resource Architecture, Rev. 6.02Architecture, ed Resource 57 EntryHi, PageMask, EntryLo0 EntryHi, , PTEI register field indicates whetherPage Huge detected, abort. EntryLo1 HugePg PWField BadVAddr d of an entry. For all but the last level dtable of (leaf an level),entry. and B refill exceptions are unused are B refill exceptions is required that the XI bit to be e, the entry is always a PTE and 1 is always for PTEs. In the leaf table, the entry PWCtl ss of the second half of the Page Table Entry. halfPage Table of the second of thess ss of the first half of the Page Table Entry. of of the first the Page Table half ss bits. This is the first half of the Page Table Entry. If an excep-an If Entry. ofThisis the first the PageTable bits. half an exception is EntryLo0 PTEI multiplying after onto the (shifting)temporary bypointer, the native bits. This is the second half ofsecond th is the bits. This half . Similarly, it . Similarly, ddress in the temporary pointer, ofreturned size. The the native pointer theddress in temporary pointer, ddress in the temporary pointer, of returned the nativesize. The pointer theddress in temporary pointer, ddress in the temporary pointer, of returned the nativesize. The pointer theddress in temporary pointer, PWField -2 (shifting in zeros at the most significant bit) and then rotated right by 2 PTEI inferred size, and leaf PTE of size. For optionsbase other than baseline, the PTEI . mporary pointer. If mporary pointer. III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: PWField PTEW emory data structures. There are three types three types are emory data structures. There PWField bits from faultingthe address, with least-significant bit e implemented and enabled, the HW Page Walker MDW bits from bitsthe faulting address, with least-significantbit PWSize PTW e implemented. PWSize . PWSize Directory indexDirectory (Mindex).Logical OR a pointeris a locationresult tosize.within pointer The the Middle Directory. value is into the placed te value is shifted right byisvalue shifted right detected, abort. tion is detected,tion is abort. value is logically shifted right by BadVPN2 •from the a a memory read Perform index (PTindex). Multiply by (shift) index the (PTindex). native pointer size, then multiply (shift) by the size of the Page Table in specified Entry, • The temporarynow pointer contains the addre •from the a a memory read Perform • The temporarynow pointer contains the addre •from the a a memory read Perform • Extract • to be used. The temporarynow pointer PageTable containsof the the address random) instruction. non-leaf PTEs ar non-leaf PTEs All PTEs are shifted right by rightPTEs are shifted All bits before formingbitsbefore the page-walker equivalentsof removeSoftware-only theplacingand bits the RI and XI protectionproper bitsthe in location bit before writing the TLB. If the RI and XI bits ar right of the G bit in the PTE memory format the PTE memory format. and the PTEvld bit is not used by Hardware Walker. The PTEvldWalker. and thenotis bit used by Hardware All entries are read from in-m read are entries All Context Huge Page non-leafPTE of tory Pointer, entry typeis a function of the tablefiel PTEvldthe level and the PTEvld bit is 0 for directory pointers to the next table 6. Extract 8. Entry into the TLB, using the same semantics as the TLBWR (TLB the two write halves of the Table Page Write 9. Continue with program execution. onwhich TL software are used by0 registers Coprocessor 7. set Inthe the bit temporary located pointer, at bit location walking process. The registers and by software are fields used walking process. and The registers 4.12.2 PTE and Directory Entry Format MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

XI and RI field. If non-leaf PTE Comment Psn 0 Comment TE, 4-bitswhich are just left of Comment to be at bit 0 e wider PTE allows for the use of allows PTE e wider PWCtl Page Size=Base Page Page Size=HgPgSz Page Size=HgPgSz ged Resource Architecture, Rev. 6.02 PTE format in memory Directory Ptr format interpreted by PTE interpreted format by HW Page HW Page Walker; PTEvld configured PTEvld Page Walker; HW Walker; PTEvld configured to be at bit Walker; ld=1 ld=0 PTEv PTEv C D V GC Page Size=Base D V G Page Size=HgPgSz 5..3 2 1 0 1 0 bit withinDirectory the ofanyPointer those field, as rmat is requiredrmat when is more than 32-bitsof physical by HW Unused or PTE entries. The 8-byte widthis configuredhav-by or PTE entries. The 4-byte widthis configuredhav-by 6 5..3 2 1 0 e software handler TLB to distinguish non-leaf entries PTE igured to pointthatto bit software within PTE. the 9:6 register format. register format. In the non-Leaf P 0 Reserved (must be 0) edfor Software-only flags. The following figuresassumea PTE for- EntryLo PFN 10 =6 and a Base Page Size of 4k for simplicity. Size of =6 and a Base Page ppropriate to be used to distinguish between a Directory Pointer or a non-leafdistinguish toppropriate to be used or Directory a Pointerbetween a Figure 4.10Figure PTE Leaf 4-byte ..0) (shifting..0) in zeros at the most significant bit) and thenrotating PTEI C D V G RI XI Use S/W C DVGRIXI C DVGRIXIS/W Use C DVGRIXIS/W 12 11 Figure 4.12Figure PTE Formats Rotated 4-Byte Figure 4.11Figure PTE Options Non-Leaf 4-byte ill already be a bit used by th by be a bit used ill already 21987654 3..0 1211 PWField =0, =0, Psn 31 30 29 Reserved Reserved (must be 0) (must be 0) =0. this In us example, 4bits are =1. This example uses 4-bits for Software-only 4-bits th flags.uses use The of example =1. This PFN PWCtl PTEW PTEW Dir Pointer 31:12 Dir Pointer bits to be used for addressingto bits be used for PTE fo - the 8-byte PFN PFN PFN Comment 31 30 29 field are reserved for future features. Leaf PTE RI XI C PWSize PWSIze Non-leaf PTENon-leaf RI XI PFN 31 31 31 987654 1615 1211 3..0 31 987654 3..10 1615 1211 The following figures show an example of 8-byte pointers ing more addressing is to be implemented.bothspace, directory pointerof Both take8-bytes memory the non-leaf and PTE Notethat the bit position of PTEvldis not fixed0. atcanbe Itprogrammed the by entries are available, there w entries are the PTEvld bit fromis directoryconf pointers. Normally, programmingA possible to avoid error is placingPTEvld the mayaddress bits be set and thus not a PTE. The following figures show an example of 4-byte pointers ing mat based on on based mat the fieldsbits into 31:30, the PTE matches the After shiftingsoftwarethe out bits (3 58microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Virtual Memory Virtual

=1 to denote 8- PTEW values. When the 0

Comment Comment PWSIze ured to be at bit 0 Page Size=Base icant bit) and the RI and XI the icant bit) and Page Size=HgPgSz Page Size=HgPgSz EntryLo1

PTE format in memory Comment 4.12 HardwarePageTable Walker and for future for future features. Directory Pointer format interpreted format interpreted Pointer Directory PTE interpreted format by HW Page by HW Page Walker; PTEvld config- Page Walker; HW by figures assume a PTE formatfigures based on PTE assume a Walker; to be at PTEvld configured bit Walker; occur with just one entry (Adjacent Page just one entry (Adjacent with occur ed Resource Architecture, Rev. 6.02Architecture, ed Resource 59 ld=1 ld=0 PTEv PTEv EntryLo0

1 0 by HW Unused represent represent adjacent physical pages. field are reserved

register format. By setting register format. By setting byte PTE, but only but4-bytesPTE, bytethe lower are written into the C C D V G Page Size=HgPgSz ng in zeros at the most signif ). However, non-leaf PTEs (ones which occur in the non-leafin upper(ones which occur PTEs ). However, 0 EntryLo 6 5..3 2 1 0 EntryLo1

EntryLo1 and

Rsvd Rsvd (must be 0) and C D V G RI XI S/W Use CDVGRIXIS/W Use CDVGRIXIS/W CDVGRIXI r a PTE in a directory, the least significant bit above thepageis 0 forsize r a PTE in a directory, 11 EntryLo0 Figure 4.13Figure PTE Leaf 8-byte 218643..0 1211987654 (if Dual Page method is enabled) or enabled) is (if Dual Page method 12 11.9 8 7 6 5 4 3..1 0 12 11.9 8 7 6 5 4 3..0 single non-leaf PTE represent both single EntryLo0 III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Figure 4.15Figure PTE Formats Rotated 8-Byte Figure 4.14Figure Options PTE Non-leaf 8-Byte That is, Reserved Reserved 31 30 29..10 9..6 5..3 2 1 0 (must be 0) (must be 0) =6 and a Base Page Size of 4k for simplicity. Page Size a Base =6 and PFN 31..12 16 15 16 15 PTEI EntryLo1. Directory Ptr Directory

Comment 31 30 29 Leaf PTE RI XI PFN C D V G Page Size=Base PWField Non-leaf PTE RI XI PFN and 1 for =0, Psn 33 35 63:36 Rsvd 63:36 35 63:39 35 Rsvd Rsvd PFN Rsvd PFN Leaf PTEs always occur in pairs ( pairs always occur in Leaf PTEs After the software bits (3..0) are right shiftedare bits (3..0) software After the away (shifti walker populates the EntryLo registers fo walker populates the EntryLo registers byte PTE entries,isdone the shift operationbyte entire on the 8 non-LeaftheTLB. In PTE, 4-bits which are just leftthe of directories) can occur either in pairs method). For the Adjacent Page method, the EntryLo0 for the memory address. The for the used address. following memory actually are only 32-bits though PWCtl fieldsmatches are rotated the 31:30,PTE to bitsthe 63 32 MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

as synthesizedfrom EntryLo1 specific whether the PTEVld specific of the typical 512 entries. and ) = 2^31EntryLo0/1 = 2GB. Each) =

Note that the index into PMD has the index into PMD Note that PTI ged Resource Architecture, Rev. 6.02 EntryLo0 PWField vel by the Hardware Page Walker. vel by the Hardware Page Walker. ) * 2^12( ) = 2^21 = 2 MB. Each EntryLo0/1 page is 1 MB,Each EntryLo0/1 page is 1 = 2 MB. ) = 2^21 =1), it is implementation- PTI thus has 1K entries instead PTW DPH ferred fromferredin levelthe the directory which Huge Page Page Method is used (if the Dual Page Method is imple- memory for writing the second TLB page. The recommended PWCtl PWField PWSize gister 5, Selectgisterpage161 5)" on . It a leaf PTE size assumes kB. of 4 ) * 2^9 ( ) * 2^9 , then the Adjacent Page Method is used. is Method then the Adjacent Page , ) * 2^12) ( MDW PTW er-of-4, and the Dual Page Methodsthe and Dual Page implemented,is not er-of-4, it is implementation- TEs are read from the directory le TEs are read the directory from hod, the size of PTE in each individual ster (CP0 Register 5, Select 7)" 164 page on 7)" 5, Select Register (CP0 ster PWSize PWSize register field is used to differentiate between different types of Machineexceptions. of types Check between different field is used to differentiate register

MCCause * level. privilege the KERNEL using performed are Memory accesses * exit a silent cause accesses memory on detected exceptions Synchronous * exception. Refill in a TLB resulting table walking, from page * * memory table walk page to support not required are Implementations * access is an unsupported When regions. memory from mapped accesses * exception. TLB Refill in a resulting is taken, exit a silent attempted, * * or LoadMemory by AddressTranslation is caused if an exception Note that * is taken, silent exit a is not taken, the exception functions, * exception. Refill in a TLB resulting * and would use the Adjacent Page and would use the Adjacent Page method. page is 1GB, which is a power-of-4 been extended to 10 bits from 9 bits. Each PMD table /* Perform hardware page table walk which is a power-of-4 and use the Adjacent Page method. Page the Adjacent and use a power-of-4 which is Section9.19, "PWField Register Register (CP0 6)"Select on page 161 5, Section 9.20, "PWSize Regi Section 9.18, "PWBase Register (CP0 Re Section 9.22, "PWCtl Register (CP0 Register 6, Select 6)" on page 171 page on 6)" Select 6, Register (CP0 Register "PWCtl 9.22, Section •2^10 ( PUDHuge Page = The hardwareThe walking page table process is described in pseudocode as follows: PageGrain For the Dual method, Page thetwo P • • See also: • the single Huge Page is always half the inferredsize. thealways the single half Huge Page is 2 x power-of-4 is page size the inferred If If the inferred page size is a power-of-4, then the Dual then a power-of-4, is page size the inferred If mented).Page method If the Dual is implemented ( bit is checked for the second PTE when it is read from behavior is to check this second PTEVld bit and if it is not set, a Machine Check exception is triggered. The specific whether a Machine Check is reported. specific whether a HugeAn example of Pagehandling follows • PMD Huge Page = 2^9 ( If the inferred Huge Page sizeHugethe is pow Page inferred If For HugePage handling,inthe Huge Page is size of the Page Met For the Adjacent resides. • 4.12.3 walking process table Hardware page 60microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Virtual Memory Virtual

)) +1) 4.12 HardwarePageTable Walker PTEW PTEW )-1) )-1) )-1) )-1) MDW ed Resource Architecture, Rev. 6.02Architecture, ed Resource 61 GDW UDW PTW >0) then MDW ) and((1<0|PWSize UDW III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: vAddr or Goffset  vAddr KERNEL) DATA, LOAD,  AddressTranslation(vAddr, DATA) vAddr, pAddr, DSize,  LoadMemory(CCA, PWSize UNPREDICTABLE 2 32   >0| vAddr >> PWField vAddr >> PWField vAddr >> PWField vAddr + PWSize << (NativeShift >> 1) PTindex vAddr >> PWField vAddr  = 0) then > 0) then > 0) =0) then Gindex << NativeShift Gindex << NativeShift Uindex << NativeShift Mindex + PWSize << (NativeShift OR (1 PToffset0 False False false false False UNPREDICTABLE UNPREDICTABLE PW GDW               GDW PWEn PWBase BadVPN2   return (0) # no structure to walk to no structure (0) # return values # Initial vAddr CCA) (pAddr, t return(0) # walker is unimplemented walker # return(0) is disabled # walker (0) return Uoffset Uoffset Moffset PToffset0 Uindex Uindex Mindex PTindex tables into # Offsets Goffset PToffset1 found encMask   HugePage  HgPgBDhit  HgPgGDhit  HgPgUDhit  HgPgMDhit size pointer # Native NativeShift DSize address faulting from computed # Indices Gindex EntryLo0  EntryLo0  EntryLo1 Context if (Config3 # Global Directory # Global if (PWSize # Starting address - Page Table Base Table Page address - # Starting  vAddr if (PWCtl if !(PWSize For readability, this pseudo-code does not deal with PTEs of different widths. widths. of different PTEs with deal does not this pseudo-code For readability, * In reality, implementations will have to deal with the different PTE PTE the different deal with have to will implementations In reality, * widths. pointer and directory * */ * * subroutine PageTableWalkRefill(vAddr) : PageTableWalkRefill(vAddr) subroutine MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

ged Resource Architecture, Rev. 6.02 =1) then# PTEvld is set PTEvld =1) then# =1) then # PTEvld is set PTEvld # =1) then ) GDI Hugpg Hugpg - 2 // shift entire PTE entire 2 // shift - - 2 // right-shift entire PTE entire - 2 // right-shift - 2 // shift entire PTE entire - 2 // shift PTEI AddressTranslation(vAddr2, DATA, LOAD, KERNEL) LOAD, DATA, AddressTranslation(vAddr2,  t  t  t  t ) && PWCtl ) && PWCtl PTEI PTEI and 0x1)=1) // check if index is odd e.g. 2x power of 4 power 2x e.g. is odd if index // check 0x1)=1) and Psn Psn and 0x1)= 0x1) //check if odd e.g. 2x power of 4 2x power e.g. if odd //check 0x1)= 0x1) and = 1) = 1) t and not lsb # lsb=0 even page; note FILL fields are 0 FILL fields note even page; # lsb=0 not lsb  t and odd page # lsb=1  t or lsb t and not lsb # lsb=0 even page; note FILL fields are 0 fields FILL note even page; # lsb=0 not lsb  t and page odd # lsb=1  t or lsb )-1 )-1 GDI UDI DPH DPH UDI GDI vAddr xor OddPageBit vAddr xor vAddr or Uoffset  vAddr KERNEL) DATA, LOAD,  AddressTranslation(vAddr, DATA) vAddr, pAddr, DSize,  LoadMemory(CCA, (1<> 6 // align PA[12] into EntryLo* register bit 6 register EntryLo* into align PA[12] 6 //  (1<> (1<> 6  (1<> ROTRIGHT(t, 2) // 32-bit rotate to place RI/XI bits place RI/XI to 32-bit rotate 2) //  ROTRIGHT(t, pw_EntryLo0 pw_EntryLo1 pw_EntryLo1 pw_EntryLo1 pw_EntryLo0 DATA) vAddr2, pAddr2, DSize,  LoadMemory(CCA2, >> PWField  t > 0) then > 0) t OddPageBit) and if (vAddr else endif ERROR goto bits place RI/XI to rotate 32-bit 2) //  ROTRIGHT(t, ROTRIGHT(t, 2) // 32-bit rotate to place RI/XI bits RI/XI place to 32-bit rotate 2) //  ROTRIGHT(t, OddPageBit) and if (vAddr else endif  vAddr2  CCA2) (pAddr2, t t t >> PWField  t lsb pw_EntryLo0 pw_EntryLo1 t >> PWField  t pw_EntryLo1 lsb pw_EntryLo0 (1 << PWField = OddPageBit UDW if ( (PWFIELD else endif REFILL goto  t vAddr t w  (PWFIELD t w  (PWField ( ( PWField if TLB page other for directory PTE from load second // HugePage  true HugePage  true HgPgUDHit t odd TLB page PTE for same from page adjacent generate // (PWCtl elseif true  HugePage  true HgPgGDHit t (PWCtl elseif // generate adjacent page from same PTE for odd TLB page PTE for same page from adjacent generate // first page loaded odd or even out whether - figure Dual Pages // else endif if (t and (1<

) PTEW 4.12 HardwarePageTable Walker ed Resource Architecture, Rev. 6.02Architecture, ed Resource 63 =1) then# PTEvld is set PTEvld =1) then# ) ) MDI UDI Hugpg - 2 // right-shift entire PTE entire 2 // right-shift - - 2 // right-shift entire PTE entire // right-shift 2 - - 2 // right-shift entire PTE entire - 2 // right-shift PTEI PTEI AddressTranslation(vAddr2, DATA, LOAD, KERNEL) DATA, AddressTranslation(vAddr2, AddressTranslation(vAddr2, DATA, LOAD, KERNEL) DATA, AddressTranslation(vAddr2,  t  t  t  t  t  t ) && PWCtl PTEI Psn = 1) and 0x1)= 0x1) // check if odd e.g. 2x power of 4 2x power odd e.g. if // check 0x1)= 0x1) and )-1 DPH MDI MDI vAddr xor (1 << (NativeShift + PWSize (NativeShift (1 << vAddr xor vAddr xor OddPageBit vAddr xor t # note FILL fields are 0 fields are FILL  t # note t and not lsb # lsb=0 even page; note FILL fields are 0 FILL fields note even page; # lsb=0 not lsb  t and odd page # lsb=1  t or lsb III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: vAddr OR Moffset  vAddr KERNEL) DATA, LOAD,  AddressTranslation(vAddr, DATA) vAddr, pAddr, DSize,  LoadMemory(CCA, ageBit = (1 << PWFIELD (1 ageBit = LoadMemory(CCA2, DSize, pAddr2, vAddr2, DATA) vAddr2, pAddr2, DSize,  LoadMemory(CCA2, >> PWField  t bits place RI/XI to rotate 32-bit 2) //  ROTRIGHT(t, pw_EntryLo1 pw_EntryLo1 pw_EntryLo0 pw_EntryLo1 pw_EntryLo1 pw_EntryLo0 DATA) vAddr2, pAddr2, DSize,  LoadMemory(CCA2, >> PWField  t bits RI/XI place to 32-bit rotate 2) //  ROTRIGHT(t, pw_EntryLo0 pw_EntryLo1 > 0) then > 0) (pAddr2, CCA2)  CCA2) (pAddr2, t t t ROTRIGHT(t, 2) // 32-bit rotate to place RI/XI bits place RI/XI to 32-bit rotate 2) //  ROTRIGHT(t, OddPageBit) and if (vAddr else endif  vAddr2 if (vAddr and OddPageBit) OddPageBit) and if (vAddr else endif  vAddr2  CCA2) (pAddr2, t t t OddPageBit) and if (vAddr else endif ERROR goto t >> PWField  t (1 << PWField = OddPageBit OddP MDW t pw_EntryLo0 w  (PWField if ( (PWField page odd TLB for directory PTE from load second // // load second PTE from directory for odd TLB page TLB odd for directory PTE from load second // else endif REFILL goto  t vAddr HugePage  true HugePage  true HgPgMDHit t pw_EntryLo1 (PWCtl elseif first page loaded or odd even out whether - figure Dual Pages // // Dual Pages - figure out whether even or odd page loaded first loaded page or odd even out whether - figure Dual Pages // odd TLB page PTE for same from page adjacent generate // bit 6 register EntryLo* into align PA[12] 6 //  (1<> lsb pw_EntryLo0 else endif vAddr CCA) (pAddr, t (t and (1<

ged Resource Architecture, Rev. 6.02 ASID - 2 // right-shift entire PTE entire right-shift - 2 // PTE entire right-shift - 2 // PTEI PTEI PTEI ))-1 ))-1 ))-1 ))-1 BDI GDI UDI MDI  t  t )-1 ntryLo0 m>>12 PTI  (1<<(PWField (1<<(PWField (1<<(PWField (1<<(PWField pw_EntryLo1 pw_EntryLo1 or PToffset0  vAddr KERNEL) DATA, LOAD,  AddressTranslation(vAddr, DATA) vAddr, pAddr, DSize,  LoadMemory(CCA, or PToffset1  vAddr KERNEL) DATA, LOAD,  AddressTranslation(vAddr, DATA) vAddr, pAddr, DSize,  LoadMemory(CCA, >> PWField  temp0 pw_E ROTRIGHT(temp0, 2) // 32-bit rotate to place RI/XI bits RI/XI to place rotate // 32-bit 2)  ROTRIGHT(temp0, >> PWField  temp1 bits RI/XI to place rotate // 32-bit 2)  ROTRIGHT(temp1, Mask m  m  m  m  else endif ERROR goto if (vAddr and OddPageBit) OddPageBit) and if (vAddr case 0100 case 0010 case 0001 case case 1000 case else endif REFILL goto  t vAddr (1<>12) 4KB as smallest to mask field Normalize step: # 2nd pw_PageMask if (HugePage) if (HugePage) then endif pair of PTE half - First Page Table Level # Leaf vAddr CCA) (pAddr, temp0 pair of PTE half - Second Page Table Level # Leaf vAddr CCA) (pAddr, temp1 into TLB pair Table Entry Page # Load temp0 pw_EntryLo0 temp1 pw_EntryLo1  1 found m  EntryHi 0xfff )| not and = ( vaddr pw_EntryHi REFILL: manner in a the TLB page into a inserts walker page hardware # The handler refill software by the executed as instruction to a TLBWR # identical 64microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Virtual Memory Virtual

4.12 HardwarePageTable Walker ed Resource Architecture, Rev. 6.02Architecture, ed Resource 65 ftware attempts to use the invalid TLB entry, a ftware attemptsuse the to invalid TLB entry, will still fill thepage into the Software can TLB. point to are not mapped. When the So are not III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: return(0) f an error/exception condition is detected on a page table page on a detected is condition f an error/exception # walk memory access, this function exits with found=0. exits with this function access, memory # walk # OnError: return(found) # I endsub TLB invalid exception will be generated. If a page is marked invalid, the hardware refill handler invalid PTEs to represent regions that MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

ged Resource Architecture, Rev. 6.02 66microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Virtual Memory Virtual

(CP0 reg- , An example is the CDMMBase tiated once per VPE, but the VPE, tiated once per pped to correspond to the control and status information in that is reserved for mapping IO reserved is that access could be allowed through a region. For that reason, the memory For region. as part of the CPU. as part ccupies a maximum of 32 kB in the a maximum ccupies cached memory transactions. Accessing Accessing transactions. memory cached CDMMis implemented by readingthe behavior. behavior. ed Resource Architecture, Rev. 6.02Architecture, ed Resource 67 wed, this region could be ma wed, ces and their ACSRs are instan and their ACSRs ces the base physical address of the CDMMaddress physical the base UNPREDICTABLE defined by a coprocessor 0 register called0 defined by a coprocessor Rs), followed by IO device registers. Rs), followed by IO Blocks’ (DRBs). Each block has access Blocks’ (DRBs). Each block has access ed, uncached access via kseg1. User-mode ed, uncached access the architecture. Software detects if r these device registers. The CDMM o registers. r these device maintain cache coherence for the CDMMcache maintain region be accessed must only using un mory-mapped IO devices that are packaged that IO devices mory-mapped III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: ion of the memory address space. It also enables the use of access control and mem- of access the use enables address also the memory It space. ion of - A new Coprocessor 0 register that sets register 0 - A new Coprocessor register field (bit 3). register is shared among the VPEs. the among register is shared CDMM CDMMBase access control and status registers (ACS and status control access aligned blocks called ‘Device Register Each of these blocks are nowof described these blocksare detail.Each in mapped registers located within this these register using a cacheable CCA may result in result cacheable CCA may these register using a physical address map. The CMDMM is of an optional feature Implementations are not required to Two blocks are defined for the CDMM- Two • ister 15, select 2). This address must be aligned to a 32 kB boundary. must be aligned addressThis to a 32 kB boundary. select 2). 15, ister coreOn a 32-bitTLB-based MMU, this region with would a most likely bemapped to the lower 512 MB of physical allowing kernel-mode unmapp memory, coherency. uncached an TLB mapping using MMU,a FMT thatwould use the regionOn cores most likely be mappedthe to MB and made lower 512 accessible is allo access user-mode if Alternatively, via kernel mode. The physicaladdress for the CDMM facility base is CDMMBase Config3 MIPS processors may include me processors MIPS probemove pins to to data communicationEJTAG the that device uses DebugFastwhich Channel, is a UART-like world. the external space physical address a region of Device Memory Map (CDMM) is Common The The CDMMdevice configuration helps registersaggregate withinvarious devicea MIPS mappings processor. into one area, preventing fragmentat ory address translation mechanisms fo •ControlDevice CDMMand Access kBCDMMThe 32 Register region- Block is divided into smaller 64-byte For implementations that have multiple VPEs, the IO devi kuseg physical address segment.kuseg physical address MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 5.1 CDMMBase Register Common Device Memory Map Memory Device Common Chapter 5 Chapter

shows the organization organization the shows RBs), Each device occupies device RBs), Each registersubsequent and any ing modified. Reading any of modified. ing Figure 5.1 Figure (ACSRs) that are (ACSRs) that are start found at the If user mode access is allowed, If user mode the ged Resource Architecture, Rev. 6.02 register. register. t offset 0x0 from the is CDMMBase) t offset CDMMBase de when such accesses are not allowed, de when such accesses region would be mapped to a physical be mappedregion would to its’ ACSR. ACSRs are only accessible in are only accessible ACSRs its’ ACSR. CDMMBase ‘Device Register Blocks’ (D ‘Device Register Blocks’ nored and the register not be l zeros being returned. Writing any of thel ACSR being zeros returned. Writing registers a ‘Access Registers’ Control Status and for the descriptionthe of or kseg2/3 (using uncached coherency). (using uncached or kseg2/3 itionalspace,address it can occupy multiple contiguous64-byte e.g., blocks, n only increment, the devices must be n only increment, space in a spe- allocated in the memory e physical address map. For each device, device type identification and access device type identification and access each device, map. For e physical address kernel mode access is allowed, the is allowed, mode access kernel located at the address pointed by the pointed the address located at r to the start of the next device and device next start of the r to the register, the first DRBof the CDMM (a register, xt available adjacent DRB. xt available adjacent ce with the lowest physical address. lowest physical address. with the ce the DRB allocated for the devi cated in CDMMBASE Section 9.42 on page 227 bit is set intheset bit is CI address region reachable through kseg1 through reachable region address coherency. uncached an entry must use useg BAT refer to Please reserved for implementation specific use. The CDMMdividedThe is 64-byte into aligned segmentsnamed On cores that use a BAT MMU, if only MMU, if a BAT that use On cores of the DRBsizedevicetheThe ACSR forthethe of the IO address. holds allocated device with a of for the lowest physical a pointe act as also device, and hence kernel mode. The ACSR is followed by the data/control registers for the IO device. device is device is allocated in the ne If the at least one DRB. If a device needs add needs a device at least one DRB. If are adjacent in th multiple DRBs which control information is lo Access control information is specified vi of the CDMM. mo supervisor in either usermode or registers IO device the Reading any of any IO device of the registers in eitherresults in all usermode zeros being returned. or supervisor mode Writing when results in the write being ig allowed, are not such accesses mode results in al kernel the ACSR registers while not in while not inkernel mode results in thewrite being ignoredandbeing the ACSR not modified. Since the ACSR act as a pointer that ca The first device must be cific manner. 68microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers 5.2 Blocks Control and Device Register CDMM - Access Common Device Memory Map

State Compliance Reset ged Resource Architecture, Rev. 6.02 R PresetR Required Preset Required R 0 Required R/W 0 Required R/W 0 Required R/W 0 Required R/W 0 Required Write Read / ster Field Descriptions (Continued) Descriptions Field ster that access is disabled. An disabled. is access that that access is disabled. An disabled. is access that k. A device is limited to 4 device A k. read access to this device is This also determines the the determines also This eld to denote the specific eld to denote the write access to this device device to this access write s that accessenabled. is A 1 indicates that access is lue of 0 indicates that only that indicates of 0 lue 1 indicates that access is ss is disabled.An attempt to ss is disabled. attemptAn to isor-mode write isor-mode access to this vision of device. This field is device. of vision number of extra 64-byte blocks blocks 64-byte number of extra Description e. Ignored on write; returns zero e. on write; returns zero on Ignored e ed is ignored. ed is ignored. device is A value enabled. of enabled. A value of 0 indicates mode in supervisor while device to the to write attempt with access disabl location of the location next device bloc allocated to this device. allocated to this device. A va allocated. is block one 64-byte kB of memory. fi DevType the with combined device revision. enabled. A value of 0 indicates attemptdevice to read from the whilemode in supervisor with access disabl read. device is A value enabled. of value of 0 indicates that acce dis- with access mode in user while device from the read ignored. abled is enabled. A value of 1 indicate is enabled. A value of 1 indicates that access is enabled. A is enabled. access that A 1 indicates of value is enabled. value of 0 indicates that acce dis- access mode with in user while to the device write ignored. abled is 1 This bit indicates if superv 2 indicates if user-mode bit This 3 This bit indicates if user-mode 0read access isor-mode to this This bit indicates if superv Table 5.1 Table Regi Status and Control Access Fields 0 11:4 63:32, us future Reserved for Sr Ur Sw Uw Name Bits DevRev 15:12the re This field specifies DevSize 21:16th specifies field This 70microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Common Device Memory Map

registers, intro- registers, . Software was en software register is not register IV Count architecture that sup- architecture that Cause ritized by the processor and ritized by the interrupts were combined combined were interrupts introduced wh with GPR shadow GPR shadow with cycles required to process an inter- ically disable or enable interrupts. ocessing of Exceptions and Interrupts: and Exceptions of ocessing e Release 1 interrupt e Release 1 ed Resource Architecture, Rev. 6.02Architecture, ed Resource 71 , based on the value, based on the of register is required. ces of interrupts are prio definitionthe coprocessor of 0 register fields associ- in its name, it is more correctly described as an NMI described correctly more is it name, its in terrupt controller. This can supportmany more priori- controller. terrupt be used to clear hazards clear hazards used to be EBase bitsinterrupt inthe handler prologue. interrupt mode thatsupports the use of an external inter- er and performance counter er and performance IP e interrupt system state. mechanismto include two optional interruptmodes: register to denote pendingandtimerinter- performance counter Cause interrupt vector(0x200) Cause equals 0. The register, which allows the exception vector base address which allows the to be modified register, significantly reduces the number of controlled by the processor interrupt system. interrupt the processor controlled by a dedicated handler. When combined When a dedicated handler. BEV following features related to the pr support for twosoftware interrupts,hardwaresix interrupts, and twospecial- EBase Status bits in the III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: register for highly applications registerin the which power-sensitive PCI register which affects th which affects register adds an upward-compatible extension to th the interruptarchitecture. Count and rrupts as a function of the as a rrupts TI each interrupt is vectored directly to vectored directly is each interrupt mode this chapter, in the next duced rupt. ated with interruptssupport changesto an external in tized interrupts, while still providing the ability to vector an interrupt directly to a dedicated handler and take GPR shadow registers. the advantage of • External Interrupt Controller (EIC) mode, in which the used, or for reduced power mode. This change is required. is power mode. This change or for reduced used, are required. instructions Both •Interrupt (VI)mode, in whichthe various sour Vectored writes to a coprocessor 0 coprocessor writes to a rupts. This change is required.Thisrupts. change is for exceptions that occur when • The addition of the DI and EI instructions which provide the ability to atom • The additionof the Release 2 of the Architecture Release 2 rupt controller bychanging Although“interrupt”(NMI) includes a Non-MaskableInterrupt ports vectored interrupts. In addition,Release 2 adds a new is it nor not affect, does it exception because • The ability tostop the • The extension of theRelease 1 interrupt control •can sequence which hazard of an execution The addition required to prioritize inte Release 1 of the Architecture included included of the Architecture Release 1 purpose interrupts: timer and performance counter. The tim purpose interrupts:timer counter. and performance Release 2 of the Architecture added the of the Architecture Release 2 • The addition of the 0Coprocessor with hardwarewith Interrupts were handled interrupt eithergeneralthe through 5 in an implementation-dependent manner. the special 0x180) or exception vector (offset MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 6.1 Interrupts Interrupts and Exceptions Interrupts Chapter 6 Chapter

register Debug bit in the bit in DM register. The final interruptThe request register. ions of Release 1 of the Architecture. ions of Release 1 ged Resource Architecture, Rev. 6.02 entation of Release 1 of the Architec- the 1 of entation of Release Status register. e way in which interrupts are handled to provide full functionthethat coprocessor 0 register fields of can bit of the Config3 register are zero, and the register are zero, and IE ring interrupt processing. This modeis optional and its des. Inclusion of the optionalthedes. Inclusion of modes donebe may selec- ioritizationvectoring and This mode of interrupts. is Interrupt Mode y always be implemented and be dynamically enabled based Status y implement up to interruptthree modes: register. ocessors implementing EJTAG) implementing ocessors bit in the the in bit rrupt Controller VEIC error, non-debugmode, processing respectively. error, Config3 bits in the dds the abilitytoprioritize and vector interrupts toa handler dedicated to ERL re is fully compatible with implementat with compatible fully is re register are both zero. e 2of the Architecturee must implement interruptcompatibility mode, and

Table 6.1Table Modes Interrupt VEIC Config3 and

Status

of the Architecture ma Architecture of the VINT EXL Config3

register is a zero (for pr a zero (for is register

VS register is a one. a register is IntCtl 0 x0 x 10 Compatibility 0 x Interrupt Vectored 1 External Inte

  

IV

Debug Cause bits in the

Status

BEV ERL Status 1 xx 0 xxx x x01 x x01 Compatibility x Compatibility and bit in the bit in the shows the current interrupt modeof theprocessor as a DM EXL IE ture. This modeThis is required.ture. du use for GPR shadow set a and to assign interrupt, that presence is denoted by the VInt bit in the supportfor an external interrupt controller handling pr optional and its presence is denoted bythe A compatible implementation Releas of mayoptionally implementbothvectored one or interrupt mo Table 6.1 the mode. affect tively in the implementation or they ma of the processor, reset statecontrolisinterrupt to0processor of theon coprocessor bits. The compatibility mode such that an imple- of the Architectu mentation of Release 2 Logically, the request for interrupt ANDedis service with the Logically, An implementationof Release 1 of the only Architectureimplements interrupt compatibility mode. of Release 2 An implementation • Interrupt (VI)mode, which a Vectored An interruptis onlywhen taken following all of the true: are •for interruptrequest as a functionservice is made, A specific interruptof the mode, described below. • The • Interruptcompatibility mode, whichidentically acts to that in an implem • The is zero, correspondinga non-exception,to non- is then asserted only if both the • External Interrupt Controller (EIC) mode, which redefines th • The 6.1.1 Interrupt Modes 72microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Interrupts and Exceptions

6.1 Interrupts IM6 IM5 IM4 IM3 IM2 IM1 IM0 IM7 y read of the register (not just after and Status and Status and Status and Status and Status and Status and Status and Status = 1). This mode is in effect if any = 1). of This mode is in effect IV IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 CalculatedFrom deasserted between the time the processor between the deasserted Interrupt Request ed Resource Architecture, Rev. 6.02Architecture, ed Resource 73 Cause Controller mode are are imple- mode Controller SW0 Cause SW1 Cause ts are not implemented,are ts or have been disabled. HW5 Cause HW3HW2 Cause HW1 Cause HW0 Cause Cause HW4 Cause is zero if neither Vectored Inter- Vectored neither if is zero Source mode, interrupts are non-vectoredinterrupts and dispatched mode,are though Interrupt VS Interrupt Mode and the default interrupt mode for a Release 2 processor. interrupta Release 2 processor. and the default for mode e in Interrupt Compatibility Mode e in Interrupt Compatibility turning from the interrupt via ERET. A request for interruptrequest A turningthe from interrupt via ERET. . = 0) or vector offset = 0)0x200 or vector (if offset

IV rupt nor External Interrupt rupt nor External Interrupt mented.

methat the software interrupt handler runs. The software interrupt handler

VEIC Config3

III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: VINT Cause Table 6.2 Config3 ed). Note that an interrupt request may be

Table 6.1Table (Continued) Modes Interrupt

VS IntCtl 0 0 0 Allowed Not - IntCtl Interrupt Type

IV Cause = 1 (if it were zero, the interrupt exception would have to would have exception the interrupt zero, it were = 1 (if

IV BEV Status “x” denotes don’t care “x” denotes don’t 01 = 1 = Hardware Interrupt, Timer Interrupt, or Perfor- Hardware Interrupt, Timer mance Counter Interrupt Software Interrupt Hardware Interrupt Hardware = 0 = 0, which would be the case if vectored interrup case if vectored the be which would = 0, Table 6.2Table Request for Interrupt Servic IV BEV VS /* Assumptions: * - Cause * Cause Status IntCtl This is the only interrupt mode for a Release 1 processor a Release 1 processor interrupt mode for the only This is • This mode is entered when a Reset exception occurs. In this occurs. exception entered when a Reset is This mode 0x180 (if exception vector offset The current interrupt requests are visible via the IP field in the Cause register on an are visible via the The current interrupt requests an interrupt exception has occurr exception an interrupt ti the interrupt exception and the starts mustbeprepared to handle this condition bysimply re isservice generated as shown in A typical softwarefor interrupt handlercompatibility might mode look as follows: the following conditionstrue: are • • 6.1.1.1Mode Compatibility Interrupt MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

*/ VS ged Resource Architecture, Rev. 6.02 bits so that “lower” priority interrupts are interrupts priority “lower” so that bits IM /* and mask with IM bits */ with IM mask /* and */ 16..23 k0 = IP7..IP0; bit set, first /* Find IntCtl software emulate to /* Shift /* Jump to specific exception routine */ routine exception to specific /* Jump eret */ code interrupted to /* Return beqclz zero, Dismiss k0, xori k0 k0, sll */ interrupt - spurious bits set /* no k0, 0x17 k0, k0, VS k0, */ 7..0 => /* 16..23 mfc0mfc0 C0_Cause k0, andi C0_Status k1, and k0, M_CauseIM k0, */ from Cause IP bits only /* Keep k0, k1 k0, */ bits IP for register Cause /* Read bits */ for IM register Status and /* laaddujr VectorBase k1, k0, k1 k0, nop k0 */ vectors of 8 interrupt base /* Get */ offset base and from target /* Compute here) * type. of this an example below is routine NestedInterrupt The disabled. also */ SimpleInterrupt: /* request the interupt and clear here interrupt the device Process * to be may need registers some do this, to order In at the device. * an ERET that is such 0 state The coprocessor restored. saved and * code. interrupted to the return will simply * */ NestedException: /* registers, and Status the EPC saving require typically Nested exceptions * disabling routine, exception the nested by modified be that may any GPRs * loop, putting an interrupt to prevent Status bits in IM the appropriate * code The sample interrupts. re-enabling and mode, kernel in the processor * only intended and is this processing of all nuances cover below cannot * * be isolated from the general exception vector before getting before vector exception the general from isolated be * * * - GPRs k0 and k1 are available (no shadow register switches invoked in invoked switches register shadow (no are available and k1 k0 - GPRs * mode) compatibility * SW1..SW0) (HW5..HW0, is IP7..IP0 priority software - The * * base exception 0x200 from Offset Location: * */ IVexception: /* analogous interrupt, a specific processes routine processing Each interrupt * routine processing each Since mode. EIC interrupt in VI or reached to those * know to the context it has line, interrupt particular to a is dedicated * further to look may need routine Each processing was asserted. which line * requests interrupt multiple if the interrupt of actual source the to determine * the performed, task is that line. Once IP on a single together are ORed * ways: of two in one processed may be interrupt * * The interrupt). simply UART a level (e.g., at interrupt - Completely * this type. of an example below is routine SimpleInterrupt * this In interrupts. other re-enabling and state sufficient - By saving * during disabled are interrupts which determines model software case the * single the is either this Typically, interrupt. of this the processing * or some being processed, the interrupt to corresponds bit that StatusIM * Status of other collection * 74microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Interrupts and Exceptions

6.1 Interrupts the interrupt handler. Vectored Inter- Vectored the interrupt handler. to a dedicated handler routine. This handler dedicated to a ed Resource Architecture, Rev. 6.02Architecture, ed Resource 75 mode by adding a priority encoder to prioritize pending /* Clear bits in copy of Status */ of Status in copy bits /* Clear k0 */ bits in ERL, EXL KSU, /* Clear */ mode, to kernel switch mask, /* Modify */ interrupts re-enable /* /* Get restart address */ address restart /* Get */ in memory /* Save */ bit the IM at least include this must /* */ include and may interrupt, current for the /* */ others /* */ be required - may not interrupts /* Disable */ and EPC /* */ and EPC /* */ interrupt the /* Dismiss each interrupt which can be directed mapped to a GPR shadow set for use by use for GPR shadow set mapped to a III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: = 0 = = 1 = 0 = 0 = 1 Save GPRs here, and setup software context */ context software setup here, and Save GPRs  VInt VEIC

IV BEV lVS /* mfc0sw C0_EPC k0, mfc0sw EPCSave k0, C0_Status k0, li StatusSave k0, ~IMbitsToClear k1, */ value Status Get /* */ interrupt for this to clear Im bits /* Get and */ in memory /* Save ins k0, k1 k0, (W_StatusKSU+W_StatusERL+W_StatusEXL) zero, S_StatusEXL, k0, mtc0 C0_Status k0, /* interrupt. device clearing here, including interrupt Process * in running a thread done with may be this environments In some * of scope beyond the is well an environment Such user mode. kernel or * this example. * */ di lwlwmtc0 StatusSave k0, mtc0 EPCSave k1, C0_Status k0, /* Restore GPRs and software state */ C0_EPC k1, eret */ EXL set) (including Status saved /* Get */ value original the /* Restore * to demonstrate the concepts. the to demonstrate * */ Status Config3 IntCt Cause Config3 /* restored must be values the saved processing, interrupt To complete * restarted. code interrupted original and the * */ interrupts interrupts and to generate a vector with to be each interrupt mode also allows theif following all of conditionsrupt in mode are true: effect is • Vectored Interrupt mode builds on the interrupt compatibility Vectored • • • • 6.1.1.2 Interrupt Vectored Mode MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

interrupts at a priority a priority interrupts at is 1, and if interruptsis1, and if are 1 0 7 6 5 4 3 2 , respectively) to providethe d a priority encoder scans the val- priority encoder d a Generated by by Generated IPPCI Vector Number Vector Priority Encoder ged Resource Architecture, Rev. 6.02 entway with the hardware interrupts IntCtl IM2 IM1 IM0 IM6 IM5 IM4 IM3 IM7 and IPTI upt and places the software upt and places bits. If any of these valuesthese bits. If any of and Status and and Status and Status and Status and Status and Status and Status and Status IntCtl IM IP7 IP7 IP2 IP1 IP0 IP6 IP5 IP4 IP3 retedas individualinterrupt hardware requests. The timer Calculated From Calculated Interrupt Request = 0), an interrupt is signaled an ERL HW4HW3 Cause HW2 Cause HW1 Cause HW0 Cause Cause Source Status Interrupt the priority encoder finds the highest priority pending interrupt, it outputs the calculation of the handler for that interrupt, as described below. Thisis the calculation of the handler interrupt, for thatas described below. ity on each hardware interr each hardware ity on combined in an implementation-depend combined . = 0, and = 0, . they are combined indicated by indicated they are combined Type EXL Software SW1 Cause Interrupt bits with the corresponding Status Table 6.3 IP Status Figure 6.1 Cause = 1, Table 6.3Table Mode Interrupt Vectored for Priority Interrupt Relative IE Priority Relative Lowest Priority SW0 Cause Highest Priority Hardware HW5 Cause Status and performance counterand performance interrupts are (with theinterrupt with which In VI interruptInthe mode, six hardware interruptsinterp are The priority order places a relative prior lowerhardware thanall interrupts. When an vector number encoded that is used in in pictorially shown ues in the order shown in enabled ( appropriate relative priority relativeappropriate of theseinterruptThe processor interruptshardware interrupts.of thelogicwith that the each of ANDs 76microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Interrupts and Exceptions

), the timer inter- ), the timer is in effect if all of the in effect is IP1..IP0 the the processor vector Cause here */ here PSS ) to the external interrupt controller, to the external interrupt) controller, ged Resource Architecture, Rev. 6.02 PCI Cause interrupt. interruptEIC mode s, and directly supplying to ller is responsibleprioritizing for all interrupts, including /* Clear KSU, ERL, EXL bits in k0 */ bits in ERL, EXL KSU, /* Clear */ mode, to kernel switch mask, /* Modify */ interrupts re-enable /* /* Clear bits in copy of Status */ of Status in copy bits /* Clear /* Disable interrupts - may not be required */ be required - may not interrupts /* Disable */ and EPC /* */ and EPC /* */ hazard /* Clear */ interrupt the /* Dismiss /* this must include at least the IM bit */ the IM at least include must this /* */ include and may interrupt, current for the /* */ others /* a system-dependent way with other hardware interrupts. The interrupt control- ), and the performance counter interrupt ( request TI = 1 = = 0 = 0 Cause 0 C0_SRSCtl k0, */ sets shadow if changing SRSCtl /* Save = 1  VEIC

IV BEV VS ins (W_StatusKSU+W_StatusERL+W_StatusEXL) zero, S_StatusEXL, k0, mtc0 C0_Status k0, /* target above, write KSU clear only sets, shadow If switching * switch clear EXL, to eret an do execute to EPC, and address * routine jump to and shadow sets, * */ */ interrupt device clearing here, including interrupt Process /* di lwlwmtc0 StatusSave k0, lw EPCSave k1, C0_Status k0, mtc0mtc0 */ EXL set) (including Status saved /* Get SRSCtlSave k0, C0_EPC k1, ehb C0_SRSCtl k0, */ value original the /* Restore eret */ SRSCtl saved /* Get */ sets shadow /* Restore swmfc sw StatusSave k0, liSRSCtlSave k0, */ memory in Save /* ~IMbitsToClear k1, */ interrupt for this to clear Im bits /* Get and to SRSCtl value write new sets, shadow If switching /* k0, k1 k0, /* restored must be values the saved processing, interrupt To complete * restarted. code interrupted original and the * */ Cause Status Config3 IntCtl • External InterruptControllerwayinterrupt the Mode redefinesprocessor theconfigured that logic is to providesup- Theinterrupt contro port for an external interrupt controller. hardware, software, timer, and performancecounter interrupt hardware, software, timer, number (and optionally the priority level) of thehighest priority where it prioritizes these interrupts in where • • rupt request ( In EIC interrupt mode, the processor sends the state of the software interrupt requests ( followingconditions are true: • 6.1.1.3 External Interrupt Controller Mode 78microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Interrupts and Exceptions

6.1 Interrupts when the inter- the when CSS SRSCtl , and interrupts are enabled ) and signals the external registers. This allows the This allowsregisters. codedin value EIC interrupt to determine if the requested IPL IPL is only loadedby the processor IP7..IP2 Status RIPL entations may choose to use the RIPL Status stem environment and needs. stem environment dicates that no interrupt requests are no interrupt requests dicates that Cause Cause ed Resource Architecture, Rev. 6.02Architecture, ed Resource 79 interrupt processing. The vector number that . , which is copiedto EICSS terruptWhen is currently the interruptserviced). being ing (or designing) the interrupt controller to provide the Figure 6.2 ted. Whented. the processor loadsaninterrupt requestinto t (63) RIPL for the interrupt to be serviced. The interrupt s, which are treated as an en an which are treated as s, le based on control status and control on le based (which overlays (which register is not in thismode,register is used and themappingthe of SRSCtl questsand produces the prioritylevel the and vector num- is strictly greater than than strictly greater is iority level, called the RequestedInterrupt Priority Level service routines is located. routines is the interrupt service where to determine VS RIPL ral as a functionof the sy offset along with the RIPL to the processor. along with the RIPL to the processor. offset IntCtl e as the vector number for the processor. number for the processor. the vector e as SRSMap Cause tions available for the vector offset: tions available for the vector offset: = 0) an interruptrequest is signaledpipeline. to the When the processor ERL ) is interpreted as the Interruptwhichis Priorityatprocessor the Level (IPL) range 0..63, inclusive.A value of 0 in range 0..63, upt, the processor compares RIPL with RIPL compares upt, the processor y software visible register. Some implem y software visible register. the request is being serviced. Because serviced. request is being the III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Status IM7..IM2 signaled, it is available to software during signaled, it is available to software during than the current IPL. If RIPL IPL. If than the current Status this is not a requirement. = 0, and EXL Status , it also loads the GPR shadowthealsoloads, it GPR set number into (whichoverlays = 1, 1, = IE RIPL IPL 1.valufirst option The is to treat the RIPL 2. The second option is to send a separate vector number along with the RIPL to the processor. 3. A third optionto sendanentirevector is Status startsinterrupt the exception, it loadsRIPL into ( as the vector number, but as the vector number, In EIC interrupt mode, the external interrupt controller is also responsible for supplying the GPR shadow set number servicingto use when the interrupt.such, the As The vector number is not stored in an currently operatingzero indicating (within a value of no that controller requests service for an interr interrupthas higher priority rupt is serviced. operationThe of EIC interrupt mode is shownpictorially in pending. The values 1..63 represent the lowest (1) to highes controllerthistheon value 6 hardware passes interruptline Cause Status mode. There are several mode. There are several implementation op ler can be a hard-wiredcan logicler block,or be configurab it can interrupt controller to notify it that vectored interrupta GPR to shadow set is done by programm correct GPR shadow set number when an interrupt is reques set number correct GPR shadow when an interrupt exception is when an interrupt exception is the into the core is combined with the EIC passes (RIPL), is a 6-bit(RIPL), is a value encoded the in interruptcontroller to be more specificor more gene externalThe interrupt controllerprioritizes interrupt its re the highestof priorityber interruptto be serviced. The pr MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

6.1 Interrupts which is added to 0x200 to cre- here */ here PSS (the default reset state), the vector reset(the default Field ed Resource Architecture, Rev. 6.02Architecture, ed Resource 81 VS tive subset of the vector numbers and values of - options 1 & 2), a vector number is produced by the inter- to create the interrupt offset, to create the interrupt offset, Value of IntCtl Value VS    /* Clear KSU, ERL, EXL bits in k0 */ bits in ERL, EXL KSU, /* Clear */ interrupts re-enable /* IntCtl ector locations. If this value is zero is this value ector locations. If s to Interrupt Compatibility Mode. A non-zerovalue enables vectoredinter- 0x0280 0x0300 0x0400 0x0600 0x0A00 0x09E0 0x11C0 0x2180 0x4100 0x8000 0x02E0 0x03C0 0x0580 0x0900 0x1000 0x09C0 0x1180 0x2100 0x4000 0x7E00 0x02C0 0x0380 0x0500 0x0800 0x0E00 0x09A0 0x1140 0x2080 0x3F00 0x7C00 0x02A0 0x0340 0x0480 0x0700 0x0C00 0b00001 0b00010 0b00100 0b01000 0b10000 III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: . For VI interrupt. For VI mode,vector theEIC number in0..7,For inclusive. the range is 0123 0x02004 0x02205 0x0200 0x02406 0x0240 0x0200 0x02607 0x0280 0x0280 0x0200 0x02C0 0x0300 0x0300 0x0380 0x0200 0x0400 0x0400 0x0500 0x0600 0x0800 61 62 63 shows the exception vector offset for a representa the exception vector offset shows Table 6.4 Table Interrupts Vectored for Offsets Vector Exception k0, k1, S_StatusIPL, 6 /* Set IPL to RIPL in copy of Status */ copy of RIPL in to IPL 6 /* Set k1, S_StatusIPL, k0, Vector Number Vector field. field. Table 6.4 ins (W_StatusKSU+W_StatusERL+W_StatusEXL) zero, S_StatusEXL, k0, mtc0 C0_Status k0, /* target above, write KSU clear only sets, shadow If switching * switch clear EXL, to eret an do execute to EPC, and address * routine jump to and shadow sets, * */ */ mode, to kernel switch IPL, /* Modify */ interrupt device clearing here, including interrupt Process /* swins StatusSave k0, */ memory in Save /* mfc0sw C0_SRSCtl k1, to SRSCtl value new write sets, shadow If switching /* SRSCtlSave k1, */ sets shadow changing if SRSCtl /* Save VS field specifies the spacing between v VS /* above. for VI mode shown to that identical code is completion The interrupt * */ IntCtl IntCtl For vectored interrupts (in either VI or EIC interruptForor vectored interrupts EIC VI modeeither (in rupt control logic. This number is combined with ate the exception vector offset vector ate the exception interruptmode, the vector isthe number in range 1..63, inclusivebeing (0“noencoding the interrupt”). for The spacing is zero and the processor revert zero is spacing rupts, and the 6.1.2 Interrupts for Vectored Offsets Generation of Exception Vector MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

external interrupt). Whenexternal interrupt). an re the change to the interrupt state to re the change 1 0 IE ged Resource Architecture, Rev. 6.02 state to resume the interrupted instruc- to resume the interrupted state Modified Event Count Event “CP0 Hazards” on page on “CP0 Hazards” . In Release 1 of 105 n occurs. Such events can be generated as a by- generated as can be Such events n occurs. CP0 Register Field(s)  0b00000)) added, andadded, this instruction soft- can be used by VS to the interrupt state (either enabling interrupts which tion handler. The saved state and the address tionof the handler. soft- (IntCtl of exception, and the current state of the processor. of the processor. state and the current of exception, instruction execution (e.g., an execution (e.g., instruction d in the chapter d in the /* Disable interrupts */ interrupts /* Disable hazard */ the /* Clear field is made field visible is by an EHB: IM PerfCnt Control PerfCnt Counter offset for a vectored interrupt is: a vectored interrupt for offset sed the interrupt state change and befo and change state the interrupt sed e, the EHB instruction was register fields may changefields mayregister the conditions underinterruptwhich an is taken. ds is modified by the listed instruction, makes the change to the interrupt terrupts which were previously enabled). urally-definedmethod for boundingof the number instructions which would azard, as describe ops processingsaves sufficient instructions, , and starts a software excep a and starts , struction are made visible by an EHB: are struction EI, DIEI, Status IE MTC0MTC0 Status Cause IM, IPL,ERL, EXL, IE IP MTC0 MTC0 Table 6.5Table EHB by Visible Made Changes State Interrupt Instruction(s) CP0 Register Written lists the CP0 register fields which can cause a change lists the CP0 register di mfc0ins C0_Status k0, mtc0 1 zero, S_StatusIM4, k0, ehb C0_Status k0, */ instruction this later than seen no is state the interrupt Change to /* */ IM field 4 of the bit /* Clear ehb */ instruction this later than seen no is state the interrupt Change to /* */ the register /* Re-write hazard */ the /* Clear 0x200 + (vectorNumber  + (vectorNumber  0x200 vectorOffset An EHB, executed after one of these fiel after one executed An EHB, state visibleinstruction than the no later followingEHB. the change to the Cause following example, a the In were previously disableddisabling or in ware to clear the hazard. clear to ware Table 6.5 the Architecture, there was no architectnothe Architecture, was there be after the instruction executed which cau was seen. In Release 2 of the Architectur Software writes to certain 0 coprocessor 0 (CP0) h coprocessor This creates a Normal executionwhen an exceptio of instructions may be interrupted Similarly, the effects of an DI in the effects Similarly, product ofproduct instruction execution(e.g., an integer overflow instruction caused by an add TLB missor caused by a a loadinstruction), or byaneventdirectly not related to exception occurs, the processor st Mode Kernel enters tion stream, ware exceptionhandlerfunctiontheof both type are a The general equation for the exception vector equation general The 6.1.2.1 Hazardsand Software the Interrupt System 82microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers 6.2 Exceptions Interrupts and Exceptions

Reset Type 6.2 Exceptions Debug Debug Debug Debug Debug Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Asynchronous e other exceptions, on was asserted. occur on the same the occur on sserted. Prioritized sserted. Prioritized ed Resource Architecture, Rev. 6.02Architecture, ed Resource 83 teger overflow, trap, overflow, teger ocessor 2 exception. ocessor 2 highest to lowest. highest was one when the when the excep- was one went to zero. went to that one can into single-step EXL EXL le Exception takes priority over was illegal: Coprocessor Unus- leted because it was not allowed allowed it was not because leted match) conditi rted to the processor rted to the valid TLB entry which the XI bit had TLB entry which valid d. Prioritized abov d. Prioritized eak condition was asserted. condition eak Description Brk Brk or DINT) was asserted. eak on load/store (address match only) or a match only) (address load/store eak on ception occurred: In exceptions to allow break on exceptions illegal instruc- , floating-point, copr break condition was a ion. If both exceptions both ion. If ncy was detected by the processor. tive priority of each, priority tive zero in the TLB entry mapping the address refer- address the mapping entry TLB the in zero was asserted to the processor. ception, deferred because because ception, deferred tion fetch matched a rd-aligned address was loaded into PC. loaded into address was rd-aligned t signal was asserted to the processor the to asserted was signal t miss on an instruction occurred fetch. rror occurred on an instruction fetch. an instruction occurred on rror instruction could comp instruction not be Table 6.6Table Exceptions Priority of n imprecise EJTAG data br n imprecise EJTAG III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: The Rese The A watch address match was detected on an instruction fetch. Priori- fetch. instruction an on detected was match address watch A An instruction-based ex instruction-based An An enabled interrupt occurred. An enabled tion was detected,was tion was asserted after including asynchronous exceptions, so exceptions, asynchronous including interrupt handlers. asynchronous) (or other An EJTAG instruction instruction EJTAG An A precise EJTAG data br precise A EJTAG A watch ex watch A An EJTAG interrupt interrupt (Ejtag An EJTAG fetch above instruction tion addresses. tized above instruction tized above fetch exceptions to allow watch on illegal instruction addresses. enced by an instruction fetch. set. Unusab Coprocessor the instruction, Exception. the Reserved Instruction store (address+data on break data able, Reserved able, Reserved Instruct system call, breakpoint data illegal on break to allow exceptions fetch data above Prioritized addresses. access to the required resources, or required resources, access to the An instruc An An internal inconsiste internal An An EJTAG SDBBP instruction was instruction executed. SDBBP An EJTAG The Cold Reset signal was asse signal Cold Reset The occurre Single Step An EJTAG lists all possible exceptions, and the rela the and exceptions, lists all possible Exception Table 6.6 Interrupt Watch Deferred Debug Interrupt Data BreakImprecise Debug Check Machine A Debug Instruction Break Nonmaskable Interrupt (NMI) Interrupt Nonmaskable NMI signal The Reset Soft Reset Debug Single Step Watch - Instruction fetch Instruction - Watch Address Address Error - fetchInstruction fetch Instruction - Refill TLB non-wo A TLB Invalid - Instruction fetchTLB A Execute-Inhibit TLB valid bit was The Precise Debug Data Break Cache Error Cache Error - Instruction fetch fetchBus Error - Instruction SDBBP fetch. cache A on error occurred an instruction bus A e Instruction Validity ExceptionsInstruction Validity An Execution Exception 6.2.1 Exception Priority MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

or Type Synchronous Synchronous Asynchronous . EJTAG Debug excep- . EJTAG e table above considers e table there is a relative priority priority is a relative there ly to instruction execution. execution. ly to instruction to allow watch to allow watch ged Resource Architecture, Rev. 6.02 her exceptions because of the of her exceptions because ously to instruction execution. instruction ously to lt of instruction execution, and execution, instruction lt of exceptions as between occurring 0xBFC0.0000 explains of each excep- the characteristics nously to instruction execution. to the previous instruction, or the relative iority to guarantee that the processor can can the processor that to guarantee iority tion that caused the exception. These excep- the that caused tion rity than synchronous exceptions mainly for mainly for rity than synchronous exceptions Table 6.8 Table ion. The ordering of th of The ordering ion. entry mapping the address refer- presence of other exceptions, both asynchro- of other presence entry mapping the address refer- address mapping the entry ion execution, and is instruction execution, of as a result ta fetch exceptions if the ProbTrap bit is zero or zerois one, bit if the ProbTrap 0xFF20.0200 Characteristics Description s detected on the address referenced by referenced s detected a on the address d a valid TLB entry whose RI is bit set. priority with respect to ot to respect with priority w other types of exceptions, but s referenced, by a load s referenced, by a load or store instruction d on a load or store data reference bove other synchronous exceptions to allow entry exceptions to Debug synchronous bove other exception that occurs asynchron d on a load or store data reference exception that occurs asynchronous ug exception that occurs as a resu a as ug exception that occurs ce. If one thinks of asynchronous exception that occurs asynchro ns are always vectored to location vectored to are always ns ligned address, or an address that was inaccessible in the cur- in the inaccessible was that address an or address, ligned lid bit was zero in the in the TLB zero lid bit was dirty bit was zero in the TLB An una An A TLB miss occurred on a data access on a data occurred A TLB miss A watch address match wa match address watch A load or store. Prioritized above da store. Prioritized or load illegal data addresses. on rent processor mode wa processor rent store instruction or by a load enced enced by a store instruction by a store enced The va A data read access matche A A bus error occurre A cache error occurre describes the typeof exception. , or to location0xBFC0.0480, or Table 6.7Table Characteristics Type Exception Table 6.6Table (Continued) of Exceptions Priority Denotes any other exception that occurs any other Denotes Denotes any other type of type other any Denotes of synchronous exceptions with each other. exceptions with synchronous of Mode, even in the presence of other exceptions. to the respect instruc with precisely reported tions tend to be prioritized belo highest priority relative highest priority to the next instruct way. second the in them These the exception. caused that to the instruction with respect precisely is reported prioritized a exceptions are instructions, they are either the lowest priority the lowest either are they instructions, These exceptions always have the highest pr highest the have always exceptions These always be placed in a runnable state. placed in a runnable be always high exceptions have very These desire to enter Debug Mode, even in the desire to enter nous and synchronous. These exceptions are shown with higher prio shown with higher exceptions are These notational convenien Table 6.7 Exception Exception Type Synchronous Synchronous Debug deb an EJTAG Denotes Asynchronous Asynchronous Reset a reset-type Denotes Asynchronous Asynchronous Debug debug an EJTAG Denotes Asynchronous respectively, in the EJTAG_Control_register. in the EJTAG_Control_register. respectively, The Reset, Soft Reset, and NMI exceptio Reset, and NMI Reset, Soft The tions are vectored to location are vectored to location tions The “Type” column of The “Type” tion type. Watch access - Data Watch Address error - Data access error Address TLB Read-Inhibit TLB Refill - access Data - Refill TLB access Data Invalid - TLB TLB Modified - Data access Data - Modified TLB The Cache Error Cache Error - Data access Bus Error Bus Error - Data access 6.2.2 Locations Exception Vector 84microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Interrupts and Exceptions

reg- reg- bit in the the in bit equals 0. 0. equals Status EBase IV BEV 6.2 Exceptions contains zeros in Status 15..12 is 0. is function of the state that VS bit is setin the gives the offset from the from gives the offset lease 1 of the architecture in lease 1 of the architecture EBase tuation can only occur when a IntCtl BEV 0xBFC0.0200 0xBFC0.0200 or base address. In Release 1 of the In Release 1 or base address. Table 6.4 er than the general exception vector. vector. exception the general er than BEV ed Resource Architecture, Rev. 6.02Architecture, ed Resource 85 itecture (and subsequent releases), software is releases), (and subsequent itecture 0x000 

Status Vector Offset Vector ssible vector addresses as a as vector addresses ssible 0xBFC0.0000 0xBFC0.0480 0xFF20.0200 the vector address value assumes the assumes that the vector address value 28 12 have the t in the vector offset. This si in the vector offset. t ss as a function of the exception. Note that the Note the exception. a function of ss as have the EBase = 1. For implementations of Re register for exceptions that register for occur when  0x000  IV 31 30 01 31 30 1

 0x000 were 0. were 31 12 EBase VS Cause EBase 0x8000.0000 0xA000.0000 31 30 not changed notitsfrom state reset and that EBase IntCtl function of the exception and whether the the exception and function of if this condition if not is met. EBase dedicated exception vector offset, rath vector offset, dedicated exception = 0 and For Release 2 of the architecture: For Release 1 of the architecture: fixed value 0b10 fixed For Release 1 of the architecture: For Release 2 of the architecture: Note that EBase fixed value 0b10 fixed Note that BEV = 0 III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Table 6.9Table Offsets Exception Vector Status Exception UNDEFINED FFF is generatedFFF whenwith an interrupt VI occurs or EIC interrupt modeenabled. The ease 2 of the Architecture (and subsequent releases), subsequent (and Architecture of the 2 ease Table 6.8Table Addresses Base Vector Exception tion. To avoid complexity in the table, tion. To base address was fixed. In Release 2 of the arch was fixed. In address base TLB Refill, EXL Exception = 1, the vector offset is as = if the 1, vector offset gives the offsets from the vector base addre from the base vector the gives offsets Reset, NMI IV combines these two tables into one that contains all po combines these two gives the vector base address as a as the vector base address gives Cause register causes Interrupts to use a to use Interrupts causes register Table 6.9 Other EJTAG Debug (with ProbTrap = 0 in Debug (with ProbTrap EJTAG the EJTAG_Control_register) = 1 in Debug (with ProbTrap EJTAG the EJTAG_Control_register) Cache Error Reset, Soft

which Table 6.10 architecture, the vector architecture, via the base address specify the vector allowed to Cause mbination of a vector offset and a vect and a Addresses for offset are a all other exceptions of a vector combination In Release 2 of the Architecture (and In Release 2 of the Architecture releases), software must subsequent guarantee that Table 6.8 ister, as implemented in Release 2 devices, is ister, ister. ister. vector offset greater than 0x greater than vector offset operation of the processor is operationis processor of the all bit positions less thanorto equal the most significant bi Forimplementations Rel of can affect the vector selec can affect base address in the case where base address in the case MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

= BEV = 0 VS Status ). The value loaded Vector ASE, and whether the 0xBFC0.0300 0x8000.0180 0x8000.0200 0xBFC0.0380 0xBFC0.0400 0x8000.0180 0xBFC0.0380 0xA000.0100 0xBFC0.0380 0xBFC0.0000 0xBFC0.0480 0xFF20.0200 0x8000.0000 0x8000.0180 0xBFC0.0200 shows the value stored in shows the value = 0) PC at which executionPC at which will be BEV assumes that EBase retains its its assumes thatEBase retains reset state and thatIntCtl reset state For Release 2 Implementations, ged Resource Architecture, Rev. 6.02 Table 6.11 Table ease 2 of the Architecture if g exceptions, which have their own spe- Status Table 9.52 onTable 9.52 page 209 x x x x x x x x x 0x100 0x180 EJTAG EJTAG Vector Offset Vector ProbTrap r implements the MIPS16 register (see register (see IV (In Release 2 0x200 implementa- (In Release register is loadedwith the interrupt table when interrupt table tions, this is the base of tions, this is the base of the vectored Cause 0 1 0 1 x x x x x EPC Cause . For implementations of Rel ‘x’ denotes don’t care don’t ‘x’ denotes ns have the same basic processing flow: processing basic same the have ns EPC EXL 0 0 0 0 1 x x x x set, NMI, cache error, and EJTAG Debu and EJTAG set, NMI, cache error, Table 6.10Table Vectors Exception = 1 IV Status register is zero, the Exception Cause Table 6.9Table (Continued) Offsets Vector Exception Status bit is set appropriately in the is bit registers, including BEV 0 0 1 1 1 0 1 1 0 BD Reset, Soft Reset, NMIReset None (Uses Address) Base General Exception General Interrupt, Cache error registerdependent is processothe on whether Status bit in the EPC EXL restarted and the into the instructionjump or delaybranch is in thehas which slot of a delay slots. each of the CP0 PC •If the the •If cial processing as described below, exceptio cial processing as described below, With the exception of Reset, Soft Re With

Exception 6.2.3 General Exception Processing Interrupt Interrupt Interrupt Interrupt All others All others Cache Error Cache Error Reset, Soft Reset, NMIReset, Soft Reset, DebugEJTAG DebugEJTAG xTLB RefillTLB Refill xTLB Refill x xTLB Refill 0 x 0 x x 1 0 x 1 x x 0 x 0 x 1 x x x x 86microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Interrupts and Exceptions

6.2 Exceptions loaded from the appropri- from the loaded bitchanged is not inthe register unless it wishes to registerchanged. is not BD es appropriateexception. to theThe Cause in the 32-bit ISA Mode), SRSCtl bit ed Resource Architecture, Rev. 6.02Architecture, ed Resource 87 bit in the the in bit in EPC/ErrorEPC/DEPC BD ISA Mode bit field, and the CSS value is value the CSS field, and PSS ISA Mode register is not loaded and the and loaded not is register /* PC of instruction */ of instruction /* PC /* Assume exception, Release 2 only */ Release exception, /* Assume EPC with the ISA MIPS16 Mode the and PC-4 with the combined registers are loaded with registers the valu nor SRSCtl are modified */ modified are nor SRSCtl Release 2 of the Architecture, the the of the Architecture, 2 Release BD Cause ESS Software need not look at the register. on that actually caused the exception. on that actually register is copied to the register is III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Delay Slot?Delay stored Value register is set, the register is set, In Branch/Jump Status SRSCtl represents the restart address for the exceptionnot and need be modified by exception d at the exception vector. exception d at the fields of the of the fields Status is 1, all exceptions go through the general exception vector */ vector exception general the go through 1, all exceptions is  1  0 EPC EXL BD BD = 1 then ExcCode EXL field in the NoNo No Yes Address of the instruction of Address jump the branch or instruction (PC-4) bit in the YesYes No Yesinstruction, combined of the the address bits of 31 Upper in instruction (PC-2 jump or the branch bits of Upper 31 EPC  restartPC EPC Cause vectorOffset  0x000 vectorOffset restartPC/* PC of branch/jump */ of branch/jump PC  restartPC/* EPC Cause bitin is set the Table 6.11Table in EPC, ErrorEPC, or Stored DEPC on an Exception Value MIPS16 , and register. For implementationsof register. CSS EXL CE EXL else endif */ of exception type of the a function as vector offsets Compute /*  SRSCtl NewShadowSet if ExceptionType = TLBRefill then = TLBRefill ExceptionType if then = Interrupt) (ExceptionType elseif vectorOffset  0x180 vectorOffset then if InstructionInBranchDelaySlot Implemented? field is loaded, fieldnot but is defined, for any exceptionthan type a coprocessor other unusable exception. if Status /* If Status CE 0, the Cause ate source. If the else /* and neither EPC nor Cause EPC nor and neither /* handler software in the normal case. • The identify the address of the instructi Note that individual exception types may load additional information into other registers. This is noted in the descrip- type below. tion of each exception Operation: The value loaded into value loaded The • The is starte processor • The . MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

= 0) then = BEV  0b00000)) VS ) ged Resource Architecture, Rev. 6.02 29..0 (IntCtl = 0) then */ = 0) 4 0) and (Status 0)  VS  HSS 4+3..IPL  = 0) then = 0) forces the base to be in kseg0 or kseg1 */ or kseg1 in kseg0 be base to the forces VS EICSS IPL + vectorOffset RIPL 29..0 31..30 = 1) or (IntCtl = 1)  0x000 2) and (SRSCtl 2) and BEV  2 then  /* No carry between bits 29 and 30 */ 29 and bits between carry /* No = 1 then = 0) then */ = 0) then 31..12 CSS IV VEIC = 1) or (IntCtl = 1) or  (vectorBase = 1 then */ = 1 then VecNum  EIC_VecNum_Signal VecNum VecNum  Cause VecNum BEV EBase 0x8000.0000 EXL have zeros in each bit position less than or */ less than bit position in each have zeros NewShadowSet SRSCtl = 0) then vectorOffset  EIC_VectorOffset_Signal vectorOffset  + (VecNum  0x200 vectorOffset elseif (EIC_option2) elseif endif  SRSCtl NewShadowSet  VIntPriorityEncoder() VecNum  SRSMap NewShadowSet if (EIC_option1) 0xBFC0.0200 IV 31..30   vectorOffset  0x200 vectorOffset if Config3 endif if (EIC_option3) else else endif 15..12 CSS PSS = 1 then 1  ExceptionType vectorOffset  0x180 vectorOffset if (Status else endif /* if (Status /* if endif BEV  vectorBase  vectorBase else SRSCtl if (Cause SRSCtl  vectorBase /* The fixed value of EBase value of The fixed /* endif /* if (Cause /* if endif  FaultingCoprocessorNumber EXL CE ExcCode endif endif /* elseif (ExceptionType = Interrupt) then */ = Interrupt) (ExceptionType /* elseif endif */ of implementation for an set information shadow Update the /* /* Release 2 of the architecture */ if (ArchitectureRevision else endif vectorBase  vectorBase if ArchitectureRevision if ArchitectureRevision  vectorBase endif /* if Status /* if endif Cause */ address base the vector Calculate /* if Status Cause /* equal to the most significant bit position of the vector offset */ vector of the position bit significant the most equal to /* PC endif */ Vector vectorOffset. and vectorBase sum of PC is the Exception /* */ require only), interrupts or EIC > 0xFFF (vectored offsets /* /* that EBase Status else 88microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Interrupts and Exceptions

bitis register ProbTrap 6.2 Exceptions ErrorEPC instructions from ing aborting state machines, ing aborting state machines, Random register is deprecated in . Note that thisvalue mayor may to a specified state. to nditions is met. Refer to the EJTAG EJTAG the to Refer met. is nditions if the 0200 if the 0xFF20 ich can execute it ; ing registers have defined state: ed Resource Architecture, Rev. 6.02Architecture, ed Resource 89 Table 6.11 Table reset initialization,includ e result of powere result being of appliedbecauseprocessorthe to register are initialized register are serted to the processor. This exception is not maskable. processor. serted to the Status register interrupt enables are cleared. are interrupt enables register EJTAG_Control_register some implementations, loaded the value into mber of TLB entries minus one. The mber of TLB entries registers are initialized withstate. boot their # This bit becomes reserved in Release 6 Release in reserved bit becomes # This # 1KB page support implemented page support # 1KB implemented page support # 1KB implemented page support # 1KB one of a number of EJTAG-related co one of a number of EJTAG-related fields of the fields of a Reset Exception, only the follow only a Reset Exception, Config3

y placing the processor in a state in wh a state in in processor the y placing ERL , and III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: bit isbit zero in the Performance Counter , and NMI , Config2 , ProbTrap s of this exception. of s . 0000 0xBFC0 SR ,  0  0 1  0 register is loaded with the restart PC, as described in the restart PC, as loaded with is register TS register is initialized to the nu , Config1 ESP

 , MaskX register is initialized to zero. 0  VPN2X BEV RP BEV , register enables and register enables ErrorEPC Wired Config RP Random 0xBFC0 0000) Status TLBEntries - 1  TLBEntries Random PageMask Watch Release 6. may notmay be predictable Reset or Soft Reset Exception. on either a PageGrain  0 Wired  0 HWREna EntryHi Status PCmay have nota valid valuein that case. In not be predictable was taken as not be predictable if the Exception Reset th • • The A Reset Exception occurs when the Cold Reset signal is as signal is Reset when the Cold occurs A Reset Exception When a Reset Exception occurs, the processor performs a full processor performs a Reset Exception occurs, the When An EJTAG Debug Exception occurs when An EJTAG Entry Vector Used Entry Vector 0xBFC0 0480 if the Specificationdetail for establishing critical and generall state, • The • The Operation • loaded with is PC ExcCode Value Register Cause None Saved Additional State None Used Entry Vector Reset ( • The • The uncached, unmapped address space. On space. uncached, unmapped address one. 6.2.5 Reset Exception 6.2.4 Debug Exception EJTAG MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

Reset Exception is typically ssor may reset the same state is exception is not maskable. . to a specified state. to other processor state may be incon- may state other processor ged Resource Architecture, Rev. 6.02 Table 6.11 tions is in actual use. The use. is in actual tions a subset of the full reset initialization.Although a Soft register are initialized register are sserted to the processor. Th to the processor. sserted l problem. As such, the proce the As such, l problem. n of any state saved by software mayn of any state different. software be very saved by followingestablished state is onReset a Soft Exception: Status address space. Since bus, Since space. tions from unmapped address uncached, register register interrupt enables are cleared. # Suggested - see Config register description register - see Config # Suggested # This bit becomes reserved in Release 6 Release in reserved becomes bit # This # For all implemented Watch registers all implemented # For Watch registers all implemented # For Watch registers all implemented # For pted, portions of the cache, memory, or cache, memory, pted, portions of the fields of the fields of ERL rily change the state of the processor, it may be forced to do so in order to place to forced to do so in order may be it of the processor, state rily change the Performance Counter , and  0 registers PerfCnt all implemented # For IE NMI  0 ,

0xBFC0 0000. 0xBFC0 SR ,  0  0  0 0 1 HighestImplementedShadowSet 0 0 0

register is loaded with the restart PC, as described in loaded with the restart PC, as is register TS I R W ,        0 2  0   0  0 BEV NMI ERL VS HSS ESS PSS CSS K0 TS SR , DC ExceptionBase register enables and ErrorEPC RP restartPC # PC of branch/jump # PC of restartPC  ErrorEPC instruction # PC of restartPC  ErrorEPC 0xBFC0 0000  0xBFC0 Status IntCtl SRSCtl SRSCtl SRSCtl  0 SRSMap Cause EBase SRSCtl  ConfigurationState Config1  ConfigurationState Config2  ConfigurationState Config3 WatchLo[n] Status Status Watch if InstructionInBranchDelaySlot then if InstructionInBranchDelaySlot else endif PC Status Config  ConfigurationState Config Config WatchLo[n] WatchLo[n] PerfCnt.Control[n] • sistent. Reset Excep between the Reset and Soft The primary difference When a SoftReset Exception occurs, the processor performs may be interru or other operations cache, A Soft Reset Exception occurs when the Reset signal is a is when the Reset signal A Soft Reset Exception occurs Reset Exception does not unnecessa Reset Exception does not instruc a state in which it can execute the processor in used to initialize the processor on power-up, whileSoftthe Reset Exception typicallyused to initializefrom non- is a recover used topower-up, on the processor The semantic is provided to allow boot difference software to save critical coprocessor 0 responsive (hung) processor. or other register state to assist in debugging the potentia interpretatio but the signal is asserted, reset either when Inaddition toanyhardware initialization required, the • The • loaded with is PC Register ExcCode Value Register Cause None • The 6.2.6 Reset Exception Soft 90microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Interrupts and Exceptions

6.2 Exceptions zation. The state of the cache, the following exceptions: the following . to a specified state. to a rdware initiali ed Resource Architecture, Rev. 6.02Architecture, ed Resource 91 Table 6.11 is asserted to the processor. to the is asserted are initialized register Status # Suggested - see Config register description register - see Config # Suggested 6 Release in reserved bit becomes # This 6 Release in reserved bit becomes # This # 1KB page support implemented page support # 1KB implemented page support # 1KB implemented page support # 1KB # For all implemented Watch registers all implemented # For Watch registers all implemented # For Watch registers all implemented # For consistentand with all regist ers are preserved, fields fields of the III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: on occurs when the NMI signal the NMI when on occurs ERL  0 registers PerfCnt all implemented # For daries, so does not do any daries, reset or other ha IE , and NMI 0xBFC0 0000. 0xBFC0 ,  0  0  0  0  0 0 1 1  0

register is loaded with restart PC, as described in PC, loaded with restart is register SR I R W , ESP    MaskX 2  0  0   1 TS VPN2X , SR NMI ERL K0 RP BEV TS ErrorEPC BEV restartPC # PC of branch/jump # PC of restartPC  ErrorEPC instruction # PC of restartPC  ErrorEPC 0xBFC0 0000  0xBFC0 0xBFC0 0000) 0xBFC0 0000) Status WatchLo[n] Status Status Status Status Status if InstructionInBranchDelaySlot then if InstructionInBranchDelaySlot else endif PC PageMask PageGrain EntryHi Config WatchLo[n] WatchLo[n] PerfCnt.Control[n] • The tion because it is not maskable. An NMI as an exception because it is not maskable. An NMI more correctly described Although described as an interrupt, it is occurs only at instruction boun is state other processor and memory, • The A nonmaskable interruptexcepti Operation Additional State Saved Additional State None Used Entry Vector Reset ( • loaded with is PC Register ExcCode Value Register Cause None Saved Additional State None Used Entry Vector Reset ( 6.2.7 (NMI) Exception Non Maskable Interrupt MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

register field is used to dis- register field is used MCCause ged Resource Architecture, Rev. 6.02 PageGrain feature is supported and the methodPage Dual is also scriptions above. bit set and the second PTE accessed has PTEVld entry an Addressis generated is implementation-depen-an Error a TLB-based MMU.If the Hardware Page Table Walker Walker Table the Hardware Page a TLB-based MMU.If # This bit becomes reserved in Release 6 Release in reserved becomes bit # This of the MIPSthe Architecture of documentation set. ocessor detects an internal inconsistency. exception. See the de See the exception. ) Volume I-A under the following circumstances: a machine check exception: a machine check 1 1 1    0   0 Table 9.53 onpage212 BEV TS SR NMI ERL restartPC # PC of branch/jump # PC of restartPC  ErrorEPC instruction # PC of restartPC  ErrorEPC 0xBFC0 0000  0xBFC0 Status then if InstructionInBranchDelaySlot else endif PC Status Status Status Status supported, and if the first accessed has PTE entry PTEVld bit clear. feature is implementedthe andHuge Directory-level page An address error exception occurs An address • An instructionisanaddress fetched fromaligned that is not onwordboundary. a • A loador store word instructionis executed in whichis not the address alignedword on a boundary. • A loador store halfword instructionisexecuted in whichis not the address alignedhalfwordboundary. on a •Mode or Supervisor Mode. User space from a kernel address to reference is made A •from User Mode. space a supervisor address to reference is made A supports misalignedRelease 6 load/store handling.Whether dent, as described in Appendix B of A machine check exception occurs when the pr occurs when the A machine check exception ExcCode Value Register Cause MCheck (See The followingThe conditions cause • Detection of multiple matchingentries TLB in the in Saved Additional State the caused condition that on the Depends Operation If there are multiple causes for the machine check exception, then the for the If there are multiple causes tinguishwhich condition caused theexception. Used Entry Vector 0x180)General exception vector (offset 6.2.9 Address Error Exception 6.2.8 Machine Check Exception 92microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Interrupts and Exceptions

6.2 Exceptions reg- field field con- field Context ed Resource Architecture, Rev. 6.02Architecture, ed Resource 93 VirtualIndex BadVPN2 Value of the failing failing address; of the the of the reference that missed. that reference the of failing address UNPREDICTABLE UNPREDICTABLE 31 13 register are loaded withhigh- the point at the unaligned instruction address. bit is clear, then the the then is clear, bit bit is set, then the bits of the of the failing address the failing of field contains VA contains field CTXTC CTXTC 31 13 BadVAddr ContextConfig from the case in which an entry matches which in from the case distinct is this that Note register. VPN2 and Config3 Config3 Register State order bits of the that missed. order virtual address If ister corresponding to the set bits of the the of the set bits to corresponding ister of the ASID field contains the ASID contains ASID field tains VA Status EPC VPN2 VPN2 case a TLB Invalid exception occurs. III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: . . EntryHi EntryLo0EntryLo1 UNPREDICTABLE UNPREDICTABLE BadVAddr Context occurs in a TLB-based MMU when no TLB entry matches a reference to a mapped address to no TLB entrya reference matches MMU when a TLB-based occurs in Register State Value bit is zero in the the in zero is bit EntryHi The BadVAddrContext Failing address If . Therefore, both . Therefore, EXL Table 9.53 onpage212 Table 9.53 onpage212 but has the valid in whichbit off, ExcCode Value Register Cause fetch an instruction load or was a Reference TLBL: store TLBS: Reference was a See Additional State Saved Additional State A TLB Refill exceptionA TLB Refill space and the Note that in the case of an instruction fetch that is not aligned on a word boundary, the PC is updatedPC is the before con- the Notethat an instructioncase of the in isnotfetch that aligned on a word boundary, dition is detected Entry Vector Used Entry Vector 0x180)General exception vector (offset Additional State Saved Additional State Register ExcCode Value Register Cause or an instruction fetch a load AdEL: Reference was a store AdES: Reference was See 6.2.10 TLB Refill Exception MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

XI reg- field field con- field ged Resource Architecture, Rev. 6.02 Context reference matches a TLB entry whose reference matches ction fetch matches a TLB entry whose entry whose a TLB matches ction fetch VirtualIndex BadVPN2 of the failing failing address; of the the the reference that missed. that the reference 31 13 s are a special case and are not affected by the RI bit. by the not affected are and special case s are a Value at the time of = 1 exception register are loaded withhigh- the EXL bit is implemented withinisthis the TLB and enabled, is bit is clear, then the the then is clear, bit bit is set, then the bits of the XI = 0 at the time of exception. = 0 at of the failing address the failing of Status EXL field contains VA contains field CTXTC CTXTC 31 13 ContextConfig field contains the ASID of field contains the virtualthea memory address of load VPN2 Status Config3 Config3 order bits of the that missed. order virtual address If ister corresponding to the set bits of the the the set bits of to corresponding ister of the ASID tains VA bit. MIPS16 PC-relative load (offset 0x180) (offset if bit. . RIE XIE Register State Value Register State EntryHi The BadVAddrContext Failing address If EntryLo0EntryLo1 UNPREDICTABLE UNPREDICTABLE EntryLo0EntryLo1 UNPREDICTABLE UNPREDICTABLE == 0 TLBL == 1 TLBXI PageGrain PageGrain IEC IEC Table 9.53 onpage212 PageGrain PageGrain denoted by the • exception vector General Register ExcCode Value Register Cause if Entry Vector Used Entry Vector 0x180)General exception vector (offset Additional State Saved Additional State if See An Read-Inhibit exception occurs when An Read-Inhibit exception occurs RI bit is set. ThisRI bit exception is only typecan occur RI bit is implemented if the withinenabled,and is the TLB this is denoted by the An Execute-Inhibit exception occurs when the virtual occurs address of exception An Execute-Inhibit an instru Entry Vector Used Entry Vector • TLB Refill vector0x000) if (offset bit is set. This exceptionThis set. is bitif type can only the occur 6.2.12 Read-Inhibit Exception 6.2.11 Exception Execute-Inhibit 94microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Interrupts and Exceptions

bit is one EXL 6.2 Exceptions reg- field field con- field Context bit is clear, then this exception also then bit is clear, IEC ed Resource Architecture, Rev. 6.02Architecture, ed Resource 95 VirtualIndex BadVPN2 to a mapped address space and the to a mapped address space of the failing failing address; of the the ception, in the sense that both use the general excep- that both use in the sense ception, of the reference that missed. that reference the of PageGrain 31 13 e loads are a special case and are not affected by the RI by not affected are case and a special are e loads The only wayThe only to distinguishisprob- bycases these two t set on a memory load reference, or with the XI bit set set bit XI the with or reference, load a memory on set t Value register are loaded withhigh- the bit is clear, then the the then is clear, bit bit is set, then the bits of the of the failing address the failing of field contains VA contains field CTXTC CTXTC 31 13 ContextConfig VPN2 Config3 Config3 order bits of the that missed. order virtual address If ister corresponding to the set bits of the the the set bits of to corresponding ister of the ASID field contains the ASID contains ASID field tains VA III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: no TLB entry matches a reference TLB entry matches no when a TLB entry matches a reference to a mapped address space, but the matched space, a reference to a mapped address TLB entry matches when a emented within the TLB and the . . Register State EntryHi The EntryLo0EntryLo1 UNPREDICTABLE UNPREDICTABLE BadVAddrContext Failing address If == 1 TLBRI == 0 TLBL IEC IEC register is indistinguishablea TLBInvalid from Ex Status Table 9.53 onpage212 Table 9.52 onpage209 PageGrain PageGrain Entry Vector Used Entry Vector 0x180)General exception vector (offset See Additional State Saved Additional State if in the tion vector and supplyTLBS. an ExcCodeof value TLBL or theingmatching for TLB a entry (using TLBP). bits are impl the RI and XI If A TLB invalid exception occurs exception A TLB invalid thebit validentry has off. in which that the condition Note Register ExcCode Value Register Cause if occurs if a valid,foundif a matching withTLB entry is occurs the RI bi on an instructionmemory fetch PC-relativreference. MIPS16 bit. ExcCode Value Register Cause fetch an instruction load or Reference was a TLBL: store TLBS: Reference was a See 6.2.13 TLB Invalid Exception MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

reg- reg- field field field con- field field con- field ged Resource Architecture, Rev. 6.02 Context Context VirtualIndex VirtualIndex BadVPN2 BadVPN2 of the failing failing address; of the the of the failing failing address; the of the of the reference that missed. that reference the of of the reference that missed. that reference the of 31 13 31 13 Value register are loaded withhigh- the register are loaded withhigh- the bit is clear, then the the then is clear, bit bit is clear, then the the then is clear, bit bit is set, then the bits of the bit is set, then the bits of the of the failing address the failing of of the failing address failing the of field contains VA contains field field contains VA contains field CTXTC CTXTC CTXTC CTXTC reference to a mapped when the matching address TLB entry is valid, 31 13 31 13 ContextConfig ContextConfig VPN2 VPN2 Config3 Config3 Config3 Config3 order bits of the that missed. address order virtual If bits of the that missed. order virtual address If ister corresponding to the set bits of the the of the set bits to corresponding ister ister corresponding to the set bits of the the the set bits of to corresponding ister of the of the ASID field contains the ASID contains ASID field ASID field contains the ASID contains ASID field tains VA tains VA ) tion occurs ona store Register State Value Register State EntryHi The BadVAddrContext Failing address If EntryLo0EntryLo1 UNPREDICTABLE UNPREDICTABLE EntryHi The EntryLo0EntryLo1 UNPREDICTABLE UNPREDICTABLE BadVAddrContext address Failing If bit is zero, indicatingnotthe that writable. page is D A TLB modified excep A TLB modified Entry Vector Used Entry Vector 0x180)General exception vector (offset Additional State Saved Additional State but the entry’s but the entry’s ExcCode Value Register Cause Mod (See Table 9.52 on page209 Saved Additional State 6.2.14 TLB Modified Exception 96microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Interrupts and Exceptions

6.2 Exceptions tected during bus transactions tected request (due to a cache miss or an unca- request (due to a cache ed Resource Architecture, Rev. 6.02Architecture, ed Resource 97 ference detects a cache tag or data error, or a parity or or a parity or error, data a cache tag or ference detects r. Notedeerrors that parity r. and bit 29 forced to a 1 puts the */ to a 1 puts forced bit 29 and  0x100 31..30 28..12 2 then Register StateRegister Value  EBase CacheErrErrorEPC state Error Restart PC rminated in an erro on, data, or prefetch access makes a bus a makes access on, data, or prefetch    III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: tions, not bus error exceptions. 31..30 = 1 then EBase 0xA000 0000 + 0x100 0000 + 0xA000 1 BEV  0xBFC0 0200 + 0x100 0200 + 0xBFC0 /* vector in kseg1 */ vector in /* PC  /* The fixed value of EBase value of The fixed /* PC  ERL ErrorEPC restartPC # PC of branch/jump # PC of restartPC ErrorEPC instruction # PC of restartPC ErrorEPC PC  if ArchitectureRevision if ArchitectureRevision else endif if InstructionInBranchDelaySlot then if InstructionInBranchDelaySlot else endif if Status CacheErr  ErrorState CacheErr Status else endif are reported as cache error excep are reported as ExcCode Value Register Cause IBE:DBE: Error onan instruction reference Error ona data reference cheable reference) and that request is te is reference) and that request cheable A bus error occurs when an instructi A bus error occurs A cache error exception occurs when an instruction or data re exception occurs when an instruction A cache error Entry Vector Used Entry Vector 0x180)General exception vector (offset Used Entry Vector 0x100) Cache error vector (offset Operation ECC error is detected on the system bus ECC error is when a cache This exception is not system bus detected on the maskable. miss occurs. the error Because address. uncached an unmapped, to is vector exception the cache, in a was Value ExcCode Register Cause N/A Saved Additional State 6.2.16 Bus Error Exception 6.2.15Exception Cache Error MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

ged Resource Architecture, Rev. 6.02 a SYSCALL instructiona SYSCALL executed. is instructionresults in a TRUEvalue. ) ) ) . Table 9.52 onpage209 Table page 9.53 on 212 Table 9.53Table on page 212 Table 9.53 onpageTable 9.53 212 A system call exception occurs when exception occurs A system call Register ExcCode Value Register Cause Sys (See Saved Additional State None Used Entry Vector 0x180)General exception vector (offset A trap exception occurs when a trap when a exception occurs A trap Register ExcCode Value Register Cause (See Tr Additional State Saved Additional State None Used Entry Vector 0x180)General exception vector (offset An integeroverflow exception complement overflow. whenselected occurs integer instructions result in a 2’s Value ExcCode Register Cause Ov (See Saved Additional State None Used Entry Vector 0x180)General exception vector (offset See Additional State Saved Additional State None Used Entry Vector 0x180)General exception vector (offset 6.2.19 System Call Exception 6.2.18 Exception Trap 6.2.17 Overflow Exception Integer 98microMIPS32™ Privile / MIPS32® III: MIPS® Architecture Vol. For Programmers Interrupts and Exceptions

” ”  ” (reserved), 6.2 Exceptions ” that access to copro- to that access that access to coproces- to that access that access to the copro- the to that access ” (EJTAG). Floating-Point Exception, le Exception occurs instead. ption, setting the Unimple- n field that is flagged with “ opcode encoding of the function field register. sor Unusable Exception occurs instead. Exception occurs Unusable sor ” (EJTAG), assuming ” (EJTAG), unimplemented “ processor Unusable Exception occurs processor ed Resource Architecture, Rev. 6.02Architecture, ed Resource 99 opcode encoding of the function field when  FCSR reported this case as a or an COP0 ” (Module/ASE), assuming ” (Module/ASE), ” (Module/ASE), assuming ” (Module/ASE),   case as a Floating-Point Exce register. allowed, a Coprocessor Unusab a Coprocessor allowed, opcodethe encoding rs field of that is flagged with “ opcode encoding of the functio oding of thethatodingfield opcode is flagged of with “ ” (Module/ASE).  FCSR COPz REGIMM opcode encoding of the rt field that is flagged with “ SPECIAL opcode encoding of the function field that is flagged with COP1 ” (partner available), ” (partner  e coprocessor is not allowed, a Co not allowed, a is coprocessor e oprocessor is not allowed, a Coproces oprocessor is not allowed, a specifies an unimplemented SPECIAL2 specifies an unimplemented specifies an unimplemented ” (reserved), or an unimplemented “ or an ” (reserved), III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: ) ” (higher-order ISA). ” (higher-order  an unimplemented “ “ opcode, some implementations of previous ISAs ” (higher-order ISA), or an unimplemented ISA), or (higher-order “ ” ” (higher-order ISA), or an unimplemented ISA), or (higher-order “ ”   that is flagged with “ CO Table 9.53Table on page 212 (reserved), or Table 9.53 on page212 ) ” (higher-order ISA), or an unimplementedISA), “ ” (higher-order ”  Some implementationsof previous ISAs reportedthis sor 1 is allowed. If access to the c to If access sor 1 is allowed. (reserved), “ mented Operation bit in the Cause field of the cessor 0 is allowed. If access to th allowed. If access cessor 0 is instead. For the COP1 setting the Unimplemented Operationin bit the Cause field of the cessor is allowed. If access to the coprocessor is is not is allowed. If to the coprocessor cessor access (reserved). that is flagged with (reserved), “ rs is “ “ • An instruction was executed that specifies a •specifies a executed that was instruction An • executed that was instruction An •specifies a executed that was instruction An • An instructionwas executed that •a specifies executed that instruction was An A Reserved InstructionA Reservedfollowing Exceptionthe if any of conditions occurs true: is •specifies an enc executed that was instruction An Additional State Saved Additional State None Used Entry Vector 0x180)General exception vector (offset A breakpoint exception occurs when a BREAK instruction is executed. when a BREAK occurs exception A breakpoint Value ExcCode Register Cause Bp (See Register ExcCode Value Register Cause RI (See Saved Additional State None 6.2.21 Instruction Exception Reserved 6.2.20 Breakpoint Exception MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

register was a Status bit in the CU2 ged Resource Architecture, Rev. 6.02 efined coprocessor has been removed. MTC2, DMTC2, CTC2, MTHC2. MTC2, DMTC2, Value essor being referenced being essor the floating-point exception the floating-point the architecture. register was register was a zero register was a zero. instruction was executed, and the instruction was Status anyof the following conditions is true: itecture, the use of COP3 as a user-d of COP3 as the use itecture, Status l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. future extension of unit number of the unit coproc bit in the the in bit ) ) ude MFC2, DMFC2, CFC2, MFHC2, DMFC2, CFC2, ude MFC2, bit in the the in bit CU0 CU1 CE Register State Register State Value Cause FCSR indicates the cause of Table 9.52 on page 209 zero. COP2 instructions incl zero. COP2 instructions was and the executed or Kernel Mode, the or Kernel and NOTE: In Release 2 of the MIPS32 Arch 2 of Release NOTE: In The use of COP3 for is reserved the Entry Vector Used Entry Vector 0x180)General exception vector (offset Register ExcCode Value Register Cause CpU (See Table 9.52 on page209 Saved Additional State • SWC1,LDC1, SDC1 or MOVCI (Special opcode functionfieldencoding) instructionCOP1X,LWC1, A COP1, •SDC2 SWC2,LDC2, or LWC2, COP2, A Entry Vector Used Entry Vector 0x180)General exception vector (offset A floating-point exception is initiatedby the floating-point coprocessor to signalfloating-point a exception. ExcCodeRegister Value FPE (See Saved Additional State A coprocessor unusable exception occurs if A coprocessor unusable Entry Vector Used Entry Vector 0x180)General exception vector (offset • A COP0 or Cache instructionwas executedthe while processor runninga modein was other Debug than Mode 6.2.23 Floating-Point Exception 6.2.22 Unusable Coprocessor Exception 100 MIPS® Architecture Vo For Programmers Interrupts and Exceptions

6.2 Exceptions ture, Rev. 6.02 Rev. ture, 101 register to determine if the ch or cache instruction whose t is a one at the timea one at thewatch that t is a Cause registers.A watch exception is taken the exception actually occurred while in actually the exception bit in the ed Resource Architec ed Resource bitchanged. is not WP WatchLo WP ity exception, the prioritylower exception is taken. were zero. This bit directly bit directly This zero. were and ion was until after deferred ERL on is triggered by a prefet triggered by is on Value register isexception set, and the until is deferred both the ting in Debug Mode. Should a watch register match while rrent handler execution. rrent handler WatchHi Status Cause and register are both zero. If either bi zero. register are both ssor 2 to signal a precise coprocessor 2 exception. coprocessor signal a precise to 2 ssor Software may use the EXL bit is zero. is bit Status bit in the the in bit register and a single instruction generates both a watch exception (which bits) and a lower-prior LL Status WP at caused the watch exception, or if the watch exception, or at caused ERL ) Status causes a watch exception, so software must clear this bit as bit as this clear must so software exception, a watch causes of the part exception to prevent a handler watch exception loop at the end of the cu Indicates that the watch except that the Indicates both and ) III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: bits of bits the register are zero. EXL ERL register address matchconditions.register triggered A watchinstruction byeven a SC if does so Status WP and Watch Register State EXL Cause bits are one in the Table 9.52 onpage209 ERL bits in the or Table 9.52 on page 209 ERL EXL register points at the instruction th and kernel mode. If the immediately if the is deferred by the state of the by the is deferred the store would not complete because the because the store would not complete Entry Vector Used Entry Vector 0x180)General exception vector (offset Additional State Saved Additional State Register ExcCodeRegister Value (See WATCH exception would normally be taken, the Watch exceptions are never taken if the processor is execu are never taken exceptions Watch the processor is in Debug the exception Mode, is inhibited the and It is implementation-dependent whether a data watch excepti a whether implementation-dependent is It address matches the EXL EPC The watch facility provides a software debugging vehicle by initiating a watch exception when an instruction or data the stored in information reference matches the address A coprocessor 2 exceptionA coprocessor is initiated by coproce Register ExcCodeRegister Value C2E (See Saved Additional State Defined by the coprocessor Used Entry Vector 0x180)General exception vector (offset 6.2.25 Exception Watch 6.2.24 2 Exception Coprocessor MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

for 6.1 on page 71 ged Resource Architecture, Rev. 6.02 service is made. See Section is made. service register is zero. is register Value Cause register register is one. s that are pending. s that are Cause bit in the IV l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. bit in the the in bit IV an enabled request for interrupt indicatesinterrupt the ) IP Cause Register State Table 9.53on page 212 The interrupt exception occurs when exception occurs The interrupt Entry Vector Used Entry Vector 0x180)General exceptionthe vector if (offset Additional State Saved Additional State Interrupt vector (offset Interrupt0x200) if vector (offset the more information. ExcCodeRegister Value Int (See 6.2.26 Interrupt Exception 102 MIPS® Architecture Vo For Programmers Interrupts and Exceptions

to to is set CSS SRSCtl CSS field, and all HSS the current mode. ered shadow set ered shadow register provides the , and SRSCtl , and ture, Rev. 6.02 Rev. ture, 103 PSS rence to GPRs work exactly GPRs work to rence SRSCtl r updating the fields in the ition. Privileged software may is copied back into SRSCtl to associate a shadow set with with shadow set a to associate PSS at are not visible in visible at are not field is zero, only the normal GPRs are are logically consid are logically registerthe providesthe number previ- of ed Resource Architec ed Resource ne by writingtheESS field to the of is copied to SRSCtl to copied is conditionsthis case, steps 2 and 3 are true. In CSS SRSCtl rrupt mode, thebindingthe interrupt of toa specific el Mode entry condition, refe des with the same capability. This is done by des withintroducing the same capability. s. More precisely, the rules fo rules the precisely, More s. , and is configured in an implementation-dependent way. for thispurpose. The CSS field of the : NMI or cache error. cache : NMI or , and allowing privileged software allowing privileged , and ERL that can besubstitutedcan thattheGPRs normal on for entry to Kernel Mode via an Status er file, even specific er file, even specific shadow th registers source. On an ERET, the value of SRSCtl source. On an ERET, , inclusive must be implemented. If this ed interrupt to a shadow set is do is set shadow a to interrupt ed er set, and the PSS field of the field the PSS set, and er shadow sets implementation-dependent and may range from one (the normal GPRs) to an PSS HSS III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: or exception are as follows: or exception are as are redirected to registers that are dedicated to that cond are redirected to registers register is updated if any of the following m ofm 16. Thehighest number actually implementedis indicated by the SRSCtl SRSCtl = 1 = 1 is copiedSRSCtl to is BEV EXL register. If the is operating processor in EIC inte register. CSS Status Status register on an interrupt • are skipped. • The exceptionsets is one that •Debug Mode The exceptionentryinto causes EJTAG • SRSMap need to reference all GPRs in the regist all need to reference are used The RDPGPR and WRPGPR instructions implemented. ous shadow register set (that which was current before the last exception or interrupt occurred). If the processor is operating in VI interrupt mode, binding of a vectored interrupt to a shadow set is done by writing to the 2. SRSCtl rrupt occurs, the value of SRSCtl When an exception or interrupt occurs, the value register. restore the shadow set of the moderestoreset the shadow to which return control SRSCtl Shadow sets are new copies of the GPRs sets are Shadow interrupt or exception. Once a shadow set is bound to a Kern The capability in this at chapter removing is targeted the need to and save restore GPRs on entry to high priority inter- rupts or exceptions, and toprovide specified processor mo as one would expect, but they multiple copies of the GPRs, called entry to Kernel Mode via an interruptGPRs an The normal vector or exception. via entry to Kernel Mode to the value taken from the appropriate appropriate thefromto the value taken 1.the No field in shadow sets between 0 and SRSCtl number of the current shadow regist of the current number Binding of an exception or non-vector or of an exception Binding shadowset is provided by the externalinterrupt controller zero. is GPR shadow sets number of The architectural maximu MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 7.1 Introduction to Shadow Sets GPR Shadow Registers Shadow GPR Chapter 7 Chapter

= 1, 1, = with a IV 0, and EPC 

e which occurs VSS , loading PSS n or interrupt are as follows: or interrupt are as n = IntCtl1, No No IV for a vectored interrupt. ed exception or on exception or ed MIPS64 Only? ged Resource Architecture, Rev. 6.02 itions is true.In this case, step 2 is skipped. = 1 ster at the end of ster an exceptio BEV = 1. conditions These are the = 1). Status VInt register in any case of a nest of any case in register BEV Function register, based on IPL, if the exception on IPL, if based an interrupt, is Cause register, = 1 or Status Config3 SRSCtl ERL l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. register if the exception is an interrupt, Cause an interrupt, is exception if the register register in any other This is the case. condition for a non-interrupt exception, or SRSMap Status = 0, and = 0, CSS SRSCtl VEIC SRSCtl register is updated if any of the following cond Table 7.1Table Sets Shadow Supporting Instructions Config3 = 1. These are thea vectored EIC interrupt. conditionsare for 1. These = 0, SRSCtl 

VEIC is updatedfrom one of the following is sources: is copied to is copied SRSCtl VSS RDPGPR Read GPR From Previous Shadow Set WRPGPR Set to Shadow GPR Write PSS CSS Mnemonic a non-vectored interrupt. IntCtl Config3 • DERET is executed A • ERET is executed with An • The ESS field of the • The appropriatethe field of • Thethe field EICSS of before the processor has been fullyinitialize ( Privileged software mayPrivileged switchsoftware shadow the currentby set writing newvalue a into SRSCtl 2. SRSCtl These rules have the effect of preserving the of the effect rules have These 3. SRSCtl target address, and doing an ERET. target 1. No field in the Similarly, the rules for updatingrules for fieldsthe the in the SRSCtl regi Similarly, 104 MIPS® Architecture Vo For Programmers 7.2 Instructions Support GPR Shadow RegistersGPR Shadow

ndent cycle-based ndent cycle-based tion of another instruc- ture, Rev. 6.02 Rev. ture, 105 that eliminate hazards. To eliminate hazards. To that tion in cycles. It is for this It is for this cycles. tion in and software. As such, and software. new a way that they are backward- ne stages of a MIPS32/ EntryHi tion issues to cycles in a superscalar issued per cycle may be greater than may be greater issued per cycle e are no hardware interlocks. azards and instruction hazards. Both are hazards. and instruction azards implementation-depe ed Resource Architec ed Resource act as explicit barriers act as exists. fer to their Implementationtheirfer to documentationthe for y produce results that are noty produce results detectableare that subsequent by hardware interlock exists between one instruction that ns may be greater than the dura ns may be greater ns have been added in such e operation of various pipeli e operation of various rm compact between hardware CP0 hazard inate these inate these hazards. Consumer On Hazard TLBR, TLBWI, TLBWR n, execution of one instructio and by the execu seen e SSNOP instruction to convert instruc e SSNOP instruction 2 of the architecture which architecture 2 of the entations, the number of instructions ure, CP0 hazards were relegated to were ure, CP0 hazards   fferent types of hazards: execution h execution hazards: types of fferent e architecture should re e required to elim III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Table 8.1Table Hazards Execution Possible of execution cycles. When no cycles. When of execution e to a second instruction, to e a ation of the hazard in instructio the hazard ation of ting MIPS processors. ting MIPS Producer lists the possible execution hazards that might exist when ther might exist that execution hazards the possible lists Hazards Related to the TLB Related Hazards MTC0 Table 8.1 required instruction “spacing” that is required instruction “spacing” th defines that MIPS32 Release 1 reason design. Note that, for superscalar MIPS implem that, for superscalar Note one, and thus that the dur thus that one, and defined below. defined below. Release 1 of th using Implementations Execution hazards are those created by the by created are those Execution hazards tion. In privileged software, there are two di Because resources controlled via Coprocessor 0 affect th 0 affect via Coprocessor controlled Because resources microMIPS32 processor, manipulation of these resources ma resources of these manipulation processor, microMIPS32 instructions for some number causes an effect is visibl that causes an effect In Release 1 the MIPS32®of Architect solutions,based primarilyon the SSNOP instruction. Since that time, it has becomeclearis that thisan insufficient practicemustwith that be addressed a fi and error-prone instructions have been added to Release instructions have been the extentpossibleit that was todoso,newinstructio the exis with compatible 8.2.1 Possible Execution Hazards MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 8.2 of Hazards Types 8.1 Introduction CP0 Hazards CP0 Chapter 8 Chapter

, IE , , , , IV IP IM IM IE IE ASID CU ASID EPC, Status Wired Index, EBase Count, Config SRSCtl Cause Status Status Status Status SRSMap WatchHi, WatchLo, Compare, EntryLo0, EntryLo1, EntryLo0, EntryLo1, PageMask ErrorEPC, TLB entry PageGrain PageMask, EntryHi ged Resource Architecture, Rev. 6.02 EntryHi PerfCnt Counter, PerfCnt Control CU Consumer On Hazard BWI, Interrupted InstructionInterrupted Cause TLBWR TLBWR TLBP, Instruction Load or Store MFC0, TLBWIMFC0 Index instruction Coprocessor EntryHi, on the execution depends Status new value of ERET DEPC, MFC0CACHEMFC0 LLAddr PageGrain TagLo Load/store affected by new affected Load/store state TLBP, TLBR, Load/store using new TLB entry TL Interrupted InstructionInterrupted Status l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l.                Table 8.1Table (Continued) Hazards Execution Possible Producer MTC0 MTCO MTC0 Other Hazards LL TLBP TLBR or Related to Exceptions Interrupts Hazards MTC0 MTC0 MTC0 CACHE MTC0 TLBWI, TLBWR MTC0 EI, DI 106 MIPS® Architecture Vo For Programmers CP0 Hazards CP0

ture, Rev. 6.02 Rev. ture, 107 , 1 PSS ASID Status Supported Supported Config Architecture WatchLo WatchHi, SRSCtl EJTAG Cache entries Cache entries Cache a hazard on a modifi- hazard on a ed Resource Architec ed Resource e no hardware interlocks. e 8.3 Hazard Clearing Instructions and Events ious GPR context be established early in early be established context GPR ious ng the new value EntryHi n fetch. Rather it is Rather n fetch. eing the new instruc- new eing the instruc- new eing the struction Hazards Hazards struction Consumer On Hazard Consumer On Hazard Function are not meant to cover this case. to cover are not meant nd instruction hazards nd instruction MFC00 register CoProcessor any e executionof one instruction, and seen by the instructionanotherfetch of   Instruction fetch seei Instruction Instruction fetch seeing Instruction the new value (including a change to ERL followed by seg- useg from the fetch an instruction ment) fetch using new TLB Instruction entry entry TLB fetch se Instruction tion stream fetch se Instruction tion stream RDPGPR WRPGPR III: MIPS32® / microMIPS32™ Privileg / MIPS32® III:        Table 8.3Table Clearing Instructions Hazard Table 8.2Table In Possible structions and Events Table 8.1Table (Continued) Hazards Execution Possible lists the possible instruction hazards when there ar when there hazards instruction lists the possible Producer Producer cation to the previous GPR context field, followed field, followed by a previous-context reference to cation to the previous GPR context because hazard an execution than rather hazard an instruction considered It is GPRs. the prev the that require may implementation some and execution hazards pipeline, the DERET a execution both Clear Hazards Related to the TLB to the Related Hazards MTC0 MTC0 TLBWI, TLBWR Cache an Instruction or Modifying Stream the Instruction to Writing Related Hazards Entry stream Instruction writes CACHE Other Hazards MTC0 Mnemonic 1. This is not precisely a hazard on the instructio Table 8.2 MTC0 lists the instructions designed to eliminate hazards. designed to lists the instructions Table 8.3 Instruction hazards are those created by th created are those hazards Instruction instruction. 8.2.2 Possible Instruction Hazards MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 8.3 Clearing In Hazard

registers and registers Status , the JALR.HB or , the , or lity. See the JALR.HB lity. the target instruction instruction the target such, kernel software run- such, kernel software nother way, no hazards remain no hazards nother way, ErrorEPC Supported Supported ent instructions which will do this , Architecture is encoding was chosen for compat- for was chosen encoding is Release 2 Release 2 Release Release 1 Release All onwards onwards ASE MCU onwards onwards onwards Release 2 ged Resource Architecture, Rev. 6.02 ing the CACHE instruction. EPC tations, including many which pre-date ly implementations re execution of that re execution of , 2 of the 2 of the Architecture, DERET and ERET field of the JALR and JR instructions. hint DEPC and forward compatibi of the instruction and nd instructionhazards betweenthe instruction that or interrupt handler. Said a handler. or interrupt struction description for additionalinformation. Release 1 implementations. As Release 1 implementations. As the Architecture; EHB, JALR.HB, JR.HB, and SYNCI the Architecture; ng of the REGIMM opcode.ofng the REGIMM This encoding was chosen on stream write, and on and befo stream write, , but is included here included 0 hazard, but is y a coprocessor can emulate the function us instruction hazards instruction hazards instruction Function and they are the only timing-independ l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. variant of the NOP/SSNOP encoding. Th azards between the execution atibility withimplemen existing MIPS are encodingusing the bit 10 of peline flush clears hazards on most ear hazards on most flush clears peline ecture. In both Release 1 and Release ecture. In both Release 1 and Release also clears both execution a also clears both t of the instruction exception cluded in existing software for backward cluded in existing software d may be still a write of the created between Synchronize caches after instruction stream write stream instruction after caches Synchronize 2 Release chaining to another interrupt. chaining to another Table 8.3Table (Continued) Instructions Clearing Hazard 1 of the architecture. EHB hazard Clear execution IRET not hazards when instruction and execution both Clear ERET hazards and instruction execution both Clear JR.HB and execution both Clear SSNOP No Operation Superscalar SYNCI JALR.HB and execution both Clear for completeness. for instruction stream. As such, it is not precisel As such, stream. instruction Mnemonic 1. SYNCI synchronizes caches after an instructi and JR.HB instructions for additional information. a new encodi using is encoded SYNCI instruction The because it causes a Reserved Instruction exception on all on exception Instruction a Reserved because it causes ning on processors that don’t implement Release 2 implement Release don’t that ning on processors The EHB is instruction a encoded using in both releases in both releases h and ERET clear DERET Even though stream, an execution hazar DERET, ERET, and SSNOP are available in Release 1 of ERET, DERET, were added 2 of the in Release Archit clear hazards both execution and instruction ibility with the Release 1 SSNOP instruction, such that existing software may be modified to be compatible with both Release 1 and Release 2 implementations. See the EHB in The JALR.HB and JR.HB instructions comp were chosen for encodings These a pi the MIPS32 architecture. Because JR.HB instructions can be in the DERET or ERET instruction.the DERET In addition, an exception or interrupt created the hazard and the firs hazard and the the created visibleinstructionfirst by the ofinterrupt an exception or handler. 8.3.1 MIPS32 Instruction Encoding 108 MIPS® Architecture Vo For Programmers CP0 Hazards CP0

ture, Rev. 6.02 Rev. ture, 109 ng. See the ng. See the and EHB SSNOP ed Resource Architec ed Resource 8.3 Hazard Clearing Instructions and Events variant NOP encodi of the III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: instruction description for additional information. The EHB and SSNOP The EHB instructions are using a encoded 8.3.2 microMIPS32 Instruction Encoding MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 110 MIPS® Architecture Vo For Programmers CP0 Hazards CP0

ers) (Others) (Others) (Others) (Others) (Others) Optional Optional Required (Release 6) Required (TLB (Pre-Release 6); (Pre-Release Optional (Others) (Others) Optional Module); Optional Optional Module); Module); Optional Optional Module); Module); Optional Optional Module); Module); Optional Optional Module); Module); Optional Optional Module); Required (MIPS MT Required (MIPS MT Required (MIPS MT Required (MIPS MT Required (MIPS MT Required (TLB MMU) Required (TLB MMU) MMU); Optional(Oth- ture, Rev. 6.02 Rev. ture, 111 e PRA. register is discussed Each 9.6 on page 9.4 on page Reference Compliance Level mber, then by select field number. then field number. by select mber, ed Resource Architec ed Resource MIPS®MT Module Module MIPS®MT Specification MIPS®MT Module Module MIPS®MT Specification MIPS®MT Module Module MIPS®MT Specification Section Section Module MIPS®MT Specification MIPS®MT Module Module MIPS®MT Specification Section 123 MIPS®MT Module Module MIPS®MT Specification 119 MIPS®MT Module Module MIPS®MT Specification dual registers are described later in this document. If used without generat- (TLB MMU)”), it applies only (TLB MMU)”), it appliesif the qualifyingcondition true. is ead configuration infor- configuration ead ead configuration infor- configuration ead containing relatively vol- containing Function register containing global register containing global nfiguration data used in the used in field of the same name MTC0 instructions. in the MFC0 and Required ide interface the ISA and between the th numerical order, first by registernu numerical order, III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: ing an exception ing qualifier bits may be bits may qualifier mation mation atile thread co thread atile Index into the TLB Index into the TLB array ration information ration array ration information ration MIPS® MT configuration data configuration MT MIPS® gister Summary Table 9.1Table Order in Numerical 0 Registers Coprocessor Register Name 1 lists the CP0 registers in numerical order. The indiviThe lists the CP0 registers in numerical order. below, with the registers presented in with the registers presented below, The Sel column indicates the value to be Table 9.1 The Coprocessor 0 registers prov (CP0) “ the compliance level is qualified (e.g., 1 4 YQMaskwhich YIELD register defining Per-VPE 1 3 VPEConf1 multi-thr Per-VPE 1 2 VPEConf0 multi-thr Per-VPE 1 1 VPEControl register Per-VPE 01 3 MVPConf1 0 Randomconfigu- multi-VPE dynamic Per-processor the TLB index into Randomly generated 0 2 MVPConf0configu- multi-VPE dynamic Per-processor 0 00 Index 1 MVPControl Per-processor Number Sel Register MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.1 0 Re Coprocessor Coprocessor 0 Registers 0 Coprocessor Chapter 9 Chapter

ers) ers) ers) ers) (Others) (Others) (Others) (Others) (Others) Optional Optional Optional Optional Optional Optional (Release 2) Recommended Recommended Required (TLB Required (TLB Required (TLB Module); Optional Optional Module); Module); Optional Optional Module); Module); Optional Optional Module); Module); Optional Optional Module); Module); Optional Optional Module); Required (MIPS MT Required (MIPS MT Required (MIPS MT Required (MIPS MT Required (MIPS MT Required (Release 6) ASE); Optional (Oth- Required (SmartMIPS (SmartMIPS Required MMU); Optional(Oth- MMU); Optional(Oth- MMU); Optional(Oth- ged Resource Architecture, Rev. 6.02 9.7 on page 9.9 on page 9.11 on page 9.7 on page Reference Compliance Level on page 141 MIPS®MT Module Module MIPS®MT Specification Module MIPS®MT Specification Section 125 MIPS®MT Module Module MIPS®MT Specification Module MIPS®MT Specification Specification 137 MIPS®MT Module Module MIPS®MT Specification ification and Section ification and 9.10 MIPS®MT Module Module MIPS®MT Specification Section Section 143 MIPS®MT Module Module MIPS®MT Specification Module MIPS®MT Specification Section 125 MIPS®MT Module Module MIPS®MT Specification Module MIPS®MT Specification SmartMIPS ASE Spec- ASE SmartMIPS of and Status g g Halt state of TC MIPS®MT Module as cache partition- as cache partition- and read via RDHWR ocessor implements the the implements ocessor to manage scheduling to manage restart instruction address configuration Function to manage scheduling a of to manage scheduling er to provide scheduling er to provide information, including cop- information, l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. registers. Per-TC register to provide control register to provide control over Per-TC Per-TC register controllin register Per-TC TC back to software virtual pages odd-numbered optional features, such control ing system use for the associatedfor of execution thread binding register 29. the If pr regis- a per-TC is MT Module, this MIPS® ter. privileged software feedback to software a VPE withina VPE a processor optional features, such virtual even-numbered pages of bits thread-specific of ies ing control ing EntryHi Table 9.1Table (Continued) Order in Numerical 0 Registers Coprocessor Register Name 1 22 63 TCSchedule 7 TCScheFBack register Per-TC 03 register to provide scheduling feed- Per-TC EntryLo1 7 Low-order portion of the TLB entry for TCOpt 2 5 TCContext read/write storage for operating Per-TC 4 0 Context in memory entry table to page Pointer Section 2 4 TCHalt 4 1 ContextConfig Context register 2 3 TCRestart value of Per-TC 2 2 TCBind TC ID information about and VPE Per-TC 4 2 UserLocal by be written can that information User 1 5 VPESchedule register Per-VPE 11 6 VPEScheFBack 72 regist Per-VPE VPEOpt 02 EntryLo0over control register to provide Per-VPE 1 Low-order portion of the TLB entry for TCStatus status Per-TC Number Sel Register 112 MIPS® Architecture Vo For Programmers Coprocessor 0 Registers

ers) ers) (Others) Optional Optional Optional Optional Optional Optional Optional Optional Optional Optional Optional Required Reserved Reserved (Release 2) Required (TLB Required (TLB ASE); Optional Module); Optional Optional Module); Required (MIPS MT Required (Release 2) Required (SmartMIPS (SmartMIPS Required MMU); Optional(Oth- MMU); Optional(Oth- ture, Rev. 6.02 Rev. ture, 113 9.15 on page 9.13 on page 9.24 on page 9.16 on page 9.23 on page 9.17 on page 9.18 on page 9.19 on page 9.20 on page 9.21 on page 9.22 on page Reference Compliance Level 9.1 Coprocessor 0 Register Summary ed Resource Architec ed Resource Section Section Section 9.14Section on page 157 Section Section 147 151 and SmartMIPS ASE Specification Section Section 177 157 Section Section 175 157 Section Section 161 Section Section 161 MIPS®MT Module Module MIPS®MT Specification Module MIPS®MT Specification Module MIPS®MT Specification Module MIPS®MT Specification 164 Section 169 Module MIPS®MT Specification 171 gister set configura- gister set configura- gister set configura- gister set configura- gister set gister set configura- gister set Hardware Page Walker Page Hardware Section r of fixed (“wired”) onfiguration in 64-bit onfiguration inters for Hardware Page Hardware Page inters for Address for Hardware Address for Function all page support plementations III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: entries address-related exception to selected hardware registers to Reserved for future extensions future Reserved for XContext register c XContext register im Page Walker Controls the numbe Walker controlling shadow re controlling shadow re controlling shadow re controlling Control Page Walker HW tion tion tion tion controlling shadow re controlling TLB entries tion controlling shadow re controlling Table 9.1Table (Continued) Order in Numerical 0 Registers Coprocessor Register Name 1 0 HWREna Enables accessvia the instruction RDHWR 5 2 SegCtl01& Segments 0 for Control Programmable Section 5 3 SegCtl13& Segments 2 for Control Programmable Section 5 0 PageMask size page Control for variable in TLB 5 1 PageGrain Control for sm 8 0 BadVAddrrecent most the the address for Reports 5 4 SegCtl25& Segments 4 for Control Programmable Section 7 1-7 4 3 5 5 PWBase Base Page Table 5 6 PWFieldof po Bit indices 5 7 PWSizeof pointers for Size 6 36 SRSConf2 46optionally and register indicating Per-VPE SRSConf3 56optionally and register indicating Per-VPE SRSConf4 6optionally and register indicating Per-VPE PWCtl 6 2 SRSConf1optionally and register indicating Per-VPE 6 0 Wired 7 6 1 SRSConf0optionally and register indicating Per-VPE Number Sel Register MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

6) 6) ers) ers) ers) dent dent mented) (Others) (Others) (Others) (Others) Required Required Required Required (TLB Module; Optional Module; Module; Optional Module; Module; Optional Module; Optional Module; Required (Release Required 2 Required (Release 6) Required (Release 2) Required (Release 2) Required (Release 6) ASE); Optional (Oth- ASE); Optional (Oth- Required (MIPS VZE Required Required (MIPS VZE Required Required (MIPS VZE Required (MIPS VZE Required Optional (Pre-Release Optional (Pre-Release Optional (Pre-Release Optional (Pre-Release Required (MIPS MCU Required Required (MIPS MCU Required MMU); Optional(Oth- implementation-depen- implementation-depen- and shadow sets imple- and ged Resource Architecture, Rev. 6.02 9.31 on page 9.32 on page 9.33 on page 9.34 on page 9.26 on page 9.27 on page 9.30 on page 9.25 on page 9.28 on page 9.29 on page Reference Compliance Level Section Section Section Section Section Section Section 9.35Section on page MIPS® VZE Module VZE Module MIPS® MIPS® VZE Module MIPS® Section Section 187 Specification 189 199 203 Section Section 181 183 187 Specification MIPS® VZE Module VZE Module MIPS® 207 Specification Section Section 179 Section 183 185 Specification Specification Specification MIPS® MCU ASE MIPS® Set Control VZE Module MIPS® and IPL fields. IPL and MCU ASE MIPS® which caused the which caused t status and control Section ementation-dependent ementation-dependent ementation-dependent lized Guest lized status and control Section ch instruction if a delay instruction ch Function ruction GuestCtl0 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. Interrupt system Interrupt Shadow register se Shadow Processor cycle count cycle Processor Processor status and control Processor user Available for impl for Available slot causedmost therecent exception. most recent exception. exception. most recent Available for impl for Available user Table 9.1Table (Continued) Order in Numerical 0 Registers Coprocessor Register Name 1 9 0 Count 8 2 BadInstrP9 Reports the bran 6-7 8 1 BadInstr the inst Reports 11 6-7 1111 0 Compare 4 GuestCtl0Ext interrupt control Timer of Extension 1212 0 Status 1 IntCtl 12 2 SRSCtl 12 3 SRSMap set IPL mapping Shadow 10 0 EntryHi portion of the High-order TLB entry Section 10 410 GuestCtl1 510virtua GuestID of GuestCtl2 6Control Guest Interrupt GuestCtl3 Register Guest Shadow 12 412 View_IPL 5 view Contiguous of IM SRSMap2mapping set IPL Shadow Number Sel Register 114 MIPS® Architecture Vo For Programmers Coprocessor 0 Registers

ers) dent (Others) (Others) Optional Optional Optional Optional Optional Optional Optional Optional Optional Optional Required Required Required Required Required Module); Optional Optional Module); Optional Module); Required (Release 2) ASE); Optional (Oth- Required (MIPS VZE (MIPS Required (MIPS VZE Required Required (MIPS MCU Required implementation-depen- ture, Rev. 6.02 Rev. ture, 115 on page 9.48 on page 9.49 on page 9.50 on page 9.51 on page 9.41 on page 9.47 on page 9.37 on page 9.39 on page 9.40 on page 9.46 on page 9.55 9.38 on page 9.45 on page 9.52 on page 9.36 on page 9.42 on page 9.43 on page Reference Compliance Level 9.1 Coprocessor 0 Register Summary ed Resource Architec ed Resource Section Section Section Section Section Section Section Section Section Section Section Section Section Section Section Section Section 245 253 259 Section 267 223 241 Specification Section 215 Section 219 221 237 217 233 269 Specification MIPS® VZE Module Specification 209 Section 227 Section Section 229 279 MIPS® VZE Module t OS and RIPL fields. and MCU ASE MIPS® zed Gues ementation-dependent cation and cation and revision Section ger Global Control ger Global Control Regis- Function ce Memory Map Base ion Support - EXL, ERL val- ion Support - Program Coun- general exception Offset III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Cause of last Exception vector base register vector base Exception user ues at current exception ter at current exception Available for impl for Available register ter Base register Program counter at last exception at last counter Program Section register Configuration Processor identifi Table 9.1Table (Continued) Order in Numerical 0 Registers Coprocessor Register Name 1 1616 316 Config3 316 Config4 4 register 3 Configuration Config5 6-7 register 4 Configuration register 5 Configuration 15 1 EBase 16 2 Config2 register 2 Configuration 17 0 LLAddr Load linked address 1314 514 NestedExc 015 EPC Nested except 2 NestedEPC 0 PRId Nested except 16 1 Config1 register 1 Configuration 18 0-n WatchLo address Watchpoint 13 4 View_RIPL view Contiguous of IP 15 2 CDMMBase Common Devi 12 713 GTOffset 0 Timer Guest Cause 1516 3 CMGCRBase 0 Mana Coherency Config 12 6 GuestCtl0 Control of Virtuali Number Sel Register MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

rchitec- dent mended. mended. Optional Optional Optional Optional Optional Required Reserved Reserved Reserved Pre-Release 6: Recommended Required (Cache) Required Required (Cache) Release 6: Required. at select 3 are recom- 3 are select at select 2 and KScratch2 Optional; KScratch1 at implementation-depen- on page Specification Optional ged Resource Architecture, Rev. 6.02 9.57 on page 9.61 on page 9.65 on page 9.66 on page 9.67 on page 9.68 on page 9.70 on page 9.63 on page 9.62 on page 9.64 on page 9.56 ce Specification Optional ce Specification Optional Reference Compliance Level Section Section Section Section Section Section PDtrace SpecificationPDtrace Optional PDtrace PDtrace SpecificationPDtrace Optional PDtrace SpecificationPDtrace SpecificationPDtrace Optional Optional Section Section 283 EJTAG SpecificationEJTAG Optional EJTAG SpecificationEJTAG Optional EJTAG SpecificationEJTAG Optional 291 301 303 305 307 311 281 297 295 299 PDtra PDtra che data interface data che Section er er Kernel Mode Section ster ster ontrol and status and ontrol Section ementation-dependent ementation-dependent Function rror control and statuscontrol rror Section l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. control register control register control register Low-order Low-order ca portion of Reserved for future extensions. extensions. future for Reserved High-order portion of cache tag interfaceHigh-order Section High-order portion of cache data interfaceof portion High-order Section Available for impl for Available XContext in 64-bit implementations 64-bit in XContext use Program counter at last EJTAG debug debug at counter last EJTAG Program exception Scratch Registers for for Scratch Registers EJTAG Debug Debug register EJTAG Low-order portion of cache Low-order tag interface Section Parity/ECC error Parity/ECC error c licitly noted as available for implementation-dependent use is reserved for future use by A use the by for future use is reserved for implementation-dependent available as noted licitly Table 9.1Table (Continued) Order in Numerical 0 Registers Coprocessor Register Name TagHi TagLo DataLo DataHi 1 selects selects selects selects 2122 all all 23 0 Debug 23 1 TraceControl control regi PDtrace 232323 424 5 TraceIBPC 6 TraceDBPC 0 PDtrace control regist Debug2 PDtrace control regist DEPC Debug2 register EJTAG 2425 2 TraceContol3 0-n control regi PDtrace PerfCntinterface counter Performance 29 even 3131 0 2-7 DESAVEn KScratch debug exception save register EJTAG Specification EJTAG Optional 30 0 ErrorEPCerror last at counter Program 20 0 23 2 TraceControl2 PDtrace 2728 0-3 CacheErr even Cache parity e 23 3 UserTraceData1 PDtrace 26 0 ErrCtl 28 odd 24 3 UserTraceData2 PDtrace 29 odd 19 0-n WatchHi control Watchpoint ture. Number Sel Register 1. Any select (Sel) value not exp 116 MIPS® Architecture Vo For Programmers Coprocessor 0 Registers

9.2 Notation UNPRE- ture, Rev. 6.02 Rev. ture, 117 UNDEFINED this field return the this field return the field, and the reset state and the reset state the field, elds that are reserved for elds Software reads of this ly, by hardware. ly, eld with zero before it as all previous software as hout affecting hardware hardware hout affecting e read from a coprocessor 0 register register 0 coprocessor from a e read the impactPro- of writes to other fields. value except after a hardware after value except ssor modifies the register between the soft- Software Interpretation Software re and, potential re and, ed Resource Architec ed Resource . Software updates of this field are visi- field return zero as long writes are zero. “Undefined”, field is of this State If the Reset software must writethis fi is guaranteed to read as zero. A field to which the value written by software the value written to which A field must be Software writes of non-zero val- zero. result in may field to this ues hardware. the behavior of A field to which the value written by is written software the A to which value field Software may write any by hardware. ignored field wit this value to reads of Software behavior. updated by hardware. last value “Undefined”, field is of this State If the Reset in an software reads of this field result DICTABLE specified in update under the conditions done field. the description of the the read/write properties of the read/write ing coprocessor 0 register fi This rule means that software can read a register, modify rule means that software can read a register, This e bits is consistent with software assumptions. tion behavior. e by and writable readable softwa not intended to act as a not intended s the term “Externally s formal value. This should not be return a predictable confused with the stream). These terms are are terms These stream). that the state is estab- assume that it can validly write the valu the appropriate state, the register withoutthe register havingconsider to this rule is a situation in which the proce III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: w, field descriptions include descriptions field w, Table 9.2Table Bit Field Notation Read/Write UNDEFINED teproperties thethe field, of following notationused: is Hardware Interpreta an event does not occur. Hardware by software read Hardware updates visible of this field are ble by hardware read. value the initialize must hardware or software either is “Undefined”, field of this State Reset the If before first read will the of definition by hardware. If the Reset of this State field is either “0”, “Pre- initializes hardware Set”, “Externally or set”, to or zero to field this is term “Preset” The powerup. on respectively, the establishes processor the that suggest to used appropriate state, wherea is used to suggest Set” lishedviasource an external (e.g.,personality pins or initialization bit and are suggestions only, which hardware can assume a zero value. requirement on the implementation. is of this field “Undefined”, If the Reset State those under only this field hardware updates of the description conditions specified in the field. 0 field which hardware does not update, and for A R which is either field static A or is updated only R/W field in which all bits ar A Notation Read/Write Read/Write ware read and write, such as might occur if an exception or interrupt occurs between the read and write. Software the or interrupt occurs between as might occuran exception such if and write, read ware guarantee that such must implementations and make sure that the use of thes use the make sure that and implementations The most significant exception to cessor designers shouldtake this into consideration when us back to that register without having unintended side effects. one field,back and write the value to With certainsoftware restrictions, may With of the field. of the field. For read/wri the For each register described belo described For each register 9.3 CPU Registers Writing 9.2 Notation MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

if a field is reserved, then a write of a reserved, then a write if a field is ged Resource Architecture, Rev. 6.02 NED or UNPREDICTABLE behavior. For behavior. NED or UNPREDICTABLE ting. An exception to this rule is that l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. ed by hardware. This meansed by hardware. that no fieldis in theCOP0modifiedregister defined COP0 register field thatfielddefined COP0 may register have reservedwrites encodings,of unsup- is ignoreditselfto but bywrite doesentire be dropped.the not cause es where software can cause UNDEFI can cause where software es example, in Release 6, for writes to a writes to for in Release 6, example, ported values cause the write to be ignor for the conditions all fields meet unless wri non-zero value to the reserved field Release 6 limits the number of cas limits the number Release 6 118 MIPS® Architecture Vo For Programmers Coprocessor 0 Registers

Index ture, Rev. 6.02 Rev. ture, 119 equal to the number of Undefined Required nn-1 0 register fields. fields. register an, or equal to, the number of TLB R R/W Index ed Resource Architec ed Resource (Release 6) 9.4 Index RegisterRegister(CP0 0,Select 0) (Pre-Release 6) if a value greater than or greater a value if otherwise. field describes the the describes plementation-dependent as a function of the number of Field Descriptions Field Descriptions ontains the index used to access the TLB for TLBP, TLBR, TLBP, for the TLB to access ontains the index used Index Optional UNDEFINED Table 9.3 Table Meaning ons may use P=0 to cause a cause use P=0 to ons may 0 ites this bit during execution execution during this bit ites field unchanged if a value greater th unchanged field register; indicate whether a TLB returns zero on read. 0 0 Reserved e minimum value for TLB-based MMUs is Ceiling(Log2(TLBEntries)). For Index Description Read/Write Reset State Compliance Index Figure 9.1Figure Format Register Index register. III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: UNPREDICTABLE Register 0, Select 0) 0, Select Register contains the index of the matching matching the index of the contains entry is for TLB-based MMUs; for TLB-based register. Index ation theof processor is Table 9.3Table Register Index 1 field match occurred and the Index No 0 A match occurred, and the Index Required

Encoding TLBWR to write to a TLB entry other than that indexed that indexed than entry other a TLB to write to TLBWR this to by 0 the Index a write of field. Hardware ignores bit. of the TLBP instruction to TLBP instruction of the 6 requires that match occurred. this bit be R/W Release allowto softwareafter set to TLBPbita the has 1 to Implementati the bit. cleared shows the format of the register is a 32-bit read/write register which c 32-bit read/write register which is a register Index Fields The

For Release 6: Hardware leaves the leaves For Release 6: Hardware and TLBWI instructions.width The theindex of field im is Th implemented. are TLB entries that withentries).six bits are required for a TLB 48 example, The oper 6: For Pre-Release Compliance Level: entries is writtenentries is to the Figure 9.1 TLB entries is writtentheto 0 30. n be written as zero; Must P 31 Failure. Hardware wr Probe P Name Bits 31 MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.4 (CP0 Register Index

ged Resource Architecture, Rev. 6.02 R/W Undefined Required of the TLBP instruction. . l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. ferenced by the TLBR and ites this field to provide the ites this field to provide Description Read/Write Reset State Compliance TLB entry re TLB entry UNPREDICTABLE Table 9.3Table (Continued) Descriptions Field Register Index TLBWI instructions. match- of the index the with field this writes Hardware execution ing TLB entry during of this contents the to find a match, If TLBP fails the field are index to the Fields Index n-1..0 TLB wr index. Software Name Bits 120 MIPS® Architecture Vo For Programmers

=1). VP DIS Config5 ture, Rev. 6.02 Rev. ture, 121 register fields. VPControl R 0 Required Write Reset State Compliance Read/ 9.5 VPControl0,4) Select Register (CP0 ed Resource Architec ed Resource describes the describes 12 11 8 7 0 sed Multi-threading supported ( i.e., =1. er Field Descriptions andconfiguration support for Release 6 multi-threading. DIS Table 9.4 all other VPs on the 0 , this virtual processor has processor virtual this register; register; rtual processors in the physi- in the rtual processors multi-threading DVP and EVP DVP and multi-threading VPControl Description VPControl VPControl III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Figure Figure 9.2 Format Register VPControl Table 9.4Table Regist VPControl . if Release 6 Virtual Processor ba . if Release 6 Virtual Required

core have been core have disabled if A DVP instruction executed on DVP instruction A disabled on fetch vi all other cal core. An EVP instruction is the only means to subse- to means only the is EVP instruction An core. cal DIS. quently clear 6 of Release See definition instructions for supporting information. for supporting instructions shows the format of the Fields CP0 Virtual ControlProcessor providesregister control CP0 Virtual Figure 9.2 Compliance Level:

031:10 0 0Reserved DIS 0 For a VP that reads Name Bits 31 MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.5 VPControl (CP04) 0, Select Register ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 122 MIPS® Architecture Vo For Programmers

register is register Wired Random ture, Rev. 6.02 Rev. ture, 123 register above. operating system (the con- available to be written available to be written by a register fields. nn-1 0 Index TLB Entries - 1 Required Random R ed Resource Architec ed Resource Write Reset State Compliance Read/ a Reset Exception, and when the 9.6 Random RegisterRegister (CP01, 0) Select register is the first entry entry the first is register otherwise. Pre-Release 6 only; deprecated in Release Release in only; deprecated Pre-Release6 otherwise. describes the ed for exclusive use ed exclusive use by the for , the mannerthe , in whichprocessor the selects values for ed to index the TLB during a TLBWR instruction. The Wired Optional Table 9.5 register; 0 returns zero on read. 0 0 Reserved Description register to the upper bound on Register 1, Select 0) 1, Select Register Random III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Figure Figure 9.3 Format Register Random Random Table 9.5Table Field Descriptions Register Random register). The entry indexed by the for TLB-basedMMUs; Required

Wired register is a read-only register whose value is us register is implementation-dependent. shows the format of the Random tents of the TLB Write Random operation. TLB Write Random Fields 6. The Compliance Level:

width of thewidth Random of fieldcalculatedin is the same manner for as that described the The valuethe registerThe of between an uppervaries and lowerfollow: bound as • A lower boundtheby is setof number TLB entries reserv written. Figure 9.3 The processor initializesThe the the • An upper bound is set by the totalof number entries TLB minus 1. andtheconstraints the required lower upper of bounds Within 0 31. nas zero; be written Must Name Bits Random n-1..0 TLB Random Index 31 9.6 (CP0 Register Random MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 124 MIPS® Architecture Vo For Programmers

Fill and register Table 9.9 Table 9.6 Table 9.7 PFN by reading EntryHi registers. CDVG ture, Rev. 6.02 Rev. ture, 125 registers; registers; registers; registers; registers may be option- registers and reading the registers and reading Figure 9-7 Context 65 3210 support for Read-Inhibitand or EntryLo1 EntryLo1 EntryLo1 EntryLo1 EntryLo1 or and A 36-bit PAE is supported in the base A 36-bit PAE and and and ddress error exception, and some fields error exception, and ddress BadVAddr otherwise. otherwise. ed Resource Architec ed Resource formats shown in EntryLo0 EntryLo0 EntryLo0 EntryLo0 EntryLo0 holds the entries for odd pages. Optional Optional EntryLo1 3 of the architecture added of the architecture 3 . e TLB and the TLBP, TLBR, TLBWI, and TLBWR TLBR, TLBWI, the TLBP, TLB and e EntryLo1 and 9.7 EntryLo0, EntryLo1(CP0 Registers 3,and 0) Select 2 ELPA MTHC0 and MFHC0 instructions defined in Release 5. defined in Release instructions MFHC0 MTHC0 and error exception sequence. Software writes to the EntryLo0 shows the format of the shows the format of the the format of the shows by writing all ones to the PFN PageGrain registers are not defined after an a not defined after are registers field allow software to determine the boundary between the for a TLB-based MMU; TLB-based for a MMU; TLB-based for a Registers 2 and 3, Select 0) 2 and 3, Registers . hysical address size greater than 36 bits. address hysical PFN PABITS In Release 5 of the Architecture, 5 of the In Release register fields. fields. register of2 the architecture fields. Release support addedaddress register for physical Release fields. register EntryLo1 III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Required Required PA BI T S is is providing greater than a 36-bit PA in MIPS32 is termed Extended Physical Address providing greater thana 36-bit PA and EntryLo1 EntryLo1 EntryLo1 port for XPA and for the XPA port for and and and the holds for entries and even pages EntryLo0 EntryLo1

EntryLo0 registers act as the between interface th EntryLo0 EntryLo0 EntryLo0 EntryLo0 Software can enable XPA using XPA Software can enable EntryLo . LPA Figure Figure 9-4 Architecture of the 1 in Format Release Register EntryLo1 EntryLo0, ComplianceLevel: The pair of Execute-Inhibit page protection bits. maybemodified by hardware during the address- ally extended by 32 bits to support a p instructions. (via MTC0)(via implicitthe do not cause updateof address-related in fields the value back. Bits read as “1” from the “1” from read as Bits back. value

Software may determine the value of For Release 1 of the Architecture, Figure 9-4 of For Release 1 Config3 Compliance Level: describes the describes the describes the fields to calculate the value of value fields to calculate the For Release 2 of the Architecture, Figure 9-5 of For Release 2 36 spaces beyond bits in range and support for 1 kB pages. the Architecture, Figure 9-6 of For Release 3 architecture; the capability of architecture; the is 40 bits, while the naturallimitupper 59 bits, is as determinedby the practical The lower limitof XPA (XPA). withintheof range 37 bits59and bits is implementation-dependent. XPA MIPS64 Architecture.size of The the new the 32-bit extension with Software can access Software can detect sup The contents The contents of the Fill 31 30 29 MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.7 EntryLo0, EntryLo1 (CP0

MMU) CDVG 65 3210 ged Resource Architecture, Rev. 6.02 R 0 Required R/W Undefined Required R/W Undefined Required R/W Undefined Required R/W Undefined Required R/W Undefined (TLB Required Write Reset State Compliance Read / Read

-1..12 Table Table . See el data struc- EntryLo0 PA BI TS is the width of the PABITS for more information. this bit is a one, accesses ange as a function of the PFN PABITS ception that results on any on ception that results becomes the G EntryLo1 becomes ng which pages have been pages have ng which to update kern to update y of the Attribute page. See are permitted. If is this bit a permitted. are l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. use a TLB Modified exception. the G bits of both and and Description bits. The boundaries of this field . See Table 9.8 . See EntryLo0 reflect the state of the G of the TLB bit. state the reflect below. PA BI TS EntryLo1 for more information. for Table 9.12 is a one, stores to the page page ca zero, stores to the paging implement to bit this use may software Kernel knowi algorithms that require is initially when a page zero If this bit is always written. TLB mapped, the Modified ex used can be page store to the The boundaries of this field ch The boundaries of this of value of the change as a function 9.8 value of where of the physical address, in physical address tures that indicatethatwas page the actually written. tual page mapping are valid. tual If to accesses zero, is a bit this If permitted. are page the to exception. Invalid cause a TLB page the both bits from G bit is a one, If TLB entry the entry. in the TLB bit TLB matches. On during are ignored ASID comparisons entry, from a TLB a read and Figure Figure 9-5 Architecture of the 2 in Format Release Register EntryLo1 EntryLo0, Fields

C 5..3Coherenc Cacheability and D 2 bit this If is writable. page the that indicating bit, “Dirty” V 1G the vir- and thus entry, the TLB that indicating bit, Valid 0 Global bit. On a TLB write, logical ANDthe of the G Fill 31..30read. on zero on write and return ignored bits are These Fill PFN 29..6 bits to Corresponds Page Frame Number. 31 30 29 Name Bits Table 9.6Table Architecture the 1 of in Release Descriptions Field Register EntryLo1 EntryLo0, 126 MIPS® Architecture Vo For Programmers

MMU) No ture, Rev. 6.02 Rev. ture, 127 Release 2 Required? support enabled, and the value of 35 12 ))..6 = 36 = = 13 = PA R 0 Required 29 6 R/W Undefined Required R/W Undefined Required R/W UndefinedR/W Undefined Required R/W Undefined Required (TLB Required Write Reset State Compliance ed Resource Architec ed Resource Example: Read / Read 6..6 if PABITS PA(29-(36- BI T S 29..6 if PA BI TS EntryLo field )) 9.7 EntryLo0, EntryLo1(CP0 Registers 3,and 0) Select 2 m Release 1. 1. m Release m Release 1. 1. m Release 1. m Release = 36 = 13 from Release 1. 1. from Release PABITS fields as a function of 1 pagekB = 1),the PFN field below. = 0), the PFN the 0), = PAB I TS ). ESP PFN for more information. for more information. Example: ESP Fill FieldFill Field PFN ange as a function of the ange as a function of the the physical address (the the address (the physical to the virtual page. to the 11 10 Corresponding EntryLo FieldRanges Bit of the address. physical and 31..7 if 31..7 Table 9.12 d is unchanged fro d is unchanged fro d is unchanged fro 31..30 if PA BI T S eld is unchanged Fill Description PageGrain PageGrain III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: . See Table 9.8 . See Table 9.8 . See above. above. above. above and and above > 12 31..(30-(36- = 0 or = 0 or = 1 and Value SP SP SP SP PA BI TS PA BI TS PA BI T S

Table 9.6 Table 9.6 Table 9.6 Table 9.6  PABITS See See See The boundaries of this field ch The boundaries of this to bits 35..12 corresponds The boundaries of this field ch value of value of See field isshifted leftrelative by 2 bits theto Releasedef- 1 inition to make room for PA corresponds to bits 33..10 of corresponds If the is not enabled processor to 1 support kB pages (Config3 page number corresponding page number corresponding pages kB 1 enabled to support is processor the If (Config3 Table 9.8Table of PABITS a Function as Widths Field EntryLo shows the movement of the . Note that in implementations of Release 1 of the Architecture, there is no support for kB1 pages, so only the No 36 1 kB Page Support Support Enabled? Fields PABITS first row of the table appliestoRelease 1. Table 9.8

C 5..3fi of this definition The D 2 of this fiel The definition VG 1 of this fiel The definition 0 of this fiel The definition Fill 31..30read. on zero on write and return ignored bits are These PFN 29..6 This field contains the physical Page Frame Number. Name Bits Table 9.7Table Architecture 2 of the in Release Descriptions Field Register EntryLo1 EntryLo0, MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

Fill field. fields are are fields mented. XI otherwise not imple- SmartMIPS SmartMIPS If not imple- If not ASE; Optional location is part is part location of the mented, this bit bit this mented, and and Yes CDVG Release 2 Required? 65 3210 33 10 ))..6 = 34 = = 11 ged Resource Architecture, Rev. 6.02 = PA R 0 Required if RI 29 6 PA BI T S R/W 0 Required by Write Reset State Compliance Example: Read / Read 6..6 if PA(29-(34- BI T S 29..6 if PA BI TS EntryLo )) bit of bit bitwritable is = 34 = 11 to read data on RI RI register register is set. If PABITS for more information. Example: Fill Field Fill Field PFN ange as a function of the PFN B Invalid or a TLBRI excep- or a TLBRI Invalid B register fields.

Corresponding EntryLo FieldRanges Bit is not set, the the is not set, l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 31..7 if PageGrain 31..30 if PA BI T S SM Description is set to zero on any write to the the to on write to zero any is set (Valid) bit is set. The The is set. bit (Valid) . See Table 9.8 . See V Config3 PageGrain > 10 PABITS 31..(30-(34- or RIE bit of the EntryLo1 Value PA BI TS RXI bit of bit PA BI T S

 RIE PABITS tion, even if the if the even tion, value of virtual page causes the a TL The boundaries of this field ch load, other than a MIPS16 PC-relative only if the the the / EntryLo0 written. regardless value of the register, the by denoted is existence its and is optional bit This Config3 Table 9.8Table (Continued) of PABITS Function as a Field Widths EntryLo Yes 34 Figure Figure 9-6 Architecture of the 3 in Format Release Register EntryLo1 EntryLo0, 1 kB Page Support Support Enabled? Fields

RI 31 Read Inhibit. an If this attempt, bit is set in a TLB entry, Fill 31..30read. on zero on write and return ignored bits are These 31 30 29 Name Bits RI XI Table 9.9 Table Architecture 3 of the Release in Field Descriptions EntryLo1 Register EntryLo0, 128 MIPS® Architecture Vo For Programmers

32 Fill field. MMU) and otherwise SmartMIPS SmartMIPS If not imple- If not ASE; Optional location is part is part location of the mented, this bit bit this mented, 36 35 ture, Rev. 6.02 Rev. ture, 129 EntryLo0[35] 65 3210

is PFNX R/W Undefined Required R/W Undefined Required R/W UndefinedR/W Undefined Required R/W Undefined Required Required (TLB R/W 0 by Required Write Reset State Compliance ed Resource Architec ed Resource Read / Read PFNX

field 9.7 EntryLo0, EntryLo1(CP0 Registers 3,and 0) Select 2 m Release 1. 1. m Release m Release 1. 1. m Release 1. m Release PageGrain isnot set, the from Release 1. 1. from Release = 1),the PFN field below. = 0), the PFN the 0), = (Valid) bit is set. The (Valid) ). ESP bit of the V for more information. ESP ange as a function of the PageGrain PFN C D V G is set any write to zero on the address (the physical ge causes a TLB Invalid or Invalid a TLB ge causes to the virtual page. to the XIE 11 10 register fields.

of the address. physical Table 9.12 d is unchanged fro d is unchanged fro d is unchanged fro bit of SM eld is unchanged Description PageGrain XIE EntryLo1 PageGrain / III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: . See Table 9.8 . See , specificallyto MIPS32 support for XPA36bits), (PA > shows and itthe natural Config3 above. above. above. above and and above = 1 and = 0 or or 55 54 SP SP SP EntryLo0 PA BI TS RXI Table 9.10 Table 9.6 Table 9.6 Table 9.6 Table 9.6 bit is writable only if the is writable bit of bit Figure 9-7Figure 5 in Release Format Register EntryLo1 EntryLo0, See See See value of corresponds to bits 35..12 to bits 35..12 corresponds The boundaries of this field ch See field isshifted leftrelative by 2 bits theto Releasedef- 1 inition to make room for PA corresponds to bits 33..10 of to bits 33..10 corresponds If the is not enabled processor to 1 support kB pages (Config3 page number corresponding page number corresponding pages kB 1 enabled to support is the processor If (Config3 register is set. If the register attempt to fetch an instruction or to load MIPS16 PC-rel- MIPS16 load or to instruction an fetch to attempt pa virtual the from data ative exception,a TLBXI even if the XI XI to the register, regardless of the value written. of the value regardless register, the to the by denoted is existence its and is optional bit This Config3 Fill applies to Fields Figure 9-7 EntryLo1[35]. upper limitof XPA. If only 40-bit XPA is supported, themost-significant of bit XI C 5..3fi of this definition The D 2 of this fiel The definition VG 1 of this fiel The definition 0 of this fiel The definition XI 30 an a TLB in entry, If this bit is set Inhibit. Execute PFN 29..6 This field contains the physical Page Frame Number. 31 30 29 63 Name Bits RI Table 9.9Table 3 of the Architecture Release in Field Descriptions Register EntryLo1 EntryLo0, MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

otherwise otherwise otherwise SmartMIPS SmartMIPS ASE; Optional XPA; Optional Optional XPA; XPA; Optional Optional XPA; ged Resource Architecture, Rev. 6.02 R 0 Required for R/W 0 Required by R/W Undefined Required for Write Reset State Compliance Read / Read -1..10 of -1..10 bit of bits =1. bitwritable is  to read data on RI PAB I TS RI MVH =1 and =1 register register is set. If = 0), these bits are =1), the combined the combined =1), = 0), the= 0), combined LPA for more information. ESP ELPA ESP ange as a function of the ange as a function of the ts as must be written XPA, MTC0 is required to required MTC0 is XPA, ess, thereby providing up up thereby providing ess, Config5 addresses is not enabled is not enabled addresses B Invalid or a TLBRI excep- or a TLBRI Invalid B register fields.

page frame number corre- frame number page is not set, the the is not set, l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. PageGrain Config3 tension. If the tension. is processor SM Description is set to zero on any write to the the to on write to zero any is set PageGrain PageGrain PageGrain (Valid) bit is set. The The is set. bit (Valid) =1) this field is concatenated with the the with concatenated is field this =1) . See Table 9.11 . See . V Config3 PageGrain fields corresponds to 0b00 fields corresponds to 0b00 fields corresponds to bits to corresponds fields = 0 or = 1 and = 0 or or ELPA RIE bit of the EntryLo1 LPA SP SP SP PFN PFN PA BI TS PA BI TS RXI ). bit of bit -1..12 of the physical (the field is address  

RIE 11 10 unshifted and the upper two bi and the unshifted PA BI TS zero). The boundaries of this field ch value of If support for large physical If support for large (Config3 The boundaries of this field ch The boundaries of this value of enabled to support XPA ( enabled to support XPA ignored on write and return 0 on read, thereby providing read, thereby providing on write and return 0 on ignored of implementations with compatibility backward full Architecture. the 1 of Release 5 pre-Release with compatibility backward ensure To software that does not support If the is not enabled processor to 1 support kB pages (Config3 PFNX zero out the extension bits if If not implemented, then reads of this field return 0. field to form the full form the to PFN field physical addr sponding to the to 59 bits of physical address. pages kB 1 enabled to support is the processor If (Config3 PFNX rel- 2 bits by left is shifted address (the field physical the for to make room nition 1 defi Release the to ative PA PageGrain load, other than a MIPS16 PC-relative if the even tion, the virtual page causes the a TL only if the the the / EntryLo0 written. regardless value of the register, the by denoted is existence its and is optional bit This Config3 Fields RI 31 Read Inhibit. an If this attempt, bit is set in a TLB entry, Fill 63..55read. on zero on write and return ignored bits are These PFNX 54..32 Page Frame NumberEx Name Bits Table 9.10Table 5 of the Architecture Release in Descriptions Field Register EntryLo1 EntryLo0, 130 MIPS® Architecture Vo For Programmers

MMU) otherwise SmartMIPS SmartMIPS ASE; Optional ture, Rev. 6.02 Rev. ture, 131 fined Required (TLB can never be larger than 36 can never be larger PABITS W Undefined Required R/W Undefined Required R/WR/W Undefined Undefined Required Required R/W 0by Required Write Reset State Compliance ed Resource Architec ed Resource Read / Read

field fields as a function of 1 kB page support enabled, and the 9.7 EntryLo0, EntryLo1(CP0 Registers 3,and 0) Select 2 PageGrain isnot set, the PFN from Release 1. 1. from Release R/ d from Release 1. R/W Unde = 1),the PFN field y the second row of the table applies in Release1. in table applies row of the the second y , and nged from Release 1. nged from Release 1. nged from Release 1. = 0), the PFN the 0), = (Valid) bit is set. The (Valid) ). ESP bit of the bit of the plementations of the Architecture, V ESP ange as a function of the PageGrain the address (the physical ge causes a TLB Invalid or Invalid a TLB ge causes PFNX to the virtual page to the XIE 11 10 register fields. ,

of the address. physical field contains field contains the physical Fill bit of SM Description field is unchanged PageGrain XIE is set to zero on any write on EntryLo1 write set to zero is any PageGrain / III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: . Config3 = 1 and = 0 or or SP SP SP EntryLo0 PA BI TS RXI bit is writable only if the only if the is bit writable of bit value of corresponds to bits 35..12 to bits 35..12 corresponds The boundaries of this field ch field isshifted leftrelative by 2 bits theto Releasedef- 1 inition to make room for PA corresponds to bits 33..10 of to bits 33..10 corresponds If the is not enabled processor to 1 support kB pages (Config3 If not implemented, then reads of this field return 0. register is set. If the register attempt to fetch an instruction or to load MIPS16 PC-rel- MIPS16 load or to instruction an fetch to attempt pa virtual the from data ative exception,a TLBXI even if the XI XI written. of the value regardless register, the to the by denoted is existence its and is optional bit This Config3 page number corresponding page number corresponding pages kB 1 enabled to support is the processor If (Config3 , in Release 5. Notein im that 5. , in Release shows the movement of the Fields Table 9.11 value of PABITS bits and there is no support for 1 kB pages, so onl C 5..3 of this definition The DVG 2 1 of this field is uncha The definition 0 of this field is uncha The definition The definition of this field is unchange XI 30 an a TLB in entry, If this bit is set Inhibit. Execute PFN 29..6This Page Frame Number. Name Bits Table 9.10Table the Architecture 5 of in Release Descriptions Field Register EntryLo1 EntryLo0, MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

reg- Release Release 2 Release 5 Release 1 Release 5 Config Required (Release 5 for if this sequence is if software if uses a PFNX 33 10 35 12 35 12 33 10 ))..6 ))..6 = 36 = 34 = 11 = 13 field of the of the field operation must be carried = PA = PA = PA = PA K0 ed with a C field encoding th zero, and the TLB must be 29..6 29..6 PABITS PABITS 29 6 29 6 29 6 29 6 PA BI TS Example: Example: UNDEFINED UNDEFINED 6..6 if PAB I TS 6..6 if if 6..6 PAB(29-(36- I TS PAB(29-(34- I TS 29..6 if 29..6 if ged Resource Architecture, Rev. 6.02 EntryLo EntryLo EntryLo EntryLo is mandatory. Instead,software mustinvali- mandatory. is registers and the and registers 59 34 59 36 = 59 = 35 = 59 = 37 ))..32 ))..32 EHINV lease prior to Release 6), the lease prior to Release = PA = PA is changed. This register =1. EntryLo1 PAB I TS Field Field 56 32 54 32 re instruction) that was creat Example: Example: EntryHI registers must be written wi and EHINV Displaced by the Fill Fill by the Displaced Fill by the Displaced PA(56-(59- BI T S PA(54-(59- BI T S 33..32 if PAB33..32 I TS 56..32 if 54..32 if PAB54..32 I TS if PAB32..32 I TS PageGrain EntryLo EntryLo EntryHI EntryLo1 EntryLo0 )) )) )) )) and = 35 = 36 = 59 = 34 = 37 = 59 tions, the operation of the processor is processor the tions, the operation of Corresponding EntryLo Field Bit Ranges on. In Release 6, hardware must ignore writes of unsupported values of the PA BI TS PA BI TS PA BI TS PA BI TS = 11 = 13 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. PAB I TS PAB I TS PAB I TS PAB I TS PAB I TS PAB I TS field of the field of EntryLo0 C Example: Example: Example: Example: Fill FieldFill Field PFNX Field PFN PA BI TS PA BI T S 63..32 & 29..7 if 63..32 & 29..7 if 2 of the Architecture (and any re (and any 2 of the Architecture 63..33 if 63..32 if 63..57 if 63..32 if 63..33 if 63..55 if apped address space. The operation of the processor is of the processor space. The operation address apped > 12 63..(32-(36- > 34 63..(57-(59- > 10 63..(32-(34- > 36 63..(55-(59- fields of both fields of the Value PFN PAB I TS PAB I TS PAB I TS PAB I TS

    lists the encoding of the the lists PABITS 36 36 34 Table 9.11Table 5 in Release of PABITS a Function as Field Widths EntryLo not done. For Release 6, this is not a requirement because support for flushed before each instance in which the value of the Table 9.12 MIPS32) and out while running in an unm ister. An implementation may choose to implement a subset of the cache coherency attributes shown, but must imple- but shown, attributes the cache coherency implement a subset of choose to An implementation may ister. mentencodings encodingsalways at least cantheseon depend appropriately. workingsoftware 2 and 3 such that In other cases of Pre-Release 6 implementa C field for the implementation. C field for TLB mappingfor an instructiona load/sto (either for fetch or for the implementati RESERVED which is Programming Note: Programming Release of implementations In . date the TLB entries explicitlyTLB entriesdate the using TLBWI with No 59 Yes 59 Support Support Enabled? 1 kB Page 132 MIPS® Architecture Vo For Programmers

ture, Rev. 6.02 Rev. ture, 133 ed Resource Architec ed Resource 9.7 EntryLo0, EntryLo1(CP0 Registers 3,and 0) Select 2 r the cacheability and coherency attributes. tion-dependent usetion-dependent usetion-dependent usetion-dependent use Optional tion-dependent use Optional tion-dependent use Optional Optional Optional Optional With Historical With Usage Compliance III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Cacheability and Coherency Attributes Table 9.12Table Attributes and Coherency Cacheability 012 • for implementa Available 3 • for implementa Available 4 • Uncached5 • Cacheable6 • for implementa Available 7 • for implementa Available • for implementa Available • for implementa Available Required Required lists the required and optionalrequired and lists the encodings fo C(5:3) Value Table 9.12 MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 134 MIPS® Architecture Vo For Programmers

0 Optional register fields. fields. register VPId ture, Rev. 6.02 Rev. ture, 135 0 Reserved nally set ware or exter- ware Global Number 8 7 location of software threads from vir- from threads software location of R hard- by Preset ed Resource Architec ed Resource describes the describes 12 11 the maximum virtual processor count in any core in ASE) in a clusterin from can be derived a the contentsASE) of Table 9.13 Table 9.8NumberRegister3, Register 1) Select Global (COP0 optionally can Themethod must be uniformly applied to all virtual proces- gister Field Descriptions gister 6 core implements multi-threading. 6 core implements register; mberingvirtual of processorsa cluster. in n be or preset, eld are not writeable; reads not writeable; eld are ClusterNum Reserved CoreNum ores with different thread counts). ores with different ally programmable. This allows for real This programmable. ally COP0 Register 3, Select 1) 3, Select COP0 Register eassigning the VPNum to thevirtual processor. Description Read/Write Reset State Compliance 20 19 16 15 Global Number III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: ber asssigned to a cluster sys- ber asssigned to a cluster of cores in the Figure Figure 9.8 Format Register Number Global Table 9.13Table Re Global Number Optional Release6

register is required if a Release tem. Reserved if clustering is not implemented. is not clustering if Reserved tem. Unimplemented bits in the fi 0. return but ca read-only, field is This be programmed by a register external to COP0 to COP0 through a be programmed by a register external memory mapped register. for examples. Reserved shows the format of the Global Number a cluster. This results in non-contiguous nua cluster. with heterogenous multi-threading (c Table 9.14 Fields The naming convention is hierarchical.unique Thein virtualis the systemClusterNum.VPNum. name of processor a extern be can indicated where The fields See tual processor to virtual processor by r ClusterNum is optionalandrequired only thata system in supports clusters of cores. Figure 9.8 The unique name of a virtual processor (VPNum;see COP0 EB twotheby methods one of this register described below. • VPNum = CoreNumX Max-VP or VPId, where Max-VP is sors in the system. sors in the • VPNum = CoreNumThis methodVPId. allows + for contiguous numberingofprocessors a cluster in virtual Compliance Level: The 0 15:12 0 Reserved. 0 31:20 0 Reserved. 0 Reserved 31 Name Bits ClusterNum 19:16 A unique num 9.8( Register Number Global MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

Required Required nally set nally set ware or exter- ware ware or exter- ware ged Resource Architecture, Rev. 6.02 R hard- by Preset R hard- by Preset 0, 1, 2, 314, 15 13, 12, . 3 0, 1, 2, 33 2, 1, 0, . is dependent is dependent optionally can optionally can Field Descriptions (Continued) Field Descriptions icalcore in a cluster. lemented bits bits lemented contiguous numbering is contiguous numbering a virtual processor in a core. a virtual a phys n be or preset, n be or preset, eld are not writeable; reads writeable; not eld are eld are not writeable; reads writeable; not eld are en VPId en VPId size equals l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. VPId VPNum VPId VPNum Description Read/Write Reset State Compliance Contiguous NumberingContiguous Numbering Non-Contiguous (total VP count in cluster) ) (total VP Table 9.14Table VPNum Unique Deriving 2 supported. If contiguous, If contiguous, supported. th on whether contiguous or non- or on whether contiguous If non-contiguous, then VPId size equals equals VPId size then If non-contiguous, ceiling (log any core) log2 (maximum VP cont of This field is read-only, but ca read-only, field is This be programmed by a register external to COP0 to COP0 through a be programmed by a register external memory mapped register. return 0. The number of unimp of number The 0. return Unimplemented bits in the Unimplemented bits in fi Unimplemented bits in the Unimplemented bits in fi 0. return but ca read-only, field is This through a to COP0 external be programmed by a register memory mapped register. Table 9.13Table Register Number Global 0121 43 4 6 2 0 8 1, 2, 3 0, 4 3, 41, 2, 0, 5, 6, 7 4, 4, 510 9, 7, 8, 0, 1 4,5 CoreNum of VPs # Fields VPId 7:0 number assigned Ato unique Name Bits CoreNum 11:8 number assigned A unique to 136 MIPS® Architecture Vo For Programmers

field is describes describes 0 =0 PTEBase SM =0 43 0 Table 9.15 ture, Rev. 6.02 Rev. ture, 137 a TLB miss, the operat- a TLBmiss, the SM =0; SM register duplicates some of register. The register. a way that the operating system register can pointregister can to any power-of- =0 and =0 and Config3 Config3 e page table entry (PTE) array. This e page table entry (PTE) array. Context Context riate shifting and masking. =0 and Config3 =0 R Undefined Required CTXTC Context , TLB Invalid, or TLB Modified) causes error exception and this field may be modi- R/W Undefined Required Write Reset State Compliance ed Resource Architec ed Resource =0 and Read / Read CTXTC 9.9 Context RegisterRegister (CP04, 0) Select CTXTC field of the otherwise. BadVPN2 =0. Config3 SM BadVPN2 register is organized in such in is organized register Optional r implementedthe by refillafter approp handler Config3 Register as a pointer pointer a as Register Context containing a in pointer to an entry th returns zero on read. on returns zero 0 0 Reserved Register when of the virtual address that register. register. Context =0 and e in memorye in thatmapping. describesthe For PTE structuressizes, other of by hardware on a TLB exception. TLB exception. on a hardware by Description 31 13 e by the operating system and is =0 then a TLB exception (TLB Refill exception (TLB a TLB =0 then Context =0 then the Register 4, Select 0) 4, Select Register register is not defined after an address CTXTC III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: =1 then the pointe SM SM BadVAddr SM for TLB-based MMUs; for TLB-based data structurethat stores virtual-to-physical translations. During address error exception sequence. error address Context Config3 23 22 Config3 Config3 Config3 normally written with a value that allows the operat- the allows that value a with written normally to use the system ing in memory. array PTE the current into VA It contains bits exception. the caused Required

=0 and =1 or =0 and =0 and field of the of the virtual address to be written into the register is a read/write register a register is register fields CTXTC shows the format of the CTXTC CTXTC Figure 9.9Figure Config3 when Format Register Context PTEBase 31..13 Context BadVPN2 Context Fields Config3 Config3 Config3 Table 9.15Table Config3 when Field Descriptions Register Context The ing system loads the TLB with the missing translation from the PTE array. The systeming loads the withTLB the missing translationPTE array. from the array is an operating system If If

Figure 9.9 fied byfied hardware duringthe the informationprovided inthe can directly reference a 16-byte structur reference can directly TLB by the this register can be used the content of If bits VA two-sized PTE structure within memory. This allows This TLB refill theusepointertheto handler without additional withintwo-sized structure PTE memory. written andwritten used by the operating system. The Compliance Level: the 0 3..0 zero; as be written Must Name Bits 31 PTEBase 31..23us for field is This BadVPN2 22..4 This field is written MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.9 (CP0 Register Context

, the 31:31-((X- describes 0 =1 SM ContextConfig YY-1 0 =1 Table 9.16 ). Although the fields ). Although the fields SM =1; 31:13 State Compliance Reset SM y in a two-levely in lookup scheme. of the contents of the contents of the =1 or Config3 ftware, and are unaffected by the unaffected are ftware, and Config3 ged Resource Architecture, Rev. 6.02 R Undefined Required R/W Undefined Required Write =1Config3 or Read / CTXTC =1 or register, it may point topair 8-byte an of 32- register, Invalid, or Modified) causes bits VA causes bits Modified) or Invalid, CTXTC of register, where this range corresponds to the corresponds to range where this register, CTXTC . Context 32 nomenclature is retained. Bits 31:X are referred to as Config3 BadVPN2 ContextConfig =1. following a modification 31:31-((X-Y)-1) first level page directory entr SM If = X 23 and Y = i.e. bits4, 22:4 are set in register (bits 22:4 are filled with VA register (bits 22:4 are BadVPN2 system to use the the use to system by the operating system ontaining the virtual register. Bits 31:X are R/W to so Bits 31:X are R/W to register. n n by hardware on a TLB Config3 Description Context Register when l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. =1 or Register as a pointer to an array of to an array a pointer as Register Context ContextConfig CTXTC =1 then the a TLB exception (Refill, then the a TLB exception =1 Y are referred to as exception. It contains bits VA It contains bits exception. This field is for use for This field is and with a is normally written value that allows the operating Context to corresponding data structures in memory address region c the address which caused the exception. writte is field This the virtual address that caused the exception. address that caused the virtual the SM X X-1 Config3 register is UNPREDICTABLE Config3 Context =1 or register. field, and bits X-1: bits and field, =1 then Bits Y-1:0 will always as 0. read Y-1:0 Bits =1 then shows the format of the the shows register fields CTXTC SM Figure Figure 9.10 Config3 when Format Register Context where X in {32..1} and Y in {31..0}. be null. May X in {31..0}. be null. May PTEBase Fields to be written to a variable range of bitsto of the “(X-1):Y” be writtenrange of a variable to Context PTEBase Table 9.16Table when Config3 Field Descriptions Register Context Config3 Config3 contiguousbitsof set range in the The value of the bit PTEs withinbit PTEs a single-level pagetable scheme, or to a If If behavior is identicalbehavior to the standard MIPS32 exception. Bits Y-1:0 are unaffected by the exception. unaffected are Y-1:0 Bits exception. ContextConfig shifting and maskingDepending steps. onvalue the in the Y)-1)

Figure 9.10 Figure the have been made variable in size and interpretation, the MIPS the Name Bits 31 PTEBase where 31:X Variable, BadVPN2 (X-1):Y Variable, 138 MIPS® Architecture Vo For Programmers

Reserved =1 (Continued) ture, Rev. 6.02 Rev. ture, 139 or or SM State Compliance Reset 0 (if R) 0 (if R/W) Undefined =1) or or for for only R/W (R/W Write Read / allowed allowed Config3 CTXT =1 or Config3 ed Resource Architec ed Resource CTXTC 9.9 Context RegisterRegister (CP04, 0) Select Description III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: eld Descriptions when when Config3 eld Descriptions Must be written as zero; returns Must be written as zero; zero on read. R be null. where Y in {31:1}. May Fields 0 (Y-1):0 Variable, Name Bits Table 9.16Table Fi Register Context MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 140 MIPS® Architecture Vo For Programmers

reg- Context ContextConfig register fields. register fields.

SM e bit cause the corre- the bit cause e ture, Rev. 6.02 Rev. ture, 141 P0 Register 4, Select 1) Config3 then the least significant significant then the least be extracted. Bits above the be extracted. Bits above der bitsof the virtual address or ContextConfig e lefte of the most- significant of the smallest of the implemented en the settingen not is imple- field. Bits below the selected field below the selected field field. Bits field cannot contain address bits register configuration. CTXTC tting is implementedby writing that BadVPN2 Context Config3 e least-significant on PTEBase describes the ed Resource Architec ed Resource BadVPN2 ware and unaffected by TLB exceptions. ware and unaffected page pairs used by the JTLB entries. This limitsThis thethe by JTLB entries. used page pairs register may be programmed.of set bits The register are R/W for software and unaffected by TLB software and unaffected R/W for are register ofvirtual thatwill address register, in which some number of bits are read-only register, and 9.10 ContextConfig Register (C register. The register. register into which the high or c what value is read back wh value is c what Context e least significant one bit causes the corresponding original written value. All implementations of the Config Register; Table 9.17 to the bits that represents Context ContextConfig by TLB exceptions. Any zero bits to th to zero bits Any by TLB exceptions. ContextConfig registerto bitssoft to be R/W (CP0 Register 4, Select 1) 4, Select (CP0 Register implemented page size is 4 kB, virtual address bit 13 is the least significant bit ContextConfig ware can determine whether a specific se ware can determine whether a specific field.bits Any zeroright to the of th ContextConfig field within the fected by TLB exceptions. fected by TLB III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: would correspond to virtual address bit 11. wouldcorrespond tovirtual address bit 11. Context register are R/W register to software and serve as the

BadVPN2 VirtualIndex Optional.

Context ContextConfig register is optional and its existence is denoted by the registerthe defines of the bits register bits to be unaffected bits to be unaffected register field. Another field. example:theif smalle 1 kB was implemented page size st define the register’s register’s register will be unaf is set, then zero bits any to the right of th

shows the formats of the of the the formats shows SM Context BadVPN2 Context ContextConfig ContextConfig Config3 exceptions. The of the If one bit causethecorresponding registerthe must emulationfor allow MIPS32/microMIPS32 of the fixed writable bit within ContextConfig ContextConfig Compliance Level: The Figure 9.11 Figure page size. For example, if the smallest if the smallest page size. For example, of the sponding The field tofield contain The the virtualindex address defined is singlecontiguous blocka by of non-zero bits withinthe This paragraphdescribes restrictionsthe on how causing a TLB exception will be written, and how many bits selected field of the selected field of the the register value. If the read value matches the original written value exactly, the original written value exactly, the register value. If value into the register and reading back the read value matches then the setting is supported. It is implementation specifi set to one or zero as appropriate. Soft appropriate. as zero set to one or ister bitsto be read as zero. ister It permissible is to implement a subset of the which to index are used memory a locationwithin the even-odd least significant writablebit within A valueof all zeroes meansthat the full 32bits of the mented except that the read value does not match the MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.10 Register ContextConfig

0 State Compliance Reset ged Resource Architecture, Rev. 6.02 R/W 0x007ffff0 Required Write Read / gister Field Descriptions Descriptions Field gister register to be writ- register values. VirtualIndex the virtual address causing virtual address the

Context if non-con- UNDEFINED if into the register field. the into tiguous causes tiguous 1 bits in this field Description l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. ContextConfig Figure 9.11Figure Format Register ContextConfig Page Table Page Table Organization Size Page PTE Size Compliance Table 9.18 Table Values ContextConfig Recommended the corresponding bits of the bits of the corresponding the bits high-order of ten with the a TLB exception. a TLB Behavior of the processor is written 1 bits are tiguous Table 9.17Table Re ContextConfig Value describes some describes useful 0x007ffff00x007ffff8 Level Single Single Level 4K 2Kbits/page 64 bits/page 32 REQUIRED RECOMMENDED Fields Table 9.18 Name Bits 31 VirtualIndex 31:0 0 mask of A to 32 con 142 MIPS® Architecture Vo For Programmers

0 ture, Rev. 6.02 Rev. ture, 143 to unprivileged software register fields. d conditionally readable d conditionally readable via register contains register contains a pointer to a register must be set to a 1 to enable UserLocal R/W Undefined Required Write Reset State Compliance Read/ UserLocal ed Resource Architec ed Resource HWREna describes the describes ation and make it accessible it and make ation 9.11 UserLocal RegisterRegister (CP04,2) Select rpretedby the hardware an register field is field is set. register register is instantiatedper TC.

must be 1. ULRI Table 9.19 ULRI . Config3 UserLocal UserInformation register; Config3 information that is not inter- information

Description ster with arbitrary inform some operating environments, the UserLocal Recommended III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Required Figure 9.12Figure Format Register UserLocal Table 9.19Table UserLocalRegister Field Descriptions ster is mandatory, and ster is mandatory, Release 6: Release 6: preted by the hardware. the preted by Pre-Release 6: Pre-Release register is a read-write register thata read-write is not interegister register is shows the format of the the shows 31..0software This field contains UserLocal Fields the RDHWR instruction. theimplemented, Module MIPS®If is MT the Figure 9.12 Figure Priorthis to Release 6, register only exists if the thread-specific storage block that is obtained via the RDHWR register. obtained is storage block that thread-specific For Release 6, this regi For Release 6, this via register 29 (ULR) of the RDHWR instruction. To do so, bit 29 of the via register 29 (ULR) of the RDHWR instruction. To Programming Notes Programming Privileged software may write this regi

unprivileged access to the register. In unprivileged access to the register. The Compliance Level: Name Bits mation 31 UserInfor- MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.11 4, Select 2) Register Register (CP0 UserLocal ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 144 MIPS® Architecture Vo For Programmers

0 register registers MIPS specific be present if be present DRSEG ture, Rev. 6.02 Rev. ture, 145 Debug ContextID ContextID Debug rporated into t switch, but may be any be any sup- may but t switch, int. The value programmed int. The value ent the register =0. R/W Undefined Required Write Reset State Compliance Read/ DM describes the ed Resource Architec ed Resource Debug 9.12 Debug4, ContextID 4) Select Register (CP0 Table 9.20 ocess specific tag to be inco specific tag to ocess register do not have any side-effects on processor oper- processor on register have do not any side-effects gister Field Descriptions gister restored on a process contex a process restored on register; Release 6. Release trace, PC-sample and breakpo ID =1. However, it is not a requirem However, =1. kernel-mode when kernel-mode EP g specifically for use in hard- g specifically EJTAG Specification i.e., it is not part of the set of part of the set i.e., it is not Specification EJTAG Optional Description Register 4, Select 4) 4, Select Register Config1 Debug ContextID ContextID Debug III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Pre-Release 6; Pre-Release Figure 9.13Figure Format Register ContextID Debug =1. It is accessible in It is accessible =1. at can assist debug. at DM Table 9.20Table Re ContextID Debug ware debug mechanisms. ware software May be used by kernel for debug pur- to inject any supplemental information poses. Debug =1. shows the format of the EP Fields Other thanbeing factoredintodebug hardware, writes to this plemental information th ation. Nor is this register to be used to observeof processor operation. side-effects ofThis register the as part defined is also not Compliance Level: Reserved Debug ContextIDDebugis programmedprovidekernel to by the a pr examples being debug related mechanisms, hardware wouldsaved/ typicallysuchuniqueprocess and as be to a Config1

fields. Figure 9.13 This register maybepresent only if accessible when accessible ID 31:0 Provides a process specific ta Name Bits 31 MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.12 (CP0 ContextID Debug ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 146 MIPS® Architecture Vo For Programmers

0 ture, Rev. 6.02 Rev. ture, 147 shows the format of the 0 to the TLB. It holds a comparison the TLB. It holds a to Figure 9.14 Figure . ed Resource Architec ed Resource Table 9.22 R/W Undefined Required Write Reset State Compliance Read / Read MaskX otherwise. 9.13 PageMask RegisterRegister (CP05,Select 0) 13 12 11 10 . introduces optionalsupport for small whereas pagesizes, Mask register fields. ster Field Descriptions Field Descriptions ster Optional PageMask used for reading from and writing reading from and used for [14:13] is read-only ate in the TLB match. match. TLB in the ate PageMask l 1s to determine the the determine 1s to l example, if 4 kB pages at are read-only read-only 0, at are and in the implementation in the implementation Description PageMask ze for each TLB entry, as shown in ze for each TLB entry, III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Mask ported pages must be continuous. Figure 9.14Figure Format Register PageMask describes the describes for TLB-based MMUs; for TLB-based Table 9.21Table Regi PageMask most-significant bits th indicates that the corresponding bit of the virtual bit of corresponding that the indicates not address should particip small for the support optional 6 makes Release page sizes 4 Corresponding from kB onwards. disabled pages bits for For 1. must be read-only are disallowed, sup- of the range can determine 1s. Software al writing pages by ported bits least-significant 0s all determine to writing read-only are 1s within that Required Table 9.21

register is a read/write register read/write register is a register; PageMask Fields The mask that sets the variable page si page variable the mask that sets

prior to Release 6, all page sizes from 4 kBmuston6, all pagesizes from be supportedto Release implementa-prior themaximum the up to for size page sup range of the tion; however, Release 6 removes supportremovesRelease for Release 6 6 also 1 kB pages. PageMask Compliance Level: 0 31 29 28 Mask 28..13bit a “1” which in is a bit mask Mask field The Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.13 5, Select 0) Register Register (CP0 PageMask

2) Required Reserved (Release 6) Required (Release Required (Release

1 0 0 0 field ged Resource Architecture, Rev. 6.02 (See Description) Values for MaskX for Values R R R/W Write Reset State Compliance 0x00x00x3 0x0 0x3 0x3 0xF 0x3 Read / Read 0x3F 0x3 0xFF 0x3 0x3FF 0x3 0xFFF 0x3 0x3FFF 0x3 Fields of the PageMask Register Register PageMask the of Fields = 0 or 1 ) SP SP = 1 and 13 SP SP and subsequent Config3 Config3 at of the Mask field, pages. pages. This field is kB pages with definition with definition pages kB PageMask l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. Release 6 onwards. Release 6 Description = 0), these bits are not writable, = 1), these bits are writable and and writable these bits are 1), = (lsb of value is located at value is located (lsb of ESP ESP return zero on read, and the effect on the TLB return zero on and the effect read, with written as if they were is on a write entry value 0b11. the must bits these Architecture, 1 of the In Release read, and have on zero be written as zero, return on the translation. address virtual no effect kB 1 6 disallows Release 0 read-only from readable, and their values are copied to and from to and from copied are values and their readable, respec- or read, on a TLB write TLB entry the tively. ( enabled are not If 1 kB pages PageGrain PageGrain releases), the MaskX field is an extension to the to the is an extension field the MaskX releases), 1 to support Mask field to th and action analogous defined above. If 1 kB pages are enabled ( Ignored on write; returns zero on read. on write; Ignored Table 9.21Table PageMask Register (Continued) Descriptions Field 1 kB 4 kB 4 1 MB 4 MB 16 kB 64 kB 16 MB 16 MB 64 256 kB 256 Page Size for Mask field Values 10..0 Table 9.22Table MaskX and the Mask for Values Fields 0 31..29, Name Bits MaskX 12..11the Architecture ( Release 2 of In 148 MIPS® Architecture Vo For Programmers

. A field of Table 9.22 Table MaskX

1 register, then reading register, ture, Rev. 6.02 Rev. ture, 149 = 0 or SP PageMask are implemented. All processors are implemented. All field Config3 by software. Release 6 requires that by software. Release 6 requires fferent value on read. Hardware may read. Hardware value on fferent Mask field as defined in of the Architecture, the size encoding is not implemented by a size encoding is not Values for MaskX for Values is mandatory. Instead, software must invali- must software Instead, mandatory. is ed Resource Architec ed Resource of Release 2 of the architec- of 2 of Release ements that page size. that page ements if software writes the Mask field with a value EHINV 0xFFFF 0x3 =1. 9.13 PageMask RegisterRegister (CP05,Select 0) g bits read-only 1s up to the minimum supported page EntryHi EHINV ) 13 Fields of the PageMask Register (Continued) Register PageMask the Fields of 1 EntryHi value 0b11 if 1K pages are not enabled ( pages are if 1K value 0b11 ones, the processor impl processor the ones, , even if the, evenif hardware returns a di g a value different than that written than that written value different g a illegal or unsupported values to the to 6). Release page If a particular exists only exists only on implementations PageMask if thisnot sequence if done.UNDEFINED is MaskX register must return zeros in all bits that correspond to encodings that are not (lsb of value is located at value is located (lsb of Table 9.22 Table III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: = 0). In Release 6, these bits are reserved. are bits these 6, In Release 0). = PageMask = PageMask register is changed. This operation must be carried out while running in an unmapped address ESP 12 11 must be flushed before each instance in which and the TLB must be flushed before each instance the register must be written with 0b11 256 MB PageGrain Page Size for Mask field Values ture and are treated as if they had the the had if they as are treated and ture PageGrain Programming Note: Programming 1. PageMask SP SP PageMask Table 9.22Table MaskX and Mask the for Values processor, a read of the processor, write of all 1s remains consistent with Pre-Release 6 behavior. write of all 1s remains consistent with Pre-Release 6 behavior. value of the space. The operation of the processor is processor space. The operation of the for not a requirement because support is For Release 6, this Config3 It isIt implementation-dependent how many of the encodings described in 9.22 Table must implement the 4 kB size (prior page In implementations of Release 2 (and subsequent 6) releases prior to Release the date the TLB entries explicitly entriesTLB date the using TLBWI with the value back. If a pair of bits reads back as back of bits reads pair If a back. the value For Pre-Release 6: The operation of the processor is UNDEFINED otherofone thanin those listed depend requirement on this in implementingstructures hardware For Release 6: Hardware ignores of writes implemented, thereby potentially returnin unsupported pagesfromkB 4 onwards have their correspondin size. Software maydetermine whichpagesizes are supported bywriting all ones to the MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 150 MIPS® Architecture Vo For Programmers

0 shows ASE; optional optional Required otherwise, (Release 6) SmartMIPS SmartMIPS Required by Required by (Pre-Release 6) (Pre-Release register is pres- Figure 9-15 ture, Rev. 6.02 Rev. ture, 151 0 1 otherwise. PageGrain (Release6) (Pre-Release 6) In implementationsboth of 8 7 5 4 Optional =1); R Write Reset State Compliance equent releases) of the Architecture that the Architecture of equent releases) Read / LPA register fields. register R/W or R R/W or ed Resource Architec ed Resource (Release 6) (Release (Pre-Release 6) 13 12 Config3 1 kB page support, the XI/RI TLB protection bits, 9.14 PageGrain RegisterRegister (CP05, 1) Select PageGrain d Physical Addressing. The lease 2 of the Architecture. 2 of lease EntryLo1 EntryLo1 for XPA ( forXPA registers is not and and and not writeable and not describes the describes 0 ASE 0 MCCause Required Meaning EntryLo* tence of this bit is denoted . If this bit is not bit in Config3 this If bits . Table 9.23 Table Description bit in the bit of the EntryLo0 the bit of EntryLo0 the bit of III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: RI or RXI RI by software. RI registers is disabled registers is enabled.registers is Figure 9-15Figure Format Register PageGrain for implementationsRelease 2 (and of subs e Check exception, and Extende and e Check exception, SM register; register; 0 1 Table 9.23Table Descriptions Field Register PageGrain for SmartMIPS™ ASE; for SmartMIPS™ S32 Required

Encoding PageGrain implemented. This bit is optional. The exis the by either the then settable, register is a read/write register used for enabling a read/write is register Required PageGrain Fields the format of the the format of include TLB-based MMUs and support 1 kB pages, the XI/RI TLB protection bits, multiple types of Machine Check exceptions;

reporting the type Machinof ent in both the SmartMIPS™ ASE andthe in As such, of the Architecture. Release 2 (and subsequent releases) description belowdescribes only the fields relevant Re to precedence. take definitions the SmartMIPS™the ASE ASE, and of the Architecture Release 2 The Compliance Level: RIE 31 Enable. Read Inhibit Name Bits 31 30 29 28 27 26 25 RIE XIE ELPA ESP IEC 9.14 PageGrain Register (CP0 Select 1) Register 5, MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

Required Required Required (Release 5) (Release 6) SmartMIPS SmartMIPS ASE; other- Required by Required by wise, optional (Pre-Release 6) (Pre-Release 0 1 0 (Release 6) (Pre-Release 6) ged Resource Architecture, Rev. 6.02 0 R R/W 0 Required Write Reset State Compliance Read / R/W or R R/W or (Release 6) (Release (Pre-Release 6)

regis- field to registers register. If If register. EntryLo1 EntryLo1 PFN EntryLo1 EntryLo* and not writeable and not and Config3 = 1. =1, then writes to above Meaning Meaning LPA and EntryLo0 and EntryLo0 and ementations of Release 2 of of Release ementations Release 5 of the Architec- 5 of the Release tence of this bit is denoted Release 5 implementation 5 implementation Release LPA bit in the the in bit l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. EntryLo0 XI bits in the in the bits rge physical addresses. physical rge gnored and reads return and reads 0. gnored return Config3 Description RXI bit of the bit of the bit or XI disabled registers is by software. XI enabled.registers is enabled enabled (XPA) field of the field SM 0 1 01 is not physical address support Large is support address physical Large PFNX is only writeable in a only is Encoding Encoding form the number. page frame full is defined. TagLo LLAddr, ters is writable and concatenated with the the with concatenated and writable is ters his bit is optional. The exis is not implemented. For implementations prior to implementations For by eitherthe ture, this bit zero on returns read. this bit is not settable, the the settable, is not this bit registers or fields are i are or fields registers ELPA i.e., XPA that support T • extension, Access to optional registers COP0 with PA bit is a 0 and Config3If this ASE and are not used in impl in not used ASE and are the Architectureunless suchan implementation also ASE. SmartMIPS™ the implements to Copro- occur the following changes 1, a is bit If this cessor 0 registers: • The Table 9.23Table (Continued) Field Descriptions Register PageGrain Fields XIE 30 Execute Inhibit Enable. ASE 12..8 SmartMIPS™ the of features control are fields These ELPA 29la for Enables support Name Bits 152 MIPS® Architecture Vo For Programmers

Required Required ture, Rev. 6.02 Rev. ture, 153 0 1 (Release6) (Pre-Release 6) R/W 0 Required R/W Write Reset State Compliance Read / ed Resource Architec ed Resource (Pre-Release 6) 9.14 PageGrain RegisterRegister (CP05, 1) Select regis- Mask field EntryLo1 register is writ- is register register is writable is writable register and Meaning Meaning bit exceptions can bit exceptions only the from Release 1 defini- llow the SmartMIPS ASE, ASE, SmartMIPS the llow tion algorithm is modified algorithm is tion EntryHi PageMask turns zero on zero read.turns 0 0 Reserved codes for the Read-Inhibit and codes for Description the virtual address. III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: exceptions both use the TLBL excep- TLBL exceptions both use the tion code. code. exception TLBRI use the Execute-Inhibit exceptions TLBXI exception code field of the = 0, 1 kB pages are not implemented, and = 0, not implemented, 1 kB pages are SP 0 and Execute-Inhibit Read-Inhibit 1 the exceptions use Read-Inhibit 01 is not enabled page support kB 1 is enabled page support kB 1 VPN2X field of the EntryLo0PFN field of MaskX field of the bit is a 1, the following changes occur to copro- occur the following changes 1, a is bit Encoding Encoding to reflect the smaller page page size. the smaller to reflect to form the “don’t care” mask for the TLB entry. to form the “don’t of and bits 12..11 tion). able and is concatenated to the right of the ters holds the physical address down to bit 10 (the the address down to bit 10 holds ters physical by 2 left is bits field shifted Config3 If • The • The virtual address transla cessor 0 registers: • The • The this bit on is ignored write and zero on returns read. If this For For implementations which fo this bit by is ignored the hardware, meaning the Read-Inhibit and Execute-Inhi use the TLBL exception code. Execute-Inhibit exceptions. Execute-Inhibit Must be written as zero; re as zero; written be Must Table 9.23Table (Continued) Field Descriptions Register PageGrain 7..5 Fields 0 25..13, IEC 27 exception Enables unique ESP 28 Enables support for 1 kB pages. Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

needed. needed. wise not of Machine multiple types ported.; Other- Check are sup- are Check itecture, be the following fields must . ged Resource Architecture, Rev. 6.02 R 0 if Optional EHINV Write Reset State Compliance Read / is mandatory. Instead, software must inval- is mandatory. 0 0 EHINV EntryHi out while running in an unmapped address space. The EntryHi flushed before each instance in which the value of the properties of =0 is written into into is written =0 =0 is written into into is written =0 PFN PFNX Meaning if this sequence if is not done. EHINV EHINV release prior to Release 6) of the Arch of the 6) Release prior to release l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. , EntryLo1 , EntryLo1 Description Field Value Required PFN ing TLBWI and the PFNX FTLB but the VPN2 field is con- not by set selected the TLB with sistent register. the Index Dual of Mode Page Directory Level mem- from accessed PTE - PTEs first ory has PTEVld bit set but second does not memory from PTE accessed set. bit PTEVld have power-of-4 size is Huge Page derived but Dual not implemented. Page mode FTLB and PageMask is not set to a that is pagesize supported by the FTLB. EntryHi with tive accesses. The value in EPC might might EPC in value The accesses. tive not point to the faulting instruction. EntryHi with UNDEFINED requirement because support for EntryLo0 EntryLo0 5 and Walker Table Hardware Page For 6 and Walker Table Hardware Page For 4page and FTLB. A VTLB Dual For 01 No Machine Check Reported 2 Hit in TLB(s). Multiple specula- for Hits in TLB(s) Multiple 3page and FTLB. A VTLB Dual For 24-31 specific Implementation Others Reserved Encoding Check Exception. Table 9.23Table (Continued) Field Descriptions Register PageGrain register is register is changed. This operation must be carried Fields For Release 6: This is not a operation of the processor is operationis processor of the written with the specified values, and the TLB must be Programming Note: Programming In implementations of Release 2 (and any PageGrain idate the TLB entries explicitly us idate Name Bits MCCause 4..0 Machine after a . Only valid Cause Machine Check 154 MIPS® Architecture Vo For Programmers

and a PageGrain ture, Rev. 6.02 Rev. ture, 155 ed Resource Architec ed Resource 0 0b11 between the instruction that writes writes that between the instruction 9.14 PageGrain RegisterRegister (CP05, 1) Select must be cleared using the EHB instruction. EHB the using must be cleared MaskX VPN2X Field Value Required III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: EntryHi PageMask is changed, a hazard may be created PageGrain subsequent CACHE instruction. This hazard instruction. subsequent CACHE Note also that if MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 156 MIPS® Architecture Vo For Programmers

0 dent register. register. tion Depen- ture, Rev. 6.02 Rev. ture, 157 Config3 R/WR/W Implementa- Write Reset State Read / otherwise. CFG 0 CFG controlled by a Segment Configuration. 9.15 SegCtl0Register (CP05, Select 2) Optional ed Resource Architec ed Resource entation system. If implemented, the Seg- implemented, If entation system. fined by thePrivileged Resourcetobe Architecturemodi- E in an MT Module processor. processor. Module E in an MT Table 9.27 Table 9.27 16 15 Description Register. Register. registers is denoted by the SC field withinregistersfield is denoted by the SC the . ents. The behavior of each region is is region each of behavior The ents. SegCtl1 SegCtl0 III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: for programmable memory segmentation; registers are instantiated per-VP registers allow configuringthe memory segm Table 9.24Table Descriptions Field Register SegCtl0 CFG 1 Segmentation ControlSegmentation Required Required

Figure 9.16Figure 2) Select 5, Register (CP0 Format Register SegCtl0 EHINV TLB invalidate feature is required by Segmentation Control. The legacy software method of rep- shows the format of the shows shows the format of the the shows Fields CFG 0 15..0 0, see Segment Configuration CFG 1 31..16 1, see Configuration Segment Name Bits Segmentation Control Segmentation Control EntryHi Section 4.10 “Segmentation Control” Figure 9.17 Figure The existence of the mentation Configurations are always active. are always mentation Configurations The address space is split into six segm Figure 9.16 Figure resentingan invalidunmappedTLB entry by using value an address is not guaranteed to work. ComplianceLevel: The The See Segmentation Controlbehaviorsallows address-specific de fied or or disabled. fied The 31 MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.17 4) (CP0 Register 5, Select SegCtl2 9.16 5, Select 3) Register SegCtl1 (CP0 9.15 5, Select 2) Register SegCtl0 (CP0

0 0 dent dent tion Depen- tion Depen- R/W Required R/WR/W Implementa- R/WR/W Implementa- R/W Required Write Reset State Write ResetState Write Compliance Read / Read / Read / CFG 2 CFG 4 CFG ged Resource Architecture, Rev. 6.02 . fined in all CFG fields of the Segmentation Control ntation Control” . R/W Required =1. =1. guration) Field Description Field Description guration) Table 9.27 Table 9.27 Table 9.27 Table 9.27 ERL Table 9.28 Table Segment becomes unmapped 16 15 16 15 Description Description Description for Segment, for use when Segment, for for Status Register. Section 4.10 “Segme l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. SegCtl2 and uncached when and uncached when unmapped. See unmapped. This field is provisioned to mapping of up support to a physical address. 36-bit Table 9.26Table Descriptions Field Register SegCtl2 Table 9.25Table Descriptions Field Register SegCtl1 CFG 5 CFG 3 Table 9.27Table CFG (SegmentConfi Figure 9.18Figure 4) Select 5, Register (CP0 Format Register SegCtl2 Figure 9.17Figure 3) Select 5, Register (CP0 Format Register SegCtl1 shows the format of the the shows describes the CFG(Segment Configuration)fields de Fields Fields Fields 0 8..7 Reserved. R0 Required PA 15..9bits Physical address EU 3 behavior. condition Error AM 6..4 Access control mode. See CFG 2 15..0 2, see Segment Configuration CFG 3 31..16 3, see Configuration Segment CFG 4 15..0 4, see Segment Configuration CFG 5 31..16 5, see Configuration Segment Name Bits Name Bits Name Bits Table 9.27 registers.

Figure 9.18 Figure 31 31 158 MIPS® Architecture Vo For Programmers

0 0 0 0 1 1 EU ture, Rev. 6.02 Rev. ture, 159 el mapped region el mapped modes, with unmapped R/W Required Write Compliance Description Read / 2 3 C

Undefined Undefined Undefined Undefined 9.17 SegCtl2Register (CP05, Select 4) ed Resource Architec ed Resource upervisor and kern field. rvisor mapped rvisor region and kernel AM sed to implement a fully-mapped flat address space address flat a fully-mapped sed to implement upervisor unmapped upervisor region and kernel e.g. sseg in a fixed mapping TLB. e.g. kseg0, kseg1 e.g. kseg0, e.g. kseg3 sseg e.g. ksseg, kuseg, suseg e.g. useg, in user and in user and supervisor appear in regions which kernel mode. CFG UNDEFINED dregion unmapped Unrestricted PA 0x000 0x000 0x002 0x000 n) Field Description (Continued) n) Field Description apped unmapped region Kernel-only Undefined Undefined mode Kernel for use when unmapped. As when unmapped. use for Description Mode mode UK UK AM MK MSK Supervisor Supervisor MUSK MUSK III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Table 9.12 on page Table 9.12 on See by base architecture. defined 133 for the encoding of this field. For Release 6, writes of of 6, writes Release For field. of this encoding the for whereas the field unmodified, leave values unsupported in Release a write 5, such result may in behavior. Table 9.29Table state reset legacy Configuration Segment User mode Action when referenced from Operating Operating from referenced when Action Table 9.28Table Modes Control Access Configuration Segment Table 9.27Table Configuratio CFG (Segment describes a configuration of Segmentation Control equivalent to legacy fixed partitioning. This is a rec- describes the access control modes specifiable in the in modes specifiable control the access describes Fields C 2..0 attribute, coherency Cache Name Bits Mode 0 kseg3 1 ksseg, sseg 23 kseg1 4 kseg0 useg kuseg, suseg, 5useg kuseg, suseg, Table 9.29 ommended reset configuration for conformancewith legacy segmentation.fixed Table 9.28 UK 000 Error Address Error Address Unm CFG Segment MK 001 Error Address Error Address Mapped mapped region Kernel-only USK 101 Address Error Unmapped Unmapped S MSK 010 Address Error Mapped Mapped Supe UUSK 111 Unmapped Unmapped Unmappe MUSK 011 Mapped Mapped Mapped s User, MUSUK 100 Mapped Mapped Unmapped U MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For virtual address range mapped by range mapped virtual address ged Resource Architecture, Rev. 6.02 EquivalentSegment name(s) itioning of MIPS32 address space space address MIPS32 of itioning kseg3 ksseg, sseg kseg1 kseg0 useg, kuseg, suseg e microMIPS32 Address Space and the Space and Address microMIPS32 e l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. through through through through through through FFFF 0xDFFF 0000 0xC000 FFFF 0xBFFF 0000 0xA000 FFFF 0x9FFF 0000 0x8000 FFFF 0x7FFF 0000 0x4000 FFFF 0x3FFF 0000 0x0000 FFFF 0xFFFF 0000 0xE000 Table 9.30Table part Configuration Segment 1 2 3 4 5 0 describes the partitioning of th the partitioning describes CFG Address range Virtual

Table 9.30 each Segment Configuration (CFG). Configuration each Segment 160 MIPS® Architecture Vo For Programmers

0 register con- register . PWBase register specifies the specifies register ture, Rev. 6.02 Rev. ture, 161 State Compliance Reset n of the indexn fields in the table system contains only a register fields. ich are Page Table Entries. ich are Page Table PWSize PWBase Write tries (PTEs). This array is knownistries (PTEs). This arrayas a Read / ed Resource Architec ed Resource describes the the describes 9.18 PWBase RegisterRegister(CP0 5, 5) Select registers. r TLB refills. It is used in combinationTLB refills. It r the with ories. Adirectoryan array of pointers.ories. Each consists of tables - up to four- tables directory levelsplus one page table register specifies the locatio register address. A single-level address. page lowest (leaf) of elements wh =1. PWSize er Field Descriptions er Field Descriptions Table 9.31 PW and Section 4.12Page Table Walker” “Hardware PWField PWBase bits extracted from faulting the The address. se virtual address, used as the starting point for hardware page table y or to a Page Table. Table. a Page to or y Config3 register; PWField Description VPE in an MT ModuleVPE in processor. e system is an array of Page Table En Page Table an array of is e system Register 5, Select 5) 5, Select Register =1. Register 5, Select 6) address pointeraddress R/W 0 Required PWBase PW III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Figure 9.19 PWBase Register Format for the page walker feature. hardware for the walker feature. hardware page Config3 Table 9.31Table Regist PWBase either to another director registers. Required Required Required Required

register contains the Page Table Ba Table the Page contains register register configurespageregister hardware table walkingfo PWSize register is instantiated per-VPE in an MT Moduleprocessor. in an MT register is instantiated per-VPE register is instantiated per- instantiated is register shows the format of the shows and PWField PWField PWBase PWBase PWBase Fields The Page Table and the Directories are indexed by indexed are and the Directories Page Table The Levels above the lowest Page Table level are known as Direct level are known as Table Page above the lowest Levels pointer in a directory is The operation of page table walking is described in faulting address. This register only exists if The existence of thisexistence register of is denotedThe when walking.is incombination It used with the The PWBase Compliance Level: The Compliance Level: The The or Page Table which will be accessed. The tainsbase theofPage Table address the first Directory or number of index bits to be used for each level. The be used of index bits to number single Page Table. A multi-levelthe - tree structure page table system forms a Page Table (PT) and is indexed using bits from the faultingPage Table The hardwareThe page walker feature supportsmulti-level page level.level The lowestpagetabl of any Figure 9.19 Figure Name Bits PWBase 31..0 Base Page Table 31 9.19 (CP0 PWField Register 9.18Register (CP0 PWBase MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

register fields. PWField ware page-tableware walking, auto- the ged Resource Architecture, Rev. 6.02 describes the describes Table 9.32 Register; tected on a read during operation hard l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. PWField shows the formats of the the formats shows mated process a TLB Refill is aborted and exceptionis taken. 9.20 Figure If a synchronousIf exception condition is de 162 MIPS® Architecture Vo For Programmers

GDW UDW 0 MDW Required PWSize PWSize PWSize Required when Required Required when Required when Required is implemented is implemented is implemented PTEI ture, Rev. 6.02 Rev. ture, 163 12 12 12 12 6 5 (Release 6) (Release 6) (Release 6) (Release 6) (Pre-Release 6) (Pre-Release 6) (Pre-Release 6) (Pre-Release 6) PTI R/W 0 R/W 0 R/W 0 R/W 0 Write ResetState Compliance Read / Read ed Resource Architec ed Resource 12 11 9.19 PWField RegisterRegister (CP05, Select 6) t of the index the t of MDI t of the index field the t of s, which is used to index is used to index s, which r of index bits is specified bits is of index r y. The number of index bits y. y. The number of index bits y. y. The number The of index bits y. . . . t significant bit of the index index the of bit significant t ast significant bit of the index 18 17 ast significant bi returns zero on read.zero on returns R0 0 Required UDW MDW GDW Description UDI . x. Least significant bi III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: PWSize PWSize PWSize Figure Figure 9.20 Format PWField Register PTW Table 9.32Table PWField Register Field Descriptions 24 23 PWSize field extracted from the faulting address, which is used to to is used which address, faulting from the field extracted index into the Global Director is specified by is specified by field extracted from the faulting address, which is used to to which is used address, faulting from the field extracted index into the Upper Director field extracted from the faulting address, which is used to to which is used address, faulting from the field extracted index into the Middle Director is specified by Release 6: Entire Release 6: Entire write is dropped if the write value to this field is less than 12. Release 6: Entire Release 6: Entire write is dropped if the write value to this field is less than 12. the pagesize is downgraded If PTI is not a power of four, four. nearest power of to the Release 6: Entire Release 6: Entire write is dropped if the write value to this field is less than 12. Release 6: Entire write is dropped if the write value to this field is less than 12. by into the Page Table. The numbe into the Table. Page extracted from the faulting addres GDI Fields 0 0 31..30 zero; as be written Must PTI 11..6 inde Table Page GDI 29..24 Directory index. Le Global UDI 23..18 Leas index. Directory Upper MDI 17..12 Directory index. Le Middle 31 30 29 Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

. ged Resource Architecture, Rev. 6.02 C, V, G TLB fields are overwritten G TLB fields are overwritten C, V, tries (PTEs). This array is knownistries (PTEs). This arrayas a R/W 2 Required Write ResetState Compliance Read / Read

-2 bits PTEI eld Descriptions (Continued) eld Descriptions Section 4.12Page Table Walker” “Hardware for these cases. ailable values by writing ailable values by writing this A value of 4 means logical 4 A value of the shifted value are rotated rotated are value the shifted unsupported value leaves the value leaves unsupported e RI/XI positions RI/XI positions for the e TLB t value is not available, PTEI programmed so that the entire PFN, PFN, entire the that so programmed multi-levelpage tablesdirectoryto - up three levelsplus one page table l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. Description e system is an array of Page Table En Page Table an array of is e system for the hardware page walk feature. page for the hardware UNPREDICTABLE UNPREDICTABLE registers. Required Required

will remain unchanged. field. If the requested shif register unmodified. Values of 0,1 are unsupported, 2 is register unmodified. Values implemen- and are optional values and all other required, tation-specific. the Software can discover av into position for RI and XI the bit locations protection the entry. TLB within A value of 2 means rotate the right-most two bits into the entry. TLB the for positions bit RI/XI entire bit the by one A value of 3 means logical shift right RI/XI into the twobits the right-most then rotate PTE and positions for the TLB entry. For Release 6, a write of an first. The purpose of this shift is to remove the SW-only shift is to remove the first. The purpose of this SW-only the Then entry. the TLB into be written what will bits from two least-significant bits of the rotate then and PTE by two bits the entire right shift two into th bits right-most entry. 0 are 1 and RESERVED of values 6, the Pre-Release For operation not be used; HW Page and should the of the Walker is Specifies the logical right shift and rotation which will will be which and rotation shift right the logical Specifies Entry values loaded by hardware applied to Page Table page table walking. The entire PTE is logically by shifted right Table 9.32Table Fi PWField Register field can be incorrectly field can be PWField PTEI register configures hardware page table walking for TLB refills. It is used in combination with the and PWSize Fields with zeros by the logical right shift operation. The intention of this facility is to only remove the SW-only bitswithlogical zeros by the of the right shift operation. The intentionfacility this of is to only removeSW-only the valuePTE from the whichbelater will writtenthe into TLB. Compliance Level: PWBase Note that that the Note The The operation of page table walking is described in level.level The lowestpagetabl of any The hardwareThe feature supports page walk PTEI 5..0 Entry shift. Table Page Name Bits 164 MIPS® Architecture Vo For Programmers 9.20 PWSize Register (CP0 Register 5, Select 7)

PWBase register . The field. field. This PWSize PTEW ture, Rev. 6.02 Rev. ture, 165 e locationof the index BadVAddr register fields. table system contains only a table system ich are Page Table Entries. Entries. ichare Page Table PWSize PWSize ze for the refill. For 32-bit addressing, access the Page Table is multiplied by the multiplied is Table Page the access register specifies th ed Resource Architec ed Resource describes the describes 9.20 Register PWSize Register (CP05,7) Select PWField ware-managed fields. ories. A directory consists of an array of pointers.directoryA Eachories. consists of address. A single-level page address. lowest (leaf) lowest (leaf) of elements wh Table 9.33 Table y or to a Page Table. Table. a Page to or y d by bits extractedfrom the faulting address Register; eft shift value) can be specified using the E in an MT Module processor. processor. Module E in an MT ble structure for soft structure for ble are multiplied by the native pointer si native multiplied by the are =1. PWSize PWSize t left shift). The index value used to left shift). The index t PW to be used for each level. The to be used for each III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Config3 either to another director . register is instantiated per-VP shows the formats of the formats the shows BadVAddr PWSize The Page Table and the Directories are indexe The Page Table Levels above the lowest Page Table level are known as Direct known as level are Table Page above the lowest Levels pointer in a directory is pointer in a directory is This register only if exists register contains the base address of the first Directory or Page Table which will be accessed. The accessed. be will which Table or Page Directory the first of base address register contains the Figure 9.21 Figure Index values used to access Directories Directories access used to Index values the native pointer size is 32 bits (2 bi size is 32 bits the native pointer single Page Table. A multi-levelthe - tree structure page table system forms a The Page Table (PT) and is indexed using bits from the faultingPage Table allows space to be allocated in the Page Ta specifies the number bits of index fields in native pointer size. Annative additionalsize. pointer multiplier(l MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

0 PTEW 6 5 ged Resource Architecture, Rev. 6.02 R 0 Required PTW R/W 0 Recommended R/W 0 Recommended Write ResetState Compliance Read / 12 11 MDW e least significant Meaning Meaning Meaning . . . to create an index into the the into index an to create to create an index into the the into index an to create the into index an to create this is to 0. bit this fixed GDI UDI MDI turns zero on turns read. 0 0 Required 18 17 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. Description ndex width. ndex width. R/W 0 Recommended Middle Directory. The least signifi- least The Middle Directory. by is specified of the field bit cant PWField Directory index. BadVAddr Directory index. BadVAddr Directory index. BadVAddr Global Directory. Th Global Directory. by is specified bit of the field PWField significant The least Directory. Upper by is specified bit of the field PWField UDW Figure 9.21 Figure Format Register PWSize 0 No read is performed using Middle 0 No read is performed using Global 0 No read is performed using Upper Table 9.33Table Descriptions Field Register PWSize Value Value Value Non-zero Number of bits to be extracted from Non-zero Number of bits to be extracted from Non-zero Number of bits to be extracted from 24 23 For32-bit the architectures, Fields 0 31 Must be written as zero; re PS 0 architectures. by the 64-bit - this is only used Size Pointer UDW 23..18 Directory index width. Upper GDW 29..24i Global Directory MDW 17..12i Middle Directory 0 PS GDW Name Bits 31 30 29 166 MIPS® Architecture Vo For Programmers

Required PA>32bits PA>32bits Use Case Huge Pages Huge Huge Pages Huge Suggested & PA>32 bits & PA>32 the directory lev- ture, Rev. 6.02 Rev. ture, 167 1 Size Leaf PTE (Release 6) (Pre-Release 6) R/W 0 Required R/W 0 for each pointer in each pointer for Write ResetState Compliance Read / 64 bits 64 bits 32-bit with PTE Size Non-Leaf Non-Leaf ed Resource Architec ed Resource . PTI 9.20 Register PWSize Register (CP05,7) Select 1 settings. 64 bits Directory PWField Pointer SIze Pointer HugePg 0 is ignored; entire Meaning PWCtl account for the native account for the data ilable values by writing this writing ilable values by to create an index into the the into index an to create is implementation-dependent. is implementation-dependent. shift of one must be imple- shift of Pointer Pointer and Addressing Description Table 9.34Table PS/PTEW Usage tes how many bytes of memory is used used is of memory many bytes tes how Release 6: Write of Release 6: Write dropped. write is BadVAddr Page Table. The least significant bit of bit of significant least The Table. Page by is specified the field self, the pointer uses the least significant bytes. uses the least significant the pointer self, PS/PTEW

III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: PTEW 0 Pre-Release 6: UNPREDICTABLE ble index width. PWSize Value PWSize Non-zero Number be of bits to extracted from addition to the shift required to shift required to the addition sizethe of machine. The set of availableshifts ava Software can discover the PTEW not available, shift value is the requested field. If A zero. as written be will mented. Value 0 meaning has changed for Release 6. for meaning has changed 0 Value Table 9.33 Table (Continued) Descriptions Field Register PWSize HugePg describes valid describes PWCtl Fields PS Table 9.34 000 0 00 1 0 1 1 0 32 bits 32 bits 1 32 bits 32 bits 32 bits N/A 32 bits 32 bits N/A 32 bits 32 bits 64 bits 32-bit 32 bits 32-bit with 32-bit with PTW 11..6 Ta Page PTEW 5..0 in index, Table Page the to applied shift the left Specifies N/A N/A >1 Not supported Name Bits els. If this size is larger than the pointerthe than it If this size is larger els. PWSize 1. The “Directory Pointer Size” column deno MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 168 MIPS® Architecture Vo For Programmers

0 Required (Release 6) Wired ware n n-1 ged Resource Architecture, Rev. 6.02 00Reserved 00Reserved Rby hard- Preset Write Reset State Compliance Read/ 0 Limit. Wired. and to is equal and 16 15 =1 or 4. A fixed-size TLB A fixed-size 4. =1 or Meaning able to a variable-sized an implementation-depen- MT =4 does not have wired entries. does not have =4 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. Limit Description MT Config d is determined by determined by d is d is determined by determined by d is Figure 9.23 WiredRegister Format The maximum number of maximum number of The wired of entries may be equal to the number TLB entries minus one. fieldTheis reserved i.e., writesare return 0s. ignored, reads the less than be must which entries, number of TLB entries one. minus number of The wired entries is imple- mentation-dependent Limit. Config Table 9.35Table Wired Register Field Descriptions m m-1 0 6 compatibility. Release Pre > 0 The maximum number of wired Encoding TLB, such asTLB, when such The size of this fiel this of size The are only applic entries Wired The size of this fiel this of size The in the case of of case the in programmed but only Limit may alternatively be programmed but only as specified by the contents of architecturally is not capability this i.e., register dent visible. Attempting to writevaluea greater than Limitinto the be dropped. the write to field causes Wired 0 Fields 0 31. m Must be written as zero; returns zero on read. 0 15..n Must be written as zero; returns zero on read.

Limit m-1..16 below. - table see wired limit TLB Wired n-1..0 wired TLB boundary R/W 0 Required Name Bits 31 170 MIPS® Architecture Vo For Programmers

PWBase register . The PWSize ture, Rev. 6.02 Rev. ture, 171 e locationof the index BadVAddr table system contains only a table system contains ich are Page Table Entries. ich are Page Table register fields. register PWCtl tries (PTEs). This array is knownistries (PTEs). This arrayas a register specifies th ed Resource Architec ed Resource 9.22Register PWCtl Register (CP06, 6) Select describes the the describes PWField TLB refills. It is used in combination with the ories. Adirectoryan array of pointers. Eachories. of consists tables - up to four- tables directory levelsplus one page table address. A single-level page address. lowest (leaf) of elements wh =0. =1. PW Table 9.36 PWEn y or to a Page Table. Table. a Page to or y PWCtl Config3 d by bits extractedfrom the faulting address Register; VPE in an MT Modulean VPE in processor. e system is an array of Page Table En Page Table an array of is e system PWCtl to be used for each level. The to be used for each III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: registers. for the walker feature. hardware page either to another director PWSize Required Required

and . register is instantiated per- instantiated is register shows the formats of the formats the shows register configures hardwarewalking table page for BadVAddr PWField PWCtl The Page Table and the Directories are indexe The Page Table Levels above the lowest Page Table level are known as Direct as level are known Table Page lowest above the Levels pointer in a directory is Figure 9.24 Figure The Page Table (PT) and is indexed using bits from the faultingPage Table single Page Table. A multi-levelthe - tree structure page table system forms a Hardware pagetable walking is disabled when The hardwareThe page walker feature supportsmulti-level page level.levellowest The pagetabl of any register contains the base address of the first Directory or Page Table which will be accessed. The accessed. be which will Table or Page the first Directory of register contains the base address The existence of thisexistence register of The is denoted when PWBase, PWField Compliance Level: The specifies the number of index bits fields in 9.22Select 6) Register 6, (CP0 PWCtl Register MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

, if a then read- HugePg =1. Software 5..0 PWCtl HugePg PWCtlPsn PWCtl State Compliance Reset up to bitPTE. An 64 in the 7 6 DPH HugePg Psn ged Resource Architecture, Rev. 6.02 PTEvld R/W 0 Required R/W 0 Required Write Read / R or R/W 0 Required R or R/W 0 Required .e., directory .e., directory is bit is only is bit Field Descriptions Field Descriptions -of-4 in size. For this case, Page PTE can represent a = 0. Animplementation= 0. that doessupportHuge not Pages is required zero; returns zero; zero on read. R0 0 Required Directory levels. If this bit is PTE is used for even TLB TLB even for used is PTE will synthesize will synthesize the physical uge Page PTE can only repre- Page PTE uge non-leaf table (i non-leaf table Page support. Th Page support. in Huge Page PTE. Only used Description HugePg l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. Reserved =1. =1. field is set. PTEvld PWCtl Figure 9.24Figure Format Register PWCtl HugePg to 0. Software can determine the supported range by writing ones to Table 9.36Table PWCtl Register HugePg = 0 read-only. Software can determine Huge Page support by writing1 to 0 read-only. = Psn bit is set, then a Huge DPH is then bit set, bit is clear, then a H a then is clear, DPH bit used when used If If this bit is enabled.is set, then the Hardware Page Table when sent a region that is 2 x power 2 x that is sent a region for the physical addresses Hardware will the synthesize both the even and odd TLB pages from single the PTE entry. level) is supported. power-of-4 memory region or a 2x power-of-4 memory memory 2x power-of-4 region or a power-of-4 region. For the case, one first addresses for both the even and odd TLB pages from the single PTE entry. If set, then Huge Page PTE in page and the adjacent PTE used for the is odd PTE PTE. For adjacent the and page latter the case, the Hardware HugetPg PWCtl field is provisioned field is bits,allowing at 6 a starting bit positionfor 30 PWCtl PWCtlPsn Fields 31 - 30..8 as written be Must Reserved, can disable Huge Pages bycan disable HugePages setting If the implementationIf supportsHuge Pages,Huge then Software enables Pages setting by followingread returnsthen HugePage support 0, is not implemented. The ing. For non-Leaf implementation may choose to support a more limited range by hardwiring an implementation defined number of the high order bits of to hardwire PSn 5:0 of position Bit PWEn DPH 7 Dual Page format of Huge PWEn 31 walker enable HardwareTable Page Name Bits HugePg 6 in Page PTE supported Huge 172 MIPS® Architecture Vo For Programmers

ture, Rev. 6.02 Rev. ture, 173 Comment power-of-4) power-of-4) any power-of- 2 power-of- any Huge-Page region can region Huge-Page only be 2x power-of-4 2x power-of-4 only be (either power (either power of 4 or 2x Huge-Page region can Huge-Page be X Huge-Page Support No Must be 0 Support Huge-Page leaf entry Comment ed Resource Architec ed Resource Rsvd Field in Non- in Field Rsvd 9.22Register PWCtl Register (CP06, 6) Select Allowed Allowed Huge Page configurations configurations Page Huge not used not used Even TLB page and Odd TLB page and TLB Even from derived page entries both single PTE Odd TLB page and TLB Even from derived page entries both single PTE PTEVld PTEVld Always PTE Always PTE esented in the Directory Levels. the Directory esented in PTE PTE Size of Huge Page Huge Size of field is used to denote whether are supported HugePages or not. III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Type of Entry is taken. HugePg Power of 4 Power 4 of non-Power not used Table 9.37Table Field HugePg and =0 means Pointer Pointer =0 means Table 9.38Table Levels in Directory representation Huge Page aborts and TLB Refill exception aborts and TLB If encountered, HW Page Walker If encountered,PageWalker HW Two PTEs are read from mem- Two to HW Page Walker ory by the used for and Odd be the Even entries. page TLB =1 means Huge Page Non-Leaf Leaf PTEVld PTEVld PTE DPH PTEVld 0 Allowed Not 1 Allowed describes how describes the describes how describesPages are repr Huge PTE PWCTL HugePg Table 9.37 Table 9.38 1PTE 0 Pointer Always PWCTL MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 174 MIPS® Architecture Vo For Programmers

43 0 for Implementations for ture, Rev. 6.02 Rev. ture, 175 register fields. register State Compliance Reset HWREna ed Resource Architec ed Resource R/W 0 Reserved - Optional R/W 0 Required Write Read / Read cessor 0 is not enabled. 0 is cessor describes the the describes 9.23 HWREna RegisterRegister (CP07, 0) Select Table 9.39 Mask . XNP sters, and register sters, and register in this field is a 1 and and a 1 in this field is a mode in a mode whichcopro implemented, bit ‘n’ of Register; plemented, access to the the to access plemented, gisters via the registers are accessible RDHWR which hardware determines at hardware register register (which hardware ented, the corresponding bit ented, the corresponding Config5 ignored on write. ignored on Description HWREna access to the to the implementation- access III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Figure 9.25Figure Format Register HWREna PerfCnt and (Release 2). (Release lists the RDHWR regi RDHWR the lists Table 9.39Table HWREna Register Field Descriptions Required

instruction to a particular to a particular instruction may not be an register). may not be an actual ‘n’ is not If RDHWR register a write. is ignored on and zero a field returns this If RDHWR register ‘n’ is im register is enabled if bit in this field is a ‘n’ 1 and dis- 0. a of this field is ‘n’ abled if bit See for the RDHWR instruction a list of valid hard- ware registers. Table 9.40 disabled if bit is a 0. the corresponding dependent hardware registers 31 and 30. hardware registers 31 dependent If a register is not implem returns a zero and is is register to that access implemented, is If a register enabled if the corresponding bit to bit number ‘n’ corresponds ‘n’ in this field. register contains a bit mask th register contains shows the format of the shows HWREna Fields Release 6 adds access to CP0 adds Release 6 instruction when that instructionis executed in Figure 9.25 Figure Compliance Level: The Impl Mask 29..0 by the RDHWR access enables in this field bit Each 31..30 Impl These bits enable 31 30 29 Name Bits 9.23 7, Select 0) Register Register (CP0 HWREna MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

register mented Optional Required Required Required Required Required Reserved (Release 6) (Release 6) ister is imple- is ister Required if the is implemented is Required if any if Required UserLocal reg- PerfCnt turn value can be vir-

register, then reading register, sel ers are accessible via the a Reserved a Reserved Instruction Excep- is notprovide desirable to is HWREna ged Resource Architecture, Rev. 6.02 ndent use. If they ndent use. If they ould be the smallest the ould be field. register, while odd while odd register, at hardware register. at hardware SCX family of instruc- cess to the coprocessor 0 coprocessor cess to the dually disabled and the re . CPUNum Control XNP h of the hardware regist of the hardware h pecific storage block. In Release 6, is currently This register running. Meaning instructions is not present, other- not present, is instructions EBase er provides read access to the copro- access to the read provides er In some operating environments, the the In some operating environments, software may emulate the instruction’s software may emulate the instruction’s the return value sh value return the the system which must be synchronize must be synchronize the system which zed at the cost of handling zed at the cost of r implementation-depe r for future architecture use. Access architecture future for zed value. For example, if it etc. In absence of hardware support for In absence of hardware support in a Reserved Instruction Exception. in a Reserved Instruction selects the the selects Config5 value denotes the value denotes number of cycles synchronize. sel register provides read ac lease 6 Double-Width LLX/ 6 Double-Width lease e processor implements th that must be be used with the SYNCI instruction. See that instruction’s instruction’s that See instruction. SYNCI with the be used register in the in the pair. register l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. Register. register is required. 123register CC incrementscycle every CPU CPU cycle register increments every second CC register CC incrementsCPU cycle every third register, if it is implemented. is implemented. if it register, a thread-s to a pointer is register Counter Count Table 9.40Table Numbers Register RDHWR CCRes Value UserLocal register, access to that register may be indivi register, selects the implementation. in the wise present atomics, user or extended double-width behavior through means. other See tions. If set to 1, then LLX/SCX family of family LLX/SCX to 1, then If set tions. between update of the register. For example: between update of the register. cessor 0 description for the use of this value. In the typical implementation, this value value this implementation, In the typical for the value. use of this description caches in are no should be zero if there tracks cache the instruction or because no caches, are there because (either cases, other In cache). data the to writes caches of the size line results in a Reserved Instruction Exception. Instruction in a Reserved results These registers numbers are reserved provides read access to the coprocessor 0 the coprocessor to access read provides UserLocal UserLocal These register numbers are reserved fo are not implemented, access results the the register, privileged software may select whic privileged software may select register, Count CC This regist cycle counter. High-resolution XNP Indicates support for Re ULR This Local User Register. CCResThis CC register. the of Resolution PerfCnt Even Counter Pair. Performance CPUNum of the Number CPU on which the program SYNCI_Step Address step sizeto HWREna 5 3 4 1 0 2 29 6-28 Using the tualized by the operating system. tualized by the Software maydetermine which registers are implementedby writing all ones to the the value back. If a bit back as reads a one, th RDHWRa registerinstruction.In doing may so, be virtuali tion, interpreting the instruction, and returning the virtuali direct access to the direct access 30-31 Number Mnemonic Description Compliance Register 176 MIPS® Architecture Vo For Programmers

0 ture, Rev. 6.02 Rev. ture, 177 register fields. fields. register ndefined Required address that caused one of the fol- one of the caused that address rs, or for Watch exceptions, since or for Watch rs, BadVAddr Write Reset State Compliance Read/ ed Resource Architec ed Resource describes the 9.24 BadVAddr RegisterRegister (CP08, Select 0) er Field Descriptions er Field Descriptions Table 9.41 BadVAddr register; register; ss information for cache or bus erro ss information for cache Register 8, Select 0) 8, Select Register Description BadVAddr III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Figure 9.26Figure Format Register BadVAddr . rtual address R U Table 9.41Table Regist BadVAddr Required

register does not capture addre capture register does not register is a read-only register that captures the most recent virtual that captures the most recent register read-only register is a shows the format of the the shows BadVAddr BadVAddr Fields

Compliance Level: The lowing exceptions: • Addresserror (AdELAdES) or • Modified TLB Refill • TLBS) Invalid (TLBL, TLB •TLB The an addressing error. is none 9.26 Figure 31 Name Bits BadVAddr 31..0 Bad vi MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.24 (CP0 Register BadVAddr ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 178 MIPS® Architecture Vo For Programmers

0 Required Required (Release 6) (Pre-Release 6) (Pre-Release register fields. Register 8, Select 1) ture, Rev. 6.02 Rev. ture, 179 register is onlyby set State Compliance Reset BadInstr register is instantiatedper- BadInstr R Undefined Optional Inhibit, TLB Modified BadInstr Write Read / describes the ed Resource Architec ed Resource on emulation. The registerMachineInterrupts,set by is not NMI, 9.25 BadInstr Register (CP0 Table 9.42 Table . bit must bit always to 1. be set bit set to 1. Thebit 1. set to BI BI register is not set by Watch or EJTAG exceptions. or EJTAG register is not set by Watch BadInstr register; ead Inhibit, TLB Execute Config3 Config3 int, Floating-Point, exception2 Coprocessor BadInstr BadInstr 32 bits are placed in bits bits are 32 capture the most recent instruction which caused the following one of BadInstr UNPREDICTABLE Description is Register 8, Select 1) 8, Select Register 16 containing zero. 16 containing Optional III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Required Figure 9.27Figure Format Register BadInstr BadInstr instruction word. cessor. For Release For Release 6, the cessor. Table 9.42Table Descriptions Field Register BadInstr e Error exceptions. The e Error exceptions. register is indicated by the is register Instruction words words Instruction smaller than bits 31: with 15:0, Release 6 -

BadInstr register is provided to allow acceleration of provided to is instructi register register is a read-only register that is a read-only register register shows the proposedtheformat of BadInstr Address Error, TLB Refill, TLB Invalid, TLB TLB TLB R Invalid, Refill, Error, Address Coprocessor Unusable, Coprocessor Unusable, Reserved Instruction System Call, Breakpo Trap, Integer Overflow, BadInstr Fields Presence of the exceptions whichto are synchronous an instruction. The Figure 9.27 VPE in an MT ModuleanVPE in pro The Compliance Level: Pre-Release 6 - Compliance Level: Pre-Release check, Bus Error or Cach Error check, Bus When a synchronous exception occurs for whichWhen a synchronous exception occurs there is no valid instruction wo rd (for example TLB Refill - Instruc- tion Fetch),stored the value in • Addressing The exceptions: • validity Instruction • Execution Exception Name Bits BadInstr 31:0 Faulting 31 MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.25Register (CP0 BadInstr ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 180 MIPS® Architecture Vo For Programmers

0 Required Required (Release 6) (Pre-Release 6) (Pre-Release register fields. register register is only set by ture, Rev. 6.02 Rev. ture, 181 register is instantiated register is per- BadInstrP State Compliance Reset register contains the prior BadInstrP P BadInstrP R Undefined Optional Inhibit, TLB Modified Write Read / BadInstr describes the ed Resource Architec ed Resource registerMachine is not set by Interrupts, NMI, Table 9.43 9.26 BadInstrP Register (CP0 Register 8, Select 2) register. The register. bit set to 1. The bit mustset to1. be BP BP register is not set by Watch or EJTAG exceptions. or EJTAG register is not set by Watch BadInstrP register; ster Field Descriptions Field Descriptions ster BadInstr BadInstr ead Inhibit, TLB Execute Config3 Config3 int, Floating-Point,2 exception Coprocessor ation of instruction emulation. The emulation. instruction ation of BadInstrP BadInstr 32 bits are placed in bits bits are 32 BadInstrP Description Register 8, Select 2) 8, Select Register 16 containing zero. 16 containing . Optional III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: for these exceptions: for these exceptions: Required Figure Figure 9.28 Format Register BadInstrP cessor. For Release For Release 6, the cessor. register is indicated by the e Error exceptions. The e Error exceptions. Table 9.43Table Regi BadInstrP Instruction words words Instruction smaller than 15:0, with bits 31: with 15:0, Release 6 - BadInstrP UNPREDICTABLE register is used in conjunctionwith the register is updated register is provided to allow acceler P P is shows the proposedtheformat of BadInstr BadInstr Coprocessor Unusable, Coprocessor Unusable, Reserved Instruction System Call, Breakpo Trap, Integer Overflow, TLB TLB TLB R Invalid, Refill, Error, Address BadInstrP Fields BadInstrP Figure 9.28 check, Bus Error or Cach Error check, Bus branch instruction, when the faulting instruction is in a branch delay slot. The The Compliance Level: Pre-Release 6 - Compliance Level: Pre-Release Presence of the When a synchronousWhenand exception faulting the occurs instructionthenslot,a branch delayin is not the value stored in • validity Instruction • Execution Exception • Addressing The exceptions whichto are synchronous an instruction. The MT ModuleanVPE in pro Name Bits 31 BadInstrP 31:0 instruction. branch Prior 9.26 Register (CP0 BadInstrP MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 182 MIPS® Architecture Vo For Programmers

0 ture, Rev. 6.02 Rev. ture, 183 tion is executed, retired, register fields. Selects 6 and 7) Selects e width of the processor. processor. the of e width and are not defined by and are not defined the architecture. Count Write Reset State Compliance Read/ ed Resource Architec ed Resource 9.27 CountRegister Register (CP09, 0) Select , whetheroran instruc not rposes,synchronize includingto proces- reset or at describes the P0 Register 9, the processor, not the issu the processor, Table 9.44 Count . register; Description served for implementation-dependent use Count III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Figure9.29 Count Register Format . Table 9.44Table Count RegisterField Descriptions Implementation-dependent Required

shows the format of the shows register acts as a timer, incrementing at a constant rate constant at a incrementing a timer, register acts as functionalor diagnostic registerpufor can be written Count Count Fields sors. CountThe registerread via RDHWR can also be register 2. 9.29 Figure Compliance Level: CP0 register 9, Selects 6 and 7 are re Compliance Level: The

or any forward progress is made through the pipeline. The rate at which the counter increments is implementation- functionof the pipelinedependent,clock and is a of The Count 31..0 Interval counter R/W Undefined Required 31 Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.28 (C Reserved for Implementations 9.27Select 0) Register 9, (CP0 Count Register ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 184 MIPS® Architecture Vo For Programmers

reg-

ASID field is the the is field EntryHi register (via VPN2 ASID EntryHi ture, Rev. 6.02 Rev. ture, 185 Register 10, Select 0) registers. itecture which supports 1 ite, access operations. and e EHINV field around the use register fields. register State Compliance Reset Context of the virtual address tothe be writ-address virtual of is set to a value of 2 or 3. is set to a valueof This field 2 or or IE 31. 13 EntryHi dress error exception and these fields ASIDX Software writesthe of field is written by software withfield is written the currentsoftware by EH R/W Undefined Required ed Resource Architec ed Resource INV Write Read / Config4 BadVAddr ASID 9.29 EntryHiRegister (CP0 register. A TLBR instruction writes the TLBR instruction writes A register. n of Release 2 of the Arch n of Release 2 of the ftware mustsave andrestore thevalue of VPN2X describes the otherwise. ation used for TLB read, wr ation used 13 12 11 10 8 7 0 and restore the and restore value of th comparison process to determine TLB match. comparison EntryHi Select 0) Select er Field Descriptions er Field Descriptions TLB Invalidand TLB Modified and exceptions, in other Optional Table 9.45 Table ant for the subsequent usage of TLBWI instructions. ant of TLBWI instructions. for the subsequent usage memory accesses. One method of invalidating the memory accesses. s error exception sequence. error s field of the irtual page number / 2). / page number irtual register; register are not defined after an ad an defined after not are register d, or TLB Modified) causes bits VA software before a TLB write. software field of the TLB entry can be optionally invalidated. When this is done, the VPN2X register. An implementatio register. EntryHi used during used the TLB Description Register 10, Register EntryHi VPN2 from the selected TLB entry. The TLB entry. the selected from III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Figure 9.30Figure Format Register EntryHi for TLB-based MMU; for TLB-based EntryHi into the the into VPN2 Table 9.45Table Regist EntryHi 12..11 of the virtual address (v fields of the of the fields Required Required

31 13 field is overwrittenTLBR instruction,by so a field of the field of fieldinstruction.field withThisTLBWI exists the if VPN2 This field is written by hardware on a TLB exception or on on a TLB exception or on is written by hardware This field by written is and read, a TLB ASID and register contains the virtual register contains the address match inform VPN2 shows the format of the the shows EHINV VPNX2 EntryHi Fields Figure 9.30 Figure Because the address space identifier value and is space identifier value address memory management software. the architecture, Release 3 of the In around use of the TLBR. This is especially important in maybemodified by hardware during the addres

use of the is overwritten by a TLBR instruction, so software must save of the TLBR instruction. This is especially import The MTC0) do notdo cause the implicit address-relatedtheMTC0) fields in write of A TLB exception(TLBRefill, TLBInvali Compliance Level: The kB pages also writeskB pages alsoVA ten into the invalidated entry is ignored on address match for ister with the correspondingister fields VPN2 31..13 VA Name Bits 31 MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.29 (CP0 EntryHi Register

field =2 or 3. 3. or =2 VPN2X IE port) MMU) Required support, or if Config4 hardware invalidate hardware invalidate and and 1 kB Page Sup- Required (Release 6) Required for TLBWI in an unmapped address in an unmapped = AE If then then

else 0 State Compliance 1 Reset Undefined Config4 of the Architecture, the Architecture, of the ged Resource Architecture, Rev. 6.02 A before each instance in which the value then

If is mandatory. Instead, software must invali- must software Instead, mandatory. is R/W 0 (Release Required 2 R/W Undefined Required (TLB R/W 0 Optional (Release 3). R/W else 0 Write = 1 Read / E Config4 EHINV carried out while running carried out while =1. EntryHi EHINV field to sup- field to eld Descriptions (Continued) eld Descriptions quent releases), le by either hard- either by le VPN2 EntryHi = 1 and and = 1 on will update this field SP SP nd against which TLB refer- l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. if thisnot sequence if done.UNDEFINED is cture (and cture (and subse Config3 n with zero and the TLB must be flushed Description e bits are not writab then these bits extend the ASID field. the ASID these field. bits extend then

= 1. If enabled for write, this field con- = 1 returns zero; as be written = 0 Must then of the virtual address and is written by hard- and is written of the virtual address > 1, and this bit is set, the TLBWI instruc- TLBWI the this bit is set, > 1, and > 1, a TLBR instructi > 1, a TLBR ESP field is an extension to the field is an extension to IE AE AE IE 12 11 VPN2X Table 9.45Table Fi Register EntryHi Config4 Config4 Config4 Config4 register is changed. This operation must be If If ware on a TLB exception or on a TLB read, and is by write. before a TLB software and in not enabled, If writes are implementations of must be written field this of the 1 Architecture, Release on read. zeros with zero and returns on a TLB read and the by software to establish current ASID value for TLB write a TLB ASID field. ences match each entry’s tion will invalidate the VPN2 field of the selected TLB entry. If TLB entry. of the read bit VPN2 invalid withe the read. zero on port 1 kB pages. Thes port 1 ware or software unless the the PageGrain tains VA tains register must be writte PageGrain EntryHi Fields Programming Note: Programming implementationsIn 6) of Releaseprior to Release 2 (and any subsequentreleases of the date the TLB entries explicitlyTLB entriesdate the using TLBWI with of the space. The operation of the processor is processor space. The operation of the not a requirement because support for is For Release 6, this ASID 7..0 by hardware is written field This identifier. Address space Name Bits ASIDX 9..8 If EHINV 10 TLB Invalidate HW VPN2X 12..11the Archite 2 of In Release 186 MIPS® Architecture Vo For Programmers

0 IPTI register is shows the IntCtl . Compare ecture, the presence ecture, the presence Figure 9.31 Figure ture, Rev. 6.02 Rev. ture, 187 Register 11, Select 0) State Compliance Reset ementation-dependent way with a ementation-dependent Selects 6 and 7) Selects Write Read / ed Resource Architec ed Resource register, an interrupt request is made. In register, er. In normal use however, the In normal use however, er. register fields. the Interrupt System” on pagethe Interrupt 82 -dependent use -dependent use and are not defined by the architec- 9.30 Compare Register (CP0 Compare Compare registerimplement to anda timer timer interruptfunction. P0 Register 11, P0 Register 11, t Mode, the interruptisat thelevel by the specified bit and is combined in an impl bit and is

Count TI Compare . e does not and own. change on its Cause register, as a side effect, clears the timer interrupt. the clears a side effect, as register, describes the the describes B instruction can be used to makein visible when the terrupt state changes Description , Select 0) , Select 11 Register served for implementation served register is a read/write regist are value R/W Undefined Required register. In Release 2 (and subsequent releases) of the Archit In Release 2 (and subsequent register. Compare III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Table 9.46 njunction with the Figure 9.31Register Format Compare Cause . register equals the value of the the value of register equals Compare Table 9.46Table Register Compare Field Descriptions register; Count Implementation-dependent Required (7) in the

IP register acts in co acts in register maintains registerstable valu a Compare register is written.register is See 6.1.2.1and “Software Hazards Compare Compare Fields The Release 1 of this request the architecture, combinedis in an implementation-dependent way with hardware interrupt 5 to set interrupt bit When the value of the ture. Compare Compare Compliance Level: CP0 register 11, Selects re 6 and 7 are registerCP0 11, Compliance Level: The field. Fordiagnostic purposes, the Programming Note: Programming Release2 of the Architecture, the EH In

write-only. Writing a value to the Writing write-only. hardware or software interrupt. For Vectored Interrup hardware or software interrupt. For Vectored of the interruptof is visible to software via the format of the Name Bits Compare 31..0 comp count Interval 31 MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.31 (C Reserved for Implementations 9.30 (CP0 Register Compare ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 188 MIPS® Architecture Vo For Programmers

reg- Status “MIPS32 and Register12, 0) Select ture, Rev. 6.02 Rev. ture, 189 “Interrupts” onpage 71 for a shows the format of the terrupt enabling, and thediagnostic 109 8765432 10 ed Resource Architec ed Resource 10 9 8 7 6 5 4 3 2 1 0 Figure 9.33 9.32 StatusRegister (CP rating modes for the processor. See processor. rating modes for the IPL KSU IPL KSU register fields. for a discussion forofmodes, operating a and Status register for Pre-Release 6; register for Pre-Release that contains the operating mode, in operating the contains that Status III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: this register combine to create ope combine to create this register describes the the describes . P Register 12, Select 0) 12, Select P Register Figure 9.33Figure 6 Release for Format Register Status Figure 9.32Figure 6 Pre-Release for Format Register Status Required

Table 9.47 shows the format of the register is a read/write register register register is a read/write Status states of the processor. Fields of states of the processor. microMIPS32 Operating Modes” on page 21 discussion of interruptmodes. 9.33 Figure Compliance Level: The ister for Release 6; ister for Release RW 0 FR 0 MX 0 BEV 0 SR NMI ASE Impl IM7..IM2 IM1..IM0 0 UM R0 ERL EXL IE CU1 CU3.. CU3..CU0 RP FR RE MX 0 BEV TS SR NMI ASE Impl IM7..IM2 IM1..IM0 0 UM R0 ERL EXL IE 31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.32 (C Register Status

Required Register12, 0) Select ture, Rev. 6.02 Rev. ture, 191 1/0 State Compliance Reset Undefined R R/W Write Read / (Release 6) ed Resource Architec ed Resource (Pre-Release 6) (Pre-Release 9.32 StatusRegister (CP “64- t register mode t register er model continues behavior. See behavior. 64-bit datatypes 64-bit UNPREDICTABLE. e of this bit, the contents Meaning bit and other state or oper- other state or and bit ng-point unit. In Release 2 Release In unit. ng-point = 1 is required. I.e. the 64- on of a 32-bit FPU with sin- a 32-bit on of lease 2 of the Architecture 2 of the Architecture lease a 64-bit FPU; i.e., FR is FR i.e., FPU; 64-bit a of the Architecture (and sub- this case, FR=0, although although this case, FR=0, equent releases), both 32-bit releases), both 32-bit equent in which a 64-bit floating- ure, only MIPS64 processors processors ure, MIPS64 only 64-bit floating-point unit is 64-bit floating-point for a discussion of these com- a discussion of for FR implement a 64-bit floating- implement a 64-bit t isimplemented Description lease 5 of the Architecture, if floating- if Architecture, the 5 of lease bi-modal support for both 32-bit and both 32-bit bi-modal support for w for more details. III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: nt registers are = 1 64-bit FPU register model, is register model, FPU FR1 64-bit = t implemented = 0 32-bit FPU regist 32-bit FPU = 0 any 32-bit datatype. datatype. 32-bit any pairs of regis- are stored in even-odd ters. datatype any UNPREDICTABLE =0. FR D/L 0 contain registers can Floating-point 1 contain registers can Floating-point FIR Table 9.47Table (Continued) Descriptions Field Register Status Encoding point unit is no point unit tecture (and subsequent releases) In Release 1 of the Architect In Release for 64-bit floating-point units: for 64-bit floating-point floati could implement a 64-bit can and 64-bit processors Re point unit. As of implemented then point is of the Architecture (and subs Certain combinations of the FR Certain combinations of binations. valu the changes software When floating-poi of the ations can cause ations can bit FPR Enable” on page 22 bit FPU, with the the bit FPU, with The required. to be required. disallows Release 6 64-bit FPU register models in read-only. See belo See read-only. This bit must be ignored on write and read as zero under zero under as read and write ignored on bit must be This conditions: the following •uni floating-point No • Archi- the of 1 of Release implementation In a MIPS32 • In implementation of an Re an 1 for as read and write ignored on bit must be This of Release implementation 6 a which in releases) sequent implemented. Release 6 allows implementati In gle only. precision support this does not imply even-odd pairing of 32-bit registers because Fields FR 26 This bit is used to the floating-poin control Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

Optional (Release6) (Pre-Release 6) 1 Required 0 Reserved State Compliance Reset 0 if the pro- the if 0 cessor imple- ments the neither MDMX nor the MIPS DSP Mod- ules; other- wise Undefined ged Resource Architecture, Rev. 6.02 0 R/W Undefined Optional R/W Write Read / R if the proces- the if R sor imple- neither ments the MDMX nor theMIPS DSP Modules; R/W otherwise for details. versed endianness versed of these ASEs. If neither Meaning Meaning Meaning memory references while memory el Mode nor Supervisor Supervisor el Mode nor write and read as zero. l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. ndian Locations” on page 84 Description 01 Normal Bootstrap 01 not allowed Access allowed Access 01 mode endianness User uses configured mode User uses re “Exception Vector Table 9.47Table (Continued) Descriptions Field Register Status Encoding Encoding Encoding the processor is in user mode: running Kern Mode nor Debug Neither bit. of this state the by affected are references Mode on write be it must ignored If bit is not implemented, this and read as zero. on processors implementing one on implementing processors is implemented, DSP Module the MIPS the MDMX nor bit must be ignored on this See See Fields 0 25 This returns bit as zero; zero on read. must written be RE 25reverse-e enable to Used MX 24 Enables access to MDMX™ and MIPS® DSP resources BEV 22 of exception vectors: location the Controls Name Bits 192 MIPS® Architecture Vo For Programmers

Required if Soft Required imple- is Reset mented (Release6) processor detects processor and reports a match on multi- entries TLB ple 6) (Pre-Release Register12, 0) Select ture, Rev. 6.02 Rev. ture, 193 0 if the Required 0 Reserved State Compliance erwise Reset 1 for Soft 1 for Reset; 0 oth- Reset; 0 0 R/W R/W Write Read / ed Resource Architec ed Resource 9.32 StatusRegister (CP whether UNPRE- for a discussion of gnores or accepts the this bit when its value is a its value is when this bit When such a detection detection a such When Meaning sition. If such a transition is hould not write a 1 to this bit causing a 0-to-1 causing a 0-to-1 transition. If t should be cleared by soft- t should be cleared by d, it d, on write must be ignored detected a match on multiple on multiple a match detected rough the reset exception vector UNPREDICTABLE ignores a write of 1. tion-dependent whether this whether tion-dependent ndent whether whether plementation-dependent ed by software, it ed by software, is Description essor initialization. essor ion” on pageion” on 33 III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: whether hardware i resuming normal operation. normal resuming In 2 of the Architecture (and Release sub- 01 Soft Reset Not (NMI or Reset) Reset Soft “TLB Initializat “TLB Table 9.47Table (Continued) Descriptions Field Register Status Encoding entries. It is implementa is It entries. or an access TLB, to the on a write all, at occurs detection to the TLB. sequent releases), multiple TLBmatchesonly may a TLB write. bereported on occurs, the processor initiates a machine check exception exception check a machine initiates the processor occurs, It is bit. and sets this im condi- If the software. be corrected by can condition this bi this tion can be corrected, ware before See check a machine avoid to used initialization TLB software exception during proc on write it must be ignored If bit is not implemented, this and read as zero. to 1 a should not write Software causing a 0-to-1 tran thereby 0, was due to a Soft Reset: this bit is implemente If not and read as zero. For Pre-Release 6, software s a 0, thereby is value its when such a transition is caus write. For Release 6, hardware caused by software, it is side no with write the accepts write, the ignores hardware check machine a initiates and write the accepts or effects, exception. DICTABLE 21TLB has Indicates that the Fields 1 0 21 returns This bit as zero; zero on read. must written be SR 20th entry Indicates that the TS Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

Required for Required for wise Reserved 2 and EIC inter- EIC and 2 mode rupt only) Required if NMI Required is implemented MCU ASE; other- MCU State Compliance Reset otherwise 0 if MCU Undefined Optional ASE is not 1 for NMI; 0 1 for implemented ged Resource Architecture, Rev. 6.02 R/W Undefined (Release Optional R/W R/W Undefined Required Write mented Read / is not imple- is not 0 if MCU ASE = 1), 1), = = 0), for a for VEIC VEIC UNPRE- exception vector Config3 Config3 gnores or accepts the Meaning Meaning . An interrupt will sig- will be . An interrupt they are not implemented, implemented, not are they e 2 of the Architecture (and Architecture e 2 the of hould not write a 1 to this bit causing a 0-to-1 If causing a 0-to-1 transition. quest disabled d, it d, must be ignored on write t meaning and are interpreted t meaning and are interpreted IPL ich EIC interrupt mode is l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. rough the reset “Interrupts” on page on “Interrupts” 71 the enabling of each of the hard- ignores a write of 1. ed by software, it ed by software, is = 1), this field is the encoded encoded the is field this 1), = Description entation-dependent and entation-dependent and are not VEIC whether hardware i field, below. described Config3 01 Interrupt re Interrupt request enabled 01NMI NMI (Soft Reset or Reset) Not IPL Table 9.47Table (Continued) Descriptions Field Register Status Encoding Encoding these bits take on a differen as the IM7..IM2 bits, described above. ware interrupts. Refer to Refer ware interrupts. interrupts. enabled discussion of complete in Architecture the 2 of Release of In implementations ( is enabled mode interrupt EIC which was due to an NMI exception: to an NMI exception: due was this bit is implemente If not and read as zero. For Pre-Release 6, software s a 0, thereby is value its when such a transition is caus write. For Release 6, hardware be this bit must then If not MCU ASE implemented, is as zero; returns written zero on read. DICTABLE defined by the architecture. If they must ignored on be write and read as zero. (0..63) value of the current naled only if the IPL is requested higher than this value. If EIC interrupt mode is not enabled ( these bits take on a differen the as In implementations of Releas In implementations of subsequentreleases) in wh enabled ( Fields IPL 15..10Level. Interrupt Priority ASE 18 This bit is reserved for the MCU ASE. Impl 17..16are implem These bits NMI 19th entry Indicates that the Name Bits IM7..IM2 15..10 Interrupt Mask: Controls 194 MIPS® Architecture Vo For Programmers

Supervisor Mode is implemented; Optional other- wise Register12, 0) Select ture, Rev. 6.02 Rev. ture, 195 State Compliance Reset R0Reserved R/W Undefined Required R/W Undefined Required R/W Undefined if Required Write Read / ed Resource Architec ed Resource 9.32 StatusRegister (CP = 1), 1), = for a full for for a for VEIC “MIPS32 UNDE- fields, described fields, described Config3 R0 and and of this value. field, described field, described above. field, described above. Meaning Meaning Meaning The encoding of this bit is: 32 Operating Modes” on 32 Operating ve no effect on the interrupt the on effect ve no UM quest disabled enabling of each of soft- of each the enabling ting mode of the processor. ting mode of the processor. ignored on write and read as implemented, this bit implemented, denotes implemented, this bit this bit is implemented, hown below. The meaning of hown below. “Interrupts” on page on “Interrupts” 71 if this value is written to the the to is written value this if the returns zero on read. R 0 Reserved field. For Release 6, hardware 6, hardware For Release field. Description III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: ation of the processor is FINED KSU ignores a write 01 Base mode is Kernel Mode Base mode is User Mode 01 Interrupt re Interrupt request enabled for a full discussion of operating modes. The 0b11oper- 6, the Pre-Release For Reserved. 0b000b01 Base mode is Kernel Mode 0b10 Base Mode mode is Supervisor Base mode is User Mode “MIPS32 and microMIPS Table 9.47Table (Continued) Descriptions Field Register Status Encoding Encoding Encoding field denotes the base opera See complete discussion of enabled interrupts. interrupts. enabled discussion of complete in Architecture the 2 of Release of In implementations ( is enabled mode interrupt EIC which ware interrupts. Refer to Refer ware interrupts. Note: This field overlaps the the overlaps field This Note: these bits are writable, but ha system. page 21 encoding of this field is s has for Release changed 6. encoding 0b11 zero. KSU the bit overlaps This Note: Note: This bit overlaps the KSU the bit overlaps This Note: reserved. This bit must be the base operating mode of the processor. See the base operating mode of the processor. and microMIPS32 Operating Modes” on page 21 discussion of operating modes. below. Fields 0 7:5 as zero; written be Must R0 3 If Supervisor Mode is not UM 4 If Supervisor Mode is not KSU 4..3 this of If encoding Supervisor Mode is implemented, the Name Bits IM1..IM0 9..8 Controls Interrupt Mask: MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

LB

1 Required State Compliance Reset e TLB structure, so the TS bit e TLB structure, matches and shutdown the T the shutdown and matches ged Resource Architecture, Rev. 6.02 R/W Undefined Required R/W Undefined Required R/W Write Read / if the if the cause physical damage to th physical damage cause uits detected multiple TLB Cache Error excep- Error Cache . This allows main main allows This . UNDEFINED Meaning Meaning Meaning e the return address held in essor is executing instruc- essor e (and e (and subsequent releases), the general exception vector ) will not be updated if will not be updated ) processor when any exception processor when any exception as an unmapped and uncached and uncached as an unmapped e mastersoftware enablefor parately via the DI and EI l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. r exception are taken. EPC Description Soft Reset, NMI or Soft Reset, NMI and SRSCtl (implementations of Release SRSCtl (implementations of and hutdown” condition in which circ BD “Address Translation “Address Translation for the kuseg Segment instead of instead or Cache Erro is set: is set: 01 Interrupts are disabled Interrupts are enabled 01 level Normal level Exception 01 level Normal level Error bit is set while the the proc set while bit is EXL ERL Table 9.47Table (Continued) Descriptions Field Register Status Encoding Encoding Encoding 2 of the Architecture only Architecture the 2 of is taken another exception ErrorEPC region. See page = 1” on StatusERL when 31 memory to be accessed in the presence of cache errors. The operation of the is processor instead of the TLB Refill vector. Refill of the TLB instead ERL from tions kuseg. When When • The is in kernel processor running mode • Hardware and software interrupts are disabled •will us The ERET instruction and hardware and hardware interrupts: Architectur the 2 of In Release this bit may be modified se instructions. Reset, NMI • is treated kuseg Segment • Mode The is in Kernel processor running • Hardware and software interrupts are disabled. • exceptions use TLB Refill • EPC, Cause other than Reset, other than tion are taken. taken. are tion When Fields IE 0 Interrupt Enable: Acts as th ERL 2 Error Set Level; by the when a Reset, processor Soft EXL 1 Exception Level; Set by the Name Bits s, multiple TLB matches do not s, multiple TLB matches do design In newer damage. physical to prevent and detected were matches TLB multiple that handler exception check machine the to indicator an but is simply name, its retains the processor. by reported 1.S “TLB a indicated The TS bit originally 196 MIPS® Architecture Vo For Programmers

IM, Register12, 0) Select ture, Rev. 6.02 Rev. ture, 197 e Interrupt System” e Interrupt on s visible changes visible terrupt state when the ed Resource Architec ed Resource “Software Hazards and th “Software 9.32 StatusRegister (CP register are written. See register are B instruction can be used to make in Status III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: fields the fields of IE , or EXL , . ERL ,

Programming Note: Programming the EH of the Architecture, 2 Release In IPL page 82 MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 198 MIPS® Architecture Vo For Programmers

0 Required 0 e, including vec- ture, Rev. 6.02 Rev. ture, 199 Register 12, Select 1) 5 4 State Compliance Reset hardware or Externally Set VS register fields. register of the Architectur RPreset by by RPreset Write Read / IntCtl 10 9 ed Resource Architec ed Resource 9.33 IntCtl Register (CP0 0000 if External if External 1 2 3 4 5 describes the W W W W W ller. Thisregister exist does not in implementations of ller. Hardware 14 13 Interrupt Source Table 9.48 for a potential interrupt. interrupt. potential a for TI is both implemented and both implemented is y and Vectored Interrupt modes, modes, Interrupt y and Vectored UNPREDICTABLE terrupt capability added in Release 2 Release in terrupt capability added register; Description Cause ed, and allows software to determine to determine allows ed, software and MCU ASE IntCtl Figure 9.34Figure Format Register IntCtl III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: 22 HW0 33 H 44 H 55 H 66 H 77 H (Release 2). (Release Table 9.48Table Field Descriptions Register IntCtl Encoding IP bit this field specifies the IP number to which the Timer Inter- Timer the which to IP number the specifies field this merg rupt request is whether to consider The value of this field is enabled. The external interrupt controller is expected to is expected controller interrupt external The enabled. mode. interrupt that information for this provide Interrupt Controller Interrupt Mode Required

shows the format of the shows register controls the expanded in register controls IntCtl Fields tored interruptsexternalan and support for interrupt contro Release 1 of the Architecture. Release 1 9.34 Figure Compliance Level: The

. IPTI IPPCI IPFDC IPTI 31..29 Compatibilit For Interrupt 31 29 28 26 25 23 22 Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.33 Select 1) 12, (CP0 Register IntCtl Register

Optional Fast (EJTAG Chan- Debug nel Imple- mented) Optional (Per- formance Counters Implemented) State Compliance Reset hardware or Externally Set hardware or Externally Set ged Resource Architecture, Rev. 6.02 00Reserved RPreset by by RPreset RPreset by by RPreset Write Read /

PC for a PCI if External if External if External if External Config1 for a poten- 1 2 3 4 5 1 2 3 4 5 W W W W W W W W W W Cause FDCI Hardware Hardware Interrupt Source Interrupt Source d, this field returns d, zero Cause ectored Interrupt modes, modes, Interrupt ectored st is merged, and st is merged, allows is both implemented and both implemented is is both implemented and both implemented is UNPREDICTABLE UNPREDICTABLE ity and Vectored Interrupt modes, modes, Interrupt ity and Vectored ity and V Description l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. ed for the ASE. turns zero on read. 22 HW0 33 H 44 H 55 H 66 H 77 H 22 HW0 33 H 44 H 55 H 66 H 77 H Encoding IP bit Encoding IP bit this field specifies the IP number to which the Perfor- the which to IP number the specifies field this reque mance Counter Interrupt to consider whether to determine software on read. enabled. The external interrupt controller is expected to is expected controller interrupt external The enabled. mode. interrupt that information for this provide FDC is not implemente If EJTAG zero; as written be must implemented, not is ASE that If read. zero on returns Interrupt Controller Interrupt Mode The value of this field is tial interrupt. interrupt. tial = re this field = 0), The value of this field is field specifies the IP number to which the Fast Debug this software allows and is merged, request Interrupt Channel to consider whether determine to potential interrupt. to is expected controller interrupt external The enabled. mode. that interrupt information for this provide counters are not implemented ( performance If Interrupt Controller Interrupt Mode Table 9.48Table (Continued) Descriptions Field Register IntCtl Fields IPPCI 28..26 Compatibil Interrupt For Name Bits IPFDC 25..23 Compatibil Interrupt For MCU ASE 22..14reserv Thesebits are 200 MIPS® Architecture Vo For Programmers

ture, Rev. 6.02 Rev. ture, 201 Register 12, Select 1) State Compliance Reset 0 0 Reserved R/W 0 Optional Write Read / ed Resource Architec ed Resource 9.33 IntCtl Register (CP0 32 64 128 256 512 = 0), this field ), this field speci- VInt if a reserved value reserved if a VEIC o on read. o on Config3 nor VI mode are imple- VI mode are nor Config3 (hex) (decimal) returns zero on read. on returns zero 0 0 Reserved returns zer UNDEFINED or n vectored interrupts. interrupts. n vectored = 0 and Description Spacing Between Vectors Between Vectors Spacing VInt VEIC III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Config3 0x000x01 0x000 0x020 0 0x020x040x08 0x040 0x10 0x080 0x100 0x200 Encoding is ignored on is ignored write and as zero. reads All other values are reserved. For Pre-Release 6, the oper- processor is of the ation fies the spacing betwee spacing the fies denoted by denoted by is written to this field. For Release 6, hardware ignores writes of reserved values. If neither EIC interrupt mode mented (Config3 Table 9.48Table (Continued) Descriptions Field Register IntCtl ..10 zero; as be written Must Fields 0 4..0 zero; as be written Must 0 VS 9..5 interrupts implemented (as are Spacing. If vectored Vector Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 202 MIPS® Architecture Vo For Programmers

only) CSS Required interrupt mode interrupt ture, Rev. 6.02 Rev. ture, 203 Register 12, Select 2) 0 00 State Compliance Reset hardware register fields. register PSS R Preset by R Undefined (EIC Required SRSCtl Write Read / ed Resource Architec ed Resource 0 00 reg- for a for is 0, is 9.34 Register SRSCtl (CP0 is 1 (EIC describes the CSS fields VEIC SRSMap ESS VEIC , and UNDEFINED if a PSS , Config3 ster Field Descriptions ster Table 9.49 Table Config3 0 register to select the cur- to select register 00 zero value in this field zero shadow sets are numbered EICSS is field is written to any of is written to any field is is field is loaded from the the is from is field loaded , roller Mode” on page 78 zero, and returns zero on read. GPR shadow sets in the processor. This register does not exist in imple- GPR shadow the sets in processor. register; returns zero on read. 0ESS 0 Reserved returns zero on read. 0 0 Reserved returns zero on read. 0 0 Reserved is field contains the highest contains is field SRSMap Description EICSS SRSCtl Register 12, Select 2) 12, Select Register III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Figure 9.35Figure Format Register SRSCtl (Release 2). (Release Table 9.49Table SRSCtl Regi 0 “External Interrupt Cont 00 00 00 0. n, where n is the value of the field. value highest the represents also field in this value The the to written be can that shadow set number that is implemented by this processor. by this processor. shadow set is implemented number that normal the only that indicates field in this of zero A value GPRs A non- are implemented. implemented the that indicates of this register, or to any of the fields of the of this register, interrupt mode is enabled), th interrupt ister. The operation of the is processor ister. request and for each interrupt external controller interrupt is used in place of the value thanthe larger one in th these other values. these this field must be written as be written must field this rent shadow set for the rent shadow interrupt. See EIC interrupt mode. If discussion of Required

register controls the operation of register controls the shows the format of the shows HSS SRSCtl Fields

mentations of the architecture prior to Release 2. architecture mentations of the 9.35 Figure Compliance Level: The 0 31..30 zeros; as written be Must 0 17..16 zeros; as be written Must 0 25..22 zeros; as be written Must 0 00 HSS 29..26 Highest Shadow Set. Th Name Bits EICSS 21..18 interrupt EIC mode shadow set. If 10922 211111 210 6543 1211109 0 2625 2221 18171615 313029 9.34 (CP0 SRSCtl Register MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

State Compliance Reset Comment ged Resource Architecture, Rev. 6.02 Treat as as exception Treat 0 0 Reserved R 0 Required R/W 0 Required R/W 0 Required Write Read /

= BEV Source if soft- if if soft- if = 0. Table 9.50 CSS field is CSS Status BEV onException an or Interrupt = 1. = 1. Neither is it = 1. Neither ESS ESS BEV CSS BEV = 1 or = 1 SRSCtl eld Descriptions (Continued) eld Descriptions Status rectly by software ERL UNDEFINED UNDEFINED ception or interrupt that or interrupt that ception ception or interrupt that or interrupt that ception e next paragraph, this field Status Status An ERET instruction copies An ERET instruction er of the current GPR set. current the er of field specifies the shadow set set shadow the specifies field ons in the next noted para-

ode caused by any exception caused by ode any exception which sets which any exception any exception which sets which any exception Status returns zero on read. 0 0 Reserved returns zero on read. GPR shadow registers are imple- are registers GPR shadow field and executing an an ERET field and executing GPR shadow registers are imple- = 1, or = 1, = 1, or = 1,

Description l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. PSS EXL EXL = 0 SRSCtl IV can be changed di be changed CSS can to 1 (i.e., NMI or cache error), an entry into to 1 (i.e., NMI or cache error), an entry into Condition Cause ERL ERL mented, and with the exclusi mented, and with when an field CSS from the copied is field this graph, occurs. interrupt exception or if CSS field the into back value this Status an ERET with updated on 1. The value of instruction. This field is not updated on This field is the writing only by The operation of The operation the processor is ware writes a value into this field that is greater than the the is than that greater this field into a value writes ware valuefield.HSS in the is updated with a new value on any interrupt or exception, ERET. an on the PSS field and restored from Status mented, this field isthe numb in th noted exclusions the With describes the various sources from which the interrupt. an exception or updated on not updated on This field is EJTAG Debug mode, or any ex any mode, or Debug EJTAG occurs with Status EJTAG Debug mode, or any ex any mode, or Debug EJTAG to use on entry to Kernel M entry on use to with Status occurs other than a vectored interrupt. than a vectored other of The operation processor the is the is than that greater this field into a value writes ware valuefield.HSS in the Table 9.49Table Fi SRSCtl Register Table 9.50Table SRSCtl for new Sources rupt Exception All SRSCtl Fields Exception Type Exception Non-Vectored Inter- Non-Vectored 0 5..4 zeros; as be written Must 0 11..10 be written as zeros; Must PSS 9..6If Shadow Set. Previous ESS 15..12 Shadow Set. This Exception CSS 3..0 Current Set. If Shadow Name Bits 204 MIPS® Architecture Vo For Programmers

register and the use ture, Rev. 6.02 Rev. ture, 205 Register 12, Select 2) al map register al map SRSCtl Comment Source is Source intern is external interrupt Source controller. ed Resource Architec ed Resource . A hardware change . A hardware change to PSS the field as the result Source 9.34 Register SRSCtl (CP0 CSS be cleared with a JR.HBinstruction as or JALR.HB azard between the write of the azard between the write VectNum EICSS SRSCtl on an Exception or Interrupt (Continued) or Interrupt on an Exception 4 4+3..VectNum SRSMap SRSCtl  CSS and Events” on page on and Events” 107 = 1 = 1 = = 0 and VInt = 1 and = 1 and VEIC III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: IV IV VEIC field creates an instruction h field creates an instruction Condition Config3 Cause Config3 Config3 “Hazard Clearing Instructions rupt Table 9.50Table Sources fornew SRSCtl Vectored InterruptVectored Cause Exception Type Exception Vectored EIC Inter- EIC Vectored Programming Note: Programming to the PSS A software change of interrupt or exception entry automaticallyis cleared the for executionof the first instruction in the interrupt or exception handler. of a RDPGPR or WRPGPR instruction. This hazard must described in MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 206 MIPS® Architecture Vo For Programmers

0 . 4 3 ditional Shadow Sets ture, Rev. 6.02 Rev. ture, 207 Register 12, Select 3) register fields. State Compliance r a non-interrupt exception, r Reset 8 7 SRSMap UNPREDICTABLE R/W 0 Required R/WR/W 0 0 Required Required Write Read / ed Resource Architec ed Resource if the Architecture Ad , the shadow, the set number comesfrom SRSCt- 12 11 describes the describes register are not used fo used are not register 9.35 SRSMap Register (CP0 s for vectornumberss for 7..0. The same shadowset num- mapping from an vector number to the shadow set num- Table 9.51 creatingmany-to-one a mapping a vector from toa single = 0). In such cases 16 15 VS read or write of this register are read or write of for Vector Number 7Number Vector for 6Number Vector for 5Number Vector for 4Number Vector for R/W3Number Vector for R/W R/W 0 R/W 0 R/W 0 Required 0 Required 0 Required Required Required for Vector Number 1 Number Vector for 0 Number Vector for register; Description rrupt. The valuesrrupt.this The from Register 12, Select 3) 12, Select Register 20 19 = 0 or IntCtl 0 or = SRSMap IV III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: if a valueUNDEFINED is written to any field in this register that is greater than the Figure Figure 9.36 Format Register SRSMap in Release 2 (and subsequent releases) of subsequent 2 (and in Release Table 9.51Table Descriptions Field Register SRSMap Mode are Implemented 24 23 Required

. HSS register containsnumber the shadowregister set register containsregister 8 4-bit fieldsthe that provide the results is zero, of a software shows the format of the the shows HSS 28 27 SRSMap SRSMap . Fields SSV7 SSV6 SSV5 SSV4 SSV3 SSV2 SSV1 SSV0 ESS The operation of the processor is value of SRSCtl Compliance Level: and Vectored Interrupt and Vectored The The l shadow register set number. 9.36 Figure ber to use when servicing such an inte when servicing use to ber or a non-vectored interrupt (Cause can be established forber multiple interrupt vectors, If SRSCtl

SSV7 31..28register set number Shadow SSV6SSV5SSV4 27..24SSV3 23..20register set number Shadow SSV2 19..16register set number Shadow 15..12register set number Shadow 11..8register set number Shadow 2 Number Vector for register set number Shadow SSV1SSV0 7..4 3..0register set number Shadow register set number Shadow 31 Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.35Register (CP0 SRSMap ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 208 MIPS® Architecture Vo For Programmers

, DC , 1..0 2) 2 1 0 IP Register13, 0) Select ture, Rev. 6.02 Rev. ture, 209 exception of the exception State Compliance Reset register fields. R Undefined Required R Undefined (Release Required R Undefined Required Cause Write Read / are interpreted as the Requested Interrupt ed Resource Architec ed Resource 10 9 8 7 6 atched. With the atched. With 7..2 for IP 9.36 Cause Register (CP0 describes the describes was zero Field Descriptions Field Descriptions EXL interrupts are disp Table 9.52 Table Status is field is loaded by hard- is loaded by field is UNPREDICTABLE Meaning Meaning e 1 of the Architecture, this this Architecture, the 1 of e ASEASE IP9..IP2 RIPL IP1..IP0 0 Exc Code 0 se of the most recent exception. In addition, fields also control soft- fields also control addition, of the most recent exception. In se bits for other interrupt IP only if and returns zero on read. exception taken occurred in a in occurred taken exception register; BD register are read-only. Release 2 of theadded Architecture optional support register are read-only. Description 000 Cause Cause III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Figure 9.37Figure Format Register Cause . 01 in delay slot Not In delay slot 01pending interrupt is timer No pending is interrupt Timer Table 9.52Table Register Cause Encoding Encoding Required ).

all exceptions except Unusable. all exceptions for Coprocessor branch delay slot: branch The processor updates Unusable exception is taken. exception Th Unusable on ware every exception, but is bit must be written as zero as must be written bit types): types): Releas an implementation of In when the exception occurred. Architecture, this bit denotes whether a timer interrupt is interrupt a timer whether this bit denotes Architecture, (analogous to the pending RIPL shows the format of the shows register primarily describes the cau describes primarily register fields, all fields in the WP Cause Fields , and IV Compliance Level: The for External an Interrupt Controller (EIC) interruptin mode, which Figure 9.37 Figure Priority Level( ware interrupt requests and the vector through which

TI 30 of Release Interrupt. In an implementation 2 of the Timer CE 29..28 unit when a Coprocessor Coprocessor number referenced BD 31 whether the Indicates last Name Bits 31 30 29 28 27 26 25 24 23 22 21 20 17 15 MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.36 Select 0) Register 13, (CP0 Cause Register BD TI CE DC PCI ASE IV WP FDCI

2) Required for 2 and perfor- implemented) mance counters erwise Reserved erwise MCU ASE; Oth- State Compliance Reset ged Resource Architecture, Rev. 6.02 R Undefined (Release Required R/W 0 Required (Release R/W Undefined Required Write Read /

is PC BEV Config1 Status register register d Descriptions (Continued) d Descriptions on uses the general Count er-sensitive applica- er-sensitive Count is 1 and IV these bits return zero on zero return bits these Meaning for other interrupt types): Meaning Meaning rmance counter interrupt is rmance counter interrupt e 1 of the Architecture, this this Architecture, the of 1 e e 2 of the architecture (and representsthebase of the (and subsequent releases), power dissipation. This bit This bit power dissipation. , and returns zero on read. zero , and returns ecial interrupt vector: vector: interrupt ecial l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. Description itten with zeros. zeros. with itten ), if the Cause the if ), an interrupt excepti interrupt an register to be stopped in such situations. register to be (0x180) (0x200) pending ing register is not used but may still be the be still may is not used but register register. In some pow register. nt Count Count 01 Use the general exception vector vector interrupt special the Use 01of Enable counting of counting Disable 01is interrupt counter performance No pend- counter interrupt is Performance Cou Encoding Encoding Encoding subsequent releases In implementations of Releas In implementations exception vector or a sp exception vector or If MCU ASE is not implemented, reads and must be wr = 0), this bit must be written as zero and returns zero on zero returns and zero as written be must bit this 0), = read. tions, the the tions, Releas implementation of an In zero as must be written bit source of some noticeable the allows pending (analogous to the IP bits or Architecture, 1 the of of Release In an implementation are not implemented ( counters performance if this bit denotes whether a perfo this Release 2 of the Architecture the 2 of Release 0, the special interrupt vector 0, the table. vectored interrupt Table 9.52Table Fiel Register Cause Fields IV 23 Indicates whether DC 27 Disable PCI 26 an implementation of In Interrupt. Counter Performance ASE 17:16 25:24, These bits are reserved for the MCU ASE. Name Bits 210 MIPS® Architecture Vo For Programmers

registers are are registers implemented Register13, 0) Select ture, Rev. 6.02 Rev. ture, 211 State Compliance Reset R Undefined Required R Undefined Required R/W Undefined if watch Required Write Read / ed Resource Architec ed Resource

ERL 9.36 Cause Register (CP0 field, Status RIPL UNPRE- are both zero. are and ERL d Descriptions (Continued) d Descriptions Meaning deferred because deferred EXL ld not write a 1 to this bit ld not write a 1 to this Status Meaning = 1), these bits take on a Status bit both indicates that the that indicates bit both e 2 of the Architecture (and h EIC is h EIC interrupt mode not interrupt. If EIC interrupt If EIC interrupt. and upt. This bit denotes whether a VEIC werea one at the timewatch the ception was EXL = 0), timer and performance coun- performance and timer = 0), Description ERL VEIC Config3 rdware ignores a write of 1. a write of ignores rdware Status III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Status whether hardware ignores the write, accepts the ignores whether hardware or an interrupt is pending: interrupt an Config3 01pending interrupt is FDC No is pending interrupt FDC 11 IP3 Hardware interrupt 1 1514 IP713 IP612 Hardware interrupt 5 IP5 Hardware interrupt 4 IP410 Hardware interrupt 3 Hardware interrupt 2 IP2 Hardware interrupt 0 EXL Bit Name Encoding

ter interrupts are combined in implementation-depen- an in combined are interrupts ter dent way with any hardware is enabled ( mode exception was detected. This Status to exception the and causes deferred, was exception watch once initiated be FDC interrupt is pending: As such, software must clear this bit as part of the watch as part of the watch this bit clear must As software such, exception loop. handler to prevent a watch exception For Pre-Release 6, software shou are both zero. For Release 6, ha bit must be this implemented, are not registers If watch as on write and read ignored zero. subsequent releases) in whic when its value is a 0, thereby causing a 0-to-1 transition. If transition. 0-to-1 a causing thereby 0, is a value its when is software, it is caused by a transition such timer 1 of the Architecture, of Release In implementations in an and interrupts are combined performance-counter way with hardware implementation-dependent interrupt 5. of Releas In implementations enabled ( DICTABLE ini- and the write or accepts no effects, with side write the once exception watch a tiates different meaning and are as the interpreted different below. described Table 9.52Table Fiel Register Cause Fields WP 22 ex a watch that Indicates FDCI 21 Channel Interr Debug Fast Name Bits IP7..IP2 15..10 Indicates MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

field to rupt mode only) 2 and EIC inter- 2 and EIC DExcCode State Compliance Reset ged Resource Architecture, Rev. 6.02 e processor is running in EJTAG running in EJTAG processor is e 0 0 Reserved R Undefined (Release Optional R Undefined Required R/W Undefined Required AG is implemented and an SDBBP implemented and an AG is Write Read / a reference: load or store) load a reference: on (load or instruction fetch) instruction or on (load = 0), 0), = ruction exception VEIC d Descriptions (Continued) d Descriptions Config3 Meaning denote an SDBBP in Debug Mode. denote an SDBBP in Debug instruction is instruction executed while th to the Debug is written value this Debug Mode, external interrupt controller interrupt external e 2 of the (and Architecture e 2 of the Architecture (and ich EIC interrupt mode is mode ich EIC interrupt l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. = is 1), this field the encoded Description RI Reserved inst Int Interrupt Bp If exception. EJT Breakpoint Table 9.53 Sys exception Syscall IBE Bus error exception (instruction fetch) CpU Unusable exception Coprocessor Mod modification exception TLB DBE Bus error exception (dat AdES exception (store) error Address TLBS TLB exception (store) AdEL Address error excepti TLBL TLB exception (load or instruction fetch) ) which also implements EIC interrupt EIC interrupt also implements ) which st for software interrupts: VEIC , described above. , described Mnemonic Description Table 9.53Table Field ExcCode Register Cause Config3 98 IP1 IP0 1 interrupt software Request 0 interrupt software Request Bit Name 0x0a 0x0b 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 these bits take on a different and are interpreted meaning bits take on a different these as the IP..IP2 bits Must be written as zero; returns zero read. on (0..63) value of the requested interrupt. A value of zero of value A interrupt. requested the value of (0..63) is requested. interrupt no that indicates mode is If EIC interrupt not enabled ( In implementations of Releas In implementations wh subsequent releases) in enabled ( An implementation of Releas An implementation subsequent releases for prioritization sources. with other interrupt mode exports these bits to the exports these bits to mode Table 9.52Table Fiel Register Cause 1..0 1 0 2 5 6 3 4 7 8 9 11 10 Fields Exception Code Value Code Exception Decimal Hexadecimal

0 20..16, 7, RIPL ..10 Interrupt Priority Level. Requested Name Bits IP1..IP0 9..8 Controls the reque ExcCode 6..2 Exception code - see 212 MIPS® Architecture Vo For Programmers

that re-entry to Register13, 0) Select ture, Rev. 6.02 Rev. ture, 213 ception has a dedi- ception duling Exceptions duling (MIPS® to indicate field rs while in Debug Mode, this Mode, Debug in rs while er is not updated. If EJTAG is er is not updated. If EJTAG “Software Hazards and the Interrupt Hazards “Software DExcCode le Exception (MDMX ASE). MDMX ode, a cache error ex ed Resource Architec ed Resource ed by a cache error. ed by a cache e Coprocessor 2 exceptions 2 e Coprocessor 9.36 Cause Register (CP0 plementation-dependent use plementation-dependent on, Deallocation, or Sche erflow exception the EHBtheinstruction used can be to makeinterrupt state on-Inhibit exception on-Inhibit , register is written. See cated vector and the regist Cause implemented and a cache error occu code is written to the Debug to the is written code deprecated with Revision 5. (MIPS® DSP Module) Debug Mode was caus Mode was Debug MT Module) Cause - Reserved - im for Available Tr exception Trap Ov Arithmetic Ov GE Guest Exception Virtualized FPE exception Floating-Point C2E precis Reserved for Thread Thread Allocati TLBRI TLBRI TLB Read-Inhibit exception TLBXI TLB Executi TLB TLBXI DSPDis exception Disabled Module State DSP MDMX Previously MDMX Unusab WATCH address Reference to WatchHi/WatchLo MCheck Machine check MSADis exception Disabled MSA CacheErr m In normal Cache error. MSAFPE exception MSA Floating-Point Mnemonic Description III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: field of the e (and the subsequent releases) 1..0 Table 9.53Table Field (Continued) ExcCode Register Cause 0x0f 0x1e 0x0c 0x0e 0x1a 0x17 0x1b 0x0d 0x18 0x19 0x13 0x14 0x15 0x16 0x12 . 30 23 24 27 31 0x1f - Reserved 13 14 25 12 26 22 15 18 19 20 21 28-290x1d 0x1c - 16-17 0x10-0x11 Exception Code Value Code Exception Decimal Hexadecimal System” on page on System” 82 Programming Note: Programming 2 of the Architectur Release In changes visible when the IP visible changes MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 214 MIPS® Architecture Vo For Programmers

ERL Status and ERL EXL 0 32 1 0 EXL ture, Rev. 6.02 Rev. ture, 215 register fields. Status State Compliance Reset termined by reading termined by reading the NestedExc R Undefined Required R Undefined Required Write Read / ed Resource Architec ed Resource

9.37 NestedExc (CP0 Register 13, Select 5) - EXL describes the describes er containing of values the Status ErrorEPC the register can be de be can register the er Field Descriptions Descriptions Field er Table 9.54 terrupt, Address Error, Error, terrupt, Address scall, FPU, etc.). theseFor register; 0 field is updated regardless of field is updated regardless . Description prior to acceptance of current excep- prior to acceptance of current excep- EXL NestedExc ) register is a read-only regist ) register Fault feature, existence of feature, existence Fault ERL EXL III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: gister 13, Select 5) gister . Not updated by Debug exceptions. . Not updated by Debug exceptions. Figure Figure 9.38 Format Register NestedExc Status is not set (MCheck, In

ERL Status Status EXL Table 9.54Table Regist NestedExc NestedExc ( the current exception. Status Optional.

tion. set either would that by all exceptions Updated types which update updated by exception Not tion. by Updated exceptions which would update EPC if Status or all TLB exceptions, Bus Error, CopUnusable, Reserved Reserved CopUnusable, Error, Bus exceptions, all TLB Sy Trap, Overflow, Instruction, this exception types, register the value of (Reset, Soft Reset, NMI, Cache Error). Not updated by Not updated Cache Error). Reset, NMI, Soft (Reset, Debug exceptions. bit. shows the format of the shows NFExists Nested Exception Fields Figure 9.38 Figure Config5 Compliance Level: The prior to acceptance of to acceptance prior This registerof is part the Nested

0 31..30. as read Reserved, R0 0 Required 0 00. as read Reserved, R0 0 Required ERL 2 of Value EXL 1 of Value Name Bits 31 MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.37 (CP0 Re NestedExc ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 216 MIPS® Architecture Vo For Programmers

0 register to determine ture, Rev. 6.02 Rev. ture, 217 register requires special register requires EPC at which processing at which processing resumes EPC State Compliance Reset register when an exception register is set. register fields. EPC t and mustt and be writable. ruction, when the exception causing the exception causing ruction, when Cause EPC R/W Undefined Required ich processing resumes with the value of Write Read / ed Resource Architec ed Resource 14, Select 0) 14, Select exception, or of the bit in the that contains the that contains the address describes the PS32 base architecture, the PS32 base in Processors that Implement MIPS16e register are significan register are Field Descriptions Field Descriptions ecution of the ERET instruction. the processor writes the writes the processor Branch Delay 9.38 Exception Program Counter(CP0 Register 14, Select 0) EPC contains contains the address of the ructioninst at which to resume execu- Table 9.55 Table was was the direct cause contains either: (CP0 Register (CP0 Register EPC EPC ately preceding branch or jump inst ately preceding branch register; ) read/write register is a Description EPC register, it combines the address at wh address the it combines register, Figure 9.39Figure Format EPC Register EPC III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: ( register is already a 1, EPC . register as the result of ex result of the register as register to change resume the processor address and read the t the MIPS16e ASE or microMI Table 9.55Table EPC Register Base Architecture Status EPC EPC Required

ssor writes the the writes ssor bit in the the in bit register: shows the format of the the shows EXL instruction is in a branch delay slot, and the instruction is in a branch delay slot, and tion. • virtual the instructionthe of address that •immedi the of virtual address the Exception Program Counter ISA Mode Fields The processor reads reads The processor the

handling. When the proce the In processors that implemen Compliance Level: The occurs. • synchronous For (precise) exceptions, after an exception has been serviced. All bits of the EPC All bits of has been serviced. after an exception Unless the at what address the processor will resume. will the processor address at what 9.39 Figure • asynchronous For (imprecise) exceptions, Software may write the EPC 31..0 Exception Program Counter Name Bits 31 ASE or microMIPS32 9.38.1 Handling of the EPC Register Special MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.38 Program Counter Exception

registers: ged Resource Architecture, Rev. 6.02 ISAMode and PC valuewritten with no interpretation. Software reted by the processor as described above. described as processor by the reted 0 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. ocessing resumes, as described above. register, it distributesthe the bitsto register, EPC  ISAMode register simplyregister return the last a GPR to 31..1 0 EPC  0 ePC registera newvalueis which interp store 31..1 EPC  EPC PC  EPC ISAMode EPC  resum EPC writes to the When the processor reads reads processor the When the Software readsthe of “resumePC” is at which the address pr 218 MIPS® Architecture Vo For Programmers

. reg- 0 EPC NestedEPC register fields. register ture, Rev. 6.02 Rev. ture, 219 State Compliance the occurrence of any excep- Reset NestedEPC termined by reading termined by reading the ith thesame behavior as the R/W Undefined Required Write Read / ed Resource Architec ed Resource - instructions. Software is requiredto copy the describes the ErrorEPC the register can be de be can register the and is therefore updatedon and is therefore Table 9.56 EXL ter (CP0 Register 14, Select 2) Register ter (CP0 ) is a w read/write register Status terrupt, Address Error, Error, terrupt, Address NestedEPC register if it is desired to return to the address stored intoregister the address desired to return is if it register; register; scall, FPU, etc.). theseFor field is updated regardless of field is updated regardless 9.39 Nested Exception Program Counter (CP0 Register 14, Select 2) EPC NestedEPC . ( Description EXL NestedEPC Fault feature, existence of feature, existence Fault III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Status Figure 9.40Figure Format Register NestedEPC is not set (MCheck, In

register to the register EXL Table 9.56Table Field Descriptions Register NestedEPC register ignoresof the value registerthebyused is not ERET/DERET/IRET Optional.

Not updated by exception types which update types which update updated by exception Not Updated by Updated exceptions which would update EPC if Status all TLB exceptions, Bus Error, CopUnusable, Reserved Reserved CopUnusable, Error, Bus exceptions, all TLB Sy Trap, Overflow, Instruction, this exception types, register the value of (Reset, Soft Reset, NMI, Cache Error). by Debug exceptions. Not updated NestedEPC bit. shows the format of the the shows NestedEPC NestedEPC NFExists tion, including nested tion, including nested exceptions. value of the Nested Exception Program Counter Fields •The

Figure 9.40 Figure This registerof is part the Nested Config5 Compliance Level: The ister except that: •The Name Bits 31 NestedEPC 31..0Counter Nested Exception Program MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.39 Coun Program Exception Nested ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 220 MIPS® Architecture Vo For Programmers

0 shows Optional Optional Required Required Revision ture, Rev. 6.02 Rev. ture, 221 P0 Register 15, Select 0) State Compliance Reset hardware hardware hardware hardware 8 7 R Preset by R Presetby R Preset by R Preset by Write Read / thatcontains information identifying the ed Resource Architec ed Resource Processor ID register fields. register 9.40 Processor Identification (C PRId d allows software d allows r implementations 16 15 this field for zero. If it is it If zero. for this field The value in this field is in this field The value . If this field is not imple- not field is this . If Meaning ds creates a unique number ds ish between one revision and ber of the processor. This field ber of the processor. describes the describes or manufacturer of the processor processor the of manufacturer or that designed or manufactured or that designed manufactured the Description processor. This processor. fiel d above. The combination of the Com- een various processo een various ) register is a 32 bit read-only register bit read-only 32 is a ) register the list of Company ID assignments ID of Company the list MIPS64/microMIPS64 processor Figure 9.41Figure Format Register PRId Company ID III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Table 9.57 Table . PRId ( options, processor identification and revision level of the processor. Figure 9.41 options, processor identification andrevision level of the processor. Table 9.57Table PRIdRegister Field Descriptions 01 a MIPS32/microMIPS32 Not or Inc. Technologies, MIPS 2-255for Inc. Contact MIPS Technologies, register; register; Encoding 24 23 Required

for company-dependent options. not by the specified architecture mented,must itread as zero. processor. a MIPS32/microMIPS32 or Software can distinguish one implementing processor from MIPS64/microMIPS64 an earlier MIPS ISA by checking non-zero the processor implements the MIPS32/ processor implements the non-zero Architecture. or MIPS64/microMIPS64 microMIPS32 when a by MIPS Technologies IDs are assigned Company or license MIPS32/microMIPS32 MIPS64/microMIPS64 is acquired. in this field are: The encodings to distinguish betw distinguish to within a single company, and is qualified by the Compa- by and is qualified company, single a within nyID field, describe panyID fiel and ProcessorID implementation. processor to each assigned allows software to distingu to software allows another of the same type. this field is not If processor implemented,it must read zero. as PRId 31..24 the designer to Available Processor Identification Processor Fields Company Options the format of the the format of manufacturer, manufacturer manufacturer,

Compliance Level: The Name Bits Options Revision 7..0 Specifies the revision num 31 Company Company Company IDCompany 23..16 Identifiesthe company Processor ID 15..8 type of Identifies the MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.40 0) 15, Select (CP0 Register Identification Processor

register value, register value, PRId ged Resource Architecture, Rev. 6.02 r configuration information about the processor. Rather, the Rather, configurationr information about processor. the ient, requiring them to revert to check on the on revert to check to them requiring ient, l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. [email protected] case. the , reporting ilities of the processor. Programmers who identify cases cases who identify Programmers configurationregisters should be used to determine processor. the capabilities of the in whichnot the configurationsuffic are registers Software shouldthisuse not thefields register of toinfe should send email to 222 MIPS® Architecture Vo For Programmers

BEV is 0. Status BEV describes the 6.2.2 “Exception Status 0b10,and the addi- ture, Rev. 6.02 Rev. ture, 223 be in the kseg0 or kseg1thebe in kseg0 or equal 1. The operation of CPUNum thina multi-processor sys- For the write-gate case, the For the write-gate case, BEV Status lly in systems composed of heteroge- lly in systems composed erent value when when erent value detect the existence of the write-gate by detect the existence the exception vectors used when the exception vectors ed Resource Architec ed Resource 0 0 0 address space. To ensure backward compati- space. To address w the bitsupper of the Exception Base field to 12 11 10 9 0 9.41 EBase Register (CP0 Register 15, Select 1) it 29is forced toa 1 in theultimate exceptionbase are fixed with the value register itten with a diff 0x8000.0000, providing backward compatibility with ed by software to distinguish different processors in a to distinguishsoftware ed by different tify the specific processor wi tify the specific processor e upper bits can be changed. ces the final exception address to EBase is 1, or for any EJTAG Debugbits exception. 31..12 of The reset state any EJTAG for 1, or is e kseg1 unmapped, uncached virtual address segment. error exceptions, b BEV Table 9.58 ; Table implemented. if the write-gate is not register to form the base of the exception with zeros to form the base are concatenated register each processor to be different, especia different, each processor to be exception offset is performed inhibitingexceptionoffset a carry between29 bitsof and 30 the er containing the base address of Status ceptionregister to base if multithreading is implemented. EBase EBase Register 15, Select 1) 15, Select Register mpute location. Software can the vector III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Figure 9.42 EBaseRegister Format ) when (Release 2). (Release Exception Base register can be optionally extended to allo ception vectors to be placed anywhere in the in to be placed anywhere ception vectors The is 0. exception vector base address comes from the fixed defaults (see EBase Required BEV

if the Exception Base field is wr Exception UNDEFINED if the Status register initialize the ex register initialize the shows the format of the shows register provides theability for software to iden register is a read/write regist register is a read/write register fields. EBase EBase EBase full set of bits 31..12 are used to co writingthat one toposition bit the and checking was set. bit if and the the base address of The addition final exception address. is to beIf the value of the exception base register changed, this must be done with Release 1 implementations. Release 1 If the write-gate bit is not implemented, bits 31..30 of the of the the processor is be written. This allows ex be written. This allows bilitywith MIPS32, the write-gate bit before th be set must Vector Locations” on page 84 EBase Compliance Level: The equals 0, and a read-only CPUread-only number 0, and a equals value that may be us multi-processor system. The neous processors. Bits 31..12 of theneous Bits 31..12 of processors. tem, and allows the exception vectors for vectors exception tem, and allows the Release 6 reuses the field CPUNum reuses Release 6 9.42 Figure vectors when tion of the base address and the exception offset is done inhibiting is done carry betweentionexcep-finalthebitand of the base address and the exception a bit 29 offset 30 of tion address. Thecombination these of two restrictions for segments. For cache address virtual unmapped runs in th always this exception so that address The operation of the

1 0 31 30 29 MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.41 (CP0 EBase Register

EBase Required describes the CPUNum State Compliance State Compliance Reset Reset nally Set nally or Exter- hardware Table 9.59 ged Resource Architecture, Rev. 6.02 0 0 Reserved R Preset by R/W 0x80000 Required R/W 0 Required R/W 0 Required Write Write Read / Read Read / Read 0 WG is zero. 12 11 10 9 0 for usage. -gate is implemented. implemented. -gate is BEV register 0. register Status RDHWR hers. The value in this field field in this value The hers. this field specifies the base base the specifies field this by software to distinguish a to distinguish by software Section 9.8, "Global "Global Section 9.8, r hardware when the proces- em environment. In a single by VPNum to indicate by the gister 3, Select 1)," address address of the exception vec- ading, CPUNum can be used CPUNum can ading, registerwrite if the Description Description l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. is zero. BEV EBase Figure 9.43 EBaseRegister Format Table 9.58Table EBase Register Field Descriptions Table 9.59Table EBase Register Field Descriptions Exception Base Exception address of the exception vectors when when vectors exception of the address Bits 31..30 can be written only when WG is set. When When set. is WG when only written be can 31..30 Bits write. on unchanged bits are zero, these WG is when WG=0 in the value being written. The WG bit must WG bit must The being written. value in the when WG=0 of the values bits to change value in the written be set true 31..30. tors when Status cessor system and can be used particular processor from the ot the from particular processor is set by inputs to the processo in the syst sor is implemented system, this value should be processor set to zero. This field can also be read through Number Register (COP0 Re In Release 6 of the architecture, with multi-threading sup- with multi-threading architecture, 6 the of Release In CPUNum ported, is replaced See virtual processor number. of multi-thre absence the In as defined. shows the format of the 29..12 31..30, conjunction with bits In 31..12 field specifies the This base Fields Fields Figure 9.43

register fields. 10 31 30 bit is ignored This on write and returns one on read. bit is ignored This on write and returns zero on read. R R 1 0 Required Required 0 11..10 read. zero on returns zero; as be written Must WG 11 gate. Bits 31..30 are on writes to EBase unchanged Write Base Base 31 Name Bits Name Bits CPUNum 9..0 CPU in a multi-pro- of the the number specifies field This Exception Exception Exception Exception 224 MIPS® Architecture Vo For Programmers

bits EBase Required ture, Rev. 6.02 Rev. ture, 225 Set 63 State Compliance   Reset      Externally Externally VN VN VN VN VN ) if this condition is not met. Table 1 VS Ror Preset R0 0 Reserved represents the interrupt vector number the interrupt represents Write Read / Read VN       ed Resource Architec ed Resource VN VN VN VN UNDEFINED 9.41 EBase Register (CP0 Register 15, Select 1) for usage.     VN VN eld Descriptions (Continued) eld Descriptions bit must bitzero. to be set hers. The value in this field field in this value The hers. by software to distinguish a to distinguish by software Section 9.8, "Global "Global Section 9.8, r hardware when the proces- em environment. In a single   by VPNum to indicate by the gister 3, Select 1)," ading, CPUNum can be used CPUNum can ading, turns zero on read. zero on turns EBase vector offset greater than 0xFFF is generated when anvector interrupt offset occurs with Description Interrupt Vector Spacing in Bytes (IntCtl Spacing Interrupt Vector III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: to zero in allpositions bit less than or equal to the most-significantbit in off- the vector and thetoandmust bit zero if any be set relationships of thein are true. the row No 15..12 In the absence of multi-thre absence the In as defined. Number Register (COP0 Re virtual processor number. See virtual processor number. particular processor from the ot the from particular processor is set by inputs to the processo in the syst sor is implemented should be system, this value processor set to zero. This field can also be read via RDHWR register 0. sup- with multi-threading architecture, 6 the of Release In CPUNum ported, is replaced cessor system and can be used Table 9.59Table Fi Register EBase Table 9.48 on page 199 12 VN 1513 None None None None None VN VN 14 None None VN Table 9.60Table Be Zero Must EBase15..12 Which Under Conditions Table 6.4 EBase bit 32 64 128 256 512 1. See 10 re zero; as be written Must interrupt modeThe operation enabled. of the processor is EIC Fields or as described in in as described mustbeset tozero if theinterrupt vector spacing is 32 (or zero) bytes. Programming Note: Programming Software must set EBase set. This situation can only occur when a VI shows the conditions under which each the conditions under which 9.60 shows 0 Name Bits CPUNum 9..0a multi-pro- CPU in of the the number specifies field This MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 226 MIPS® Architecture Vo For Programmers

register field. register field. If

MVP CDMMSize ture, Rev. 6.02 Rev. ture, 227 State Compliance Reset VPEConf0 R Preset Optional R Preset Required EN CI R/W 0 Required R/W Undefined Required Write Read / 11 10 9 8 0 ed Resource Architec ed Resource describes the register fields. the register describes a write tothis register is ignored. ster ster is controlled by the 9.42 CDMMBase Register (CP0 Register 15, Select 2) Table 9.61 byte Device Reg- Meaning Meaning on behavior not IO on behavior and are mory. If this bit is set, mory. physical address bits is physical register, and register, ical address of the memory that the first 64- d, returns zero on read. d, returns Description the number of 64-byte Device Regis- P0 Register 15, Select 2) 15, Select P0 Register Figure 9.44Figure Register CDMMBase III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: CDMMBase this register returns this zeros all and ltiple VPEs, access to this regi to this access ltiple VPEs, is set toone. is 01 Region is CDMM disabled. CDMM Region is enabled. DRB DRBs 01 DRBs 12 23 ...... 511 512 DRBs CDMM Encoding Encoding Table 9.61Table Descriptions Field Register CDMMBase CDMM_UPPER_ADDR reserved for additional regis- for additional ister Block of the CDMM is reserved manage CDMM regi ters which device registers. ter Blocks are instantiated in the core. in the core. instantiated Blocks are ter If this bit is cleared, memory requests to this address to this address requests memory bit cleared, If this is system region go to regular me the CDMM logic to go region this to memory requests implementation specific. For the unimplemented address address unimplemented the For specific. implementation ignore are writes - bits mapped registers. mapped registers. of The number implemented Optional.

Config3 the format of has the 31:11base phys the of Bits 35:15 bit is cleared, a read to bit is cleared, a MVP Fields For devices that implement mu that implement For devices Compliance Level: The 36-bit physical base address for the This Commonregis- Device Memory Map facility is defined by this register. ter only exists if the Figure 9.44 Figure CI 9 indicates this 1, to set If EN 10CDMM region. the Enables Name Bits CDMMSize 8:0 represents field This CDMM_UP PER_ADDR 31 MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.42(C Register CDMMBase ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 228 MIPS® Architecture Vo For Programmers

Required 0 ture, Rev. 6.02 Rev. ture, 229 Register 15, Select 3) State Compliance Reset hardware (IP Configu- ration Value) R Presetby Write Read / ed Resource Architec ed Resource describes the register fields. 11 10 0 is set to one. to set is instantiated once per processor. once per instantiated CMGCR 9.43 CMGCRBase Register (CP0 Coherency Manager Global Configuration Register space Coherency Manager ster Field Descriptions Field ster Config3 physical address bits is physical register, and Table 9.62 register, ical address of the memory- ger GCR registers. registers. ger GCR d, returns zero on read. d, returns Description PS MT Module, this register is register Module, this PS MT Figure 9.45Figure Register CMGCRBase III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: CMGCRBase is register only exists if if exists only register is Table 9.62Table CMGCRBase Regi CMGCR_BASE_ADDR This register field reflects This the value of the register field reflects GCR_BASE field withinManager the memory-mapped Coherency GCR Base Register. of The number implemented address unimplemented the For specific. implementation ignore are writes - bits mapped Coherency Mana mapped Coherency Optional.

the format of has the 31:11base phys the of Bits 35:15 Fields Figure 9.45 Figure is reflected by this register. Th register. is reflected by this Compliance Level: for the memory-mapped base address physical The 36-bit On devices that implement the MI that implement the On devices 0 10:0 on read returns zero zero; as be written Must 0 0 Reserved Name Bits CMGCR_B ASE_ADDR 31 MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.433) 15, Select Register (CP0 Register CMGCRBase ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 230 MIPS® Architecture Vo For Programmers

0 , Select 4) , Select =1). Required Required EVA Mask Register 15 Register ture, Rev. 6.02 Rev. ture, 231 Config5 erlaya configurable is vir- hardware or Preset by or Preset 8 7 to specify the Boot to specify Exception Vec- R Externally set Write Reset State Compliance 0 Read/ ed Resource Architec ed Resource 12 9.44(CP0 Register BEVVA register fields. the describes BEVVA supports only EVA, one For an implementation only EVA, that supports in order toa configurable map tophysicaladdress. in order erlaps with BEV. The BEV Ov The BEV erlaps with BEV. er Field Descriptions lity into BEV since the address is pin configurable i.e., not Table 9.63 at the virtual captures used address Description quires a means to read BEV. the programmable to support Release 5 Enhanced Virtual Addressing (EVA). In addition, can it Addressing (EVA). to support Release 5 Enhanced Virtual implementation must guarantee BEVVA correspondssingle to the overlay that implementation must guarantee BEVVA 20 19 register; BEVVA Register 15, Select 4) 15, Select Register III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Figure 9.46Figure Format Register BEVVA Base e core, otherwisepins the may be hardwireda non-legacy to value. . if Release 5 Enhanced Virtual Addressing is supported ( i.e., if Release 5 Enhanced Virtual . Table 9.63Table Regist BEVVA Required

The BEV address is the aligned on a 4KB within boundary maximum and 1MB minimum of is a BEV overlay which of 256MB in size. register is a read-only register th a is register shows the format of the the shows 27 BEVVA BEVVA Fields The Compliance Level: tor when it is programmable as required programmable is tor when it which ov BEV Overlay the size of the be used to determine tual addresstualthat range overlays kernel unmappedsegment(s) The purpose of this register is tovisibipurpose provideregister is software of thisThe throughsettable COP0. is It optional implementation for an toallow programmability ofthrough the pins a memory- to th mapped register external requiredmaps,it address tosupport is twoconfigu- For32-bita implementation that supportsboth legacyand EVA unmapped cached and uncached addresses. overlays, for rable to mapoverlay a virtualis sufficient address within therange of the overlay to an implementation-dependent physical supported, the Where two are address. re software as mode, in EVA is in effect 9.46 Figure

011:80 0 0Reserved Base 31..12 Address (BEV) Virtual Boot Exception Vector 31 Name Bits 9.44 (CP0 Register BEVVA MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

Required hardware or Preset by or Preset ged Resource Architecture, Rev. 6.02 R Externally set Write Reset State Compliance Read/ er Field Descriptions define size of overlay: define size of , that is, , that shown above is not supported not supported shown above is Base l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. Description of Table 9.63Table Regist BEVVA is encoded as follows to encoded is Applies to bits 27:20 BEV_Overlay[31:20] = BEVVA[31:20] & (0xf || ~Mask) = BEVVA[31:20] BEV_Overlay[31:20] Mask 8’b00000000 - 1 MB - 1 8’b00000000 MB - 2 8’b00000001 - 4 MB 8’b00000011 - 8 MB 8’b00000111 MB 16 - 8’b00001111 - 32 MB 8’b00011111 - 64 MB 8’b00111111 - 128 MB 8’b01111111 8’b11111111 - 256MB that other than An encoding and causes UNDEFINED results. Fields Mask 7:0 size to define the of the Mask overlay. Name Bits 232 MIPS® Architecture Vo For Programmers

, K0 reg- , and Config KU Optional Optional Required , K23 ture, Rev. 6.02 Rev. ture, 233 P0 Register 16, Select 0) 1 wise wise Undefined Optional register fields. Fixed Mapping Mapping Fixed Fixed Mapping Mapping Fixed MMU; 0 other- MMU; 0 other- processors with a processors with a Config on. Most of the fields in the in fields on. Most of the R e constant. Three fields, e constant. ed Resource Architec ed Resource R/W for Undefined R/W for Undefined Write Reset State Compliance Read / Read describes the describes 9.45 (C Register Configuration BE AT AR MT 0 VI K0 cheability and Table 9.64 Table 16 15 14 13 12 10 9 7 6 4 3 2 0 Exception process, or ar process, Exception eld readseldand as zero is s as zero and is ignored on register; igurationcapabilities and informati e format and definition of definition e format and nizations” on pagenizations” on 313 for a nizations” on pagenizations” on 313 for a essors that do not implement cacheability and coherency and cacheability for the encoding of this field. of encoding for the for the encoding of this field. of encoding for the 2 and kseg3 ca 2 and kseg3 at do not implement a Fixed do not at Config Impl Description for implementations. Refer to the Refer implementations. for III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: implement implement a Fixed Mapping MMU, implement implement a Fixed Mapping MMU, Figure 9.47Figure Format Register Config es of unsupported values are ignored. es of unsupported values are ignored. register is implemented at at a is Config1implemented register . Table 9.64Table ConfigRegister Field Descriptions Required

“Alternative MMU Orga MMU “Alternative Table 9.12 on page 133 “Alternative MMU Orga MMU “Alternative Table 9.12 on page 133 processor specification for th processor specification this field this field specifies the kuseg the specifies field this attribute. For th processors read MMU, this field Mapping write. See of the description Fixed Mapping MMU organization. See For Release 6, writ ignored on write. on ignored See a Fixed Mapping MMU, this fi of the description Mapping Fixed MMU organization. See For Release 6, writ select field value of 1. For proc coherency attribute. this field specifies the kseg the specifies field this shows the format of the shows register specifies various conf specifies register Config Fields ister are initialized by hardware during the Reset must be initialized by software in the reset exception handler. 9.47 Figure Compliance Level: The

M 31 Denotes that the KU 27:25 that For processors 31 30 28 27 25 24 M K23 KU K23 30:28 that For processors Impl 24:16reserved This field is Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.45 0) 16, Select (CP0 Register Register Configuration

Required Required Required nally Set nally hardware hardware ware or Exter- ged Resource Architecture, Rev. 6.02 Rby hard- Preset R Preset by R Preset by Write Reset State Compliance Read / Read eld Descriptions (Continued) eld Descriptions PS64 with access access with PS64 the processor is run- the processor the ISA register field of register is not is not Config3 register Meaning Meaning Meaning of 0-2, denotes address of 0-2, denotes address If If Config3 or other register l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. is one, then MIPS32 is not is not MIPS32 then is one, in which on sets (MIPS32/64 and/or Description field is not used. field is not Config3. Config3 only to 32-bit compatibility segments compatibility 32-bit to only to all address segments All features introduced in Release 3 detect- and are optional 5 and Release able through fields. field of 23 access with microMIPS64 MIPS64or Reserved 1Big endian 01Big endian Little 01 or microMIPS32 MIPS32 or microMI MIPS64 01 Release 1 Release 2 or Release 3 or Release 5 2 Release 6 3-7 Reserved ISA Table 9.64Table Fi Config Register Encoding Encoding Encoding the ning: For Release 3, encoding values Config3. and register width (32-bit or 64-bit). and width (32-bit register instructi implemented The microMIPS32/64) denoted by are implemented then microMIPS is not implemented. microMIPS implemented then If vision level is denoted by revision level Architecture microMIPS32 the MMAR field of implemented and this implemented and Encoding 2 is new for Release 6. Fields AT 14:13 implemented by the processor. Architecture Type BE 15 Indicates the endian mode AR 12:10level. Architecture revision MIPS32 Name Bits 234 MIPS® Architecture Vo For Programmers

equired Required R Reserved ture, Rev. 6.02 Rev. ture, 235 P0 Register 16, Select 0) 0 hardware hardware 0 R Preset by R Preset by ed Resource Architec ed Resource R/W Undefined Required Write Reset State Compliance Read / Read Table 9.45 (C Register Configuration “Dual “Dual ) eld Descriptions (Continued) eld Descriptions ) “Fixed Mapping “Fixed Mapping ) “TLB “TLB and Fixed-Page- is not virtual e is virtual Meaning Meaning “Block Address Translation” Translation” Address “Block (using both virtual and indexing coherency attribute. See coherency Description III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: es of unsupported values are ignored. Standard TLB (See Standard Organization” on pageOrganization” 32 BAT (See BAT on page) 317 (See Fixed Mapping MMU” on pageMMU” on 313 Variable-Page-Size Dual VTLB and FTLB (See page on Size TLBs” 319 for the of encoding this field. 01 None 01 Instruction Cache Instruction Cach 2 3 4 Table 9.64Table Fi Config Register Encoding Encoding virtual tags): virtual tags): 9.12 on page 133 For Release 6, writ Fields 0 6:4 on read. returns zero zero; as Must be written VI 3 instructioncache Virtual K0 2:0 and cacheability Kseg0 MT 9:7 MMU Type: Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 236 MIPS® Architecture Vo For Programmers

Required Required Required ture, Rev. 6.02 Rev. ture, 237 ts per way, the line size, the ts per way, (CP0 Register 16, Select 1) register fields. hardware hardware hardware Config1 R Preset by R Preset by R Preset by Write Reset State Compliance Read/ ed Resource Architec ed Resource 16, Select 1) 16, Select codings for the number of se for the codings having MT register is 9.46 Configuration Register 1 er Field Descriptions er Field Descriptions Table 9.65the describes Config2 register Config Config2 register and encodes additional capabilitiesinformation. All fields in Meaning register; register is not implemented, Config Description Config1 Config2 III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Figure 9.48Figure Format Register Config1 Table 9.65Table Regist Config1 064 1128 2256 3512 45 1024 6 2048 732 4096 ere is no cache implemented. Encoding

Required.

implemented, this bit should read as a 1. read as this bit should implemented, this bit should read as a 0. If the the If 0. a as read should bit this is present. If the If the is present.

a value of ‘none’. a value of through 63 through in this field correspond to 1 to 64 TLB value zero is entries. The implied by 25 24 22 21 19 18 16 15 13 12 10 9 7 6 5 4 3 2 1 0 register is an adjunct to the shows the format of the shows register are read-only. register are 30..25 values 0 one. The minus in the TLB entries Number of Config1 Cache Size = Associativity * Line Size * Sets Per Way Sets * Line Size * = Associativity Size Cache Config1 Fields M 31 a that to indicate is This bit reserved IS 24:22 I=cache sets per way: MMMU Size - 1 - IS IL IA DS DL DAC2MDPCWRCAEPFP Size MMMU 31 30 the The I-Cache and D-Cache configuration parameters include en and the associativity. The total cache size for a cache is therefore: cache size for total The associativity. and the If the line size is zero, th is zero, size the line If Figure 9.48 Compliance Level: The MMU Name Bits Size - 1

9.46 (CP0 Register 1 Register Configuration MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

Required Required Required hardware hardware hardware ged Resource Architecture, Rev. 6.02 R Preset by R Preset by R Preset by Write Reset State Compliance Read/ Meaning Meaning Meaning l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. Description 012-way Direct mapped 23-way 34-way 45-way 56-way 67-way 78-way 064 1128 2256 3512 45 1024 6 2048 732 4096 14 bytes 0 bytes 14 I-Cache No present 28 34 bytes 16 5 bytes 32 6 bytes 64 7 bytes 128 Reserved Encoding Encoding Encoding

Table 9.65Table (Continued) Descriptions Field Register Config1 Fields IL 21:19 I-cache line size: IA 18:16associativity: I-cache DS 15:13 D-cache sets per way: Name Bits 238 MIPS® Architecture Vo For Programmers

Required Required Required ture, Rev. 6.02 Rev. ture, 239 (CP0 Register 16, Select 1) 0 Required hardware hardware hardware R Preset by R Preset by R Preset by R Write Reset State Compliance Read/ ed Resource Architec ed Resource 9.46 Configuration Register 1 Module is implemented. at the processor contains at the contains processor at the processor contains at the contains processor Meaning Meaning Meaning Release Release 5 and cannot be Description III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: 012-way Direct mapped 23-way 34-way 45-way 56-way 67-way 78-way 01coprocessor No 2 implemented Coprocessor 2 implements 14 bytes 0 bytes 14 D-Cache No present 28 34 bytes 16 5 bytes 32 6 bytes 64 7 bytes 128 Reserved Encoding Encoding Encoding

This bit indicates not only th a coprocessor such but that 2, support for Coprocessor is attached.

MIPS64/microMIPS64 processor. Not used on a processor. MIPS64/microMIPS64 processor. MIPS32/microMIPS32 This bit indicates not only th support for MDMX, but that such a processing ele- attached. is ment MDMX is deprecated in implemented when the MSA Table 9.65Table (Continued) Descriptions Field Register Config1 Fields C2 6 2 implemented: Coprocessor DL 12:10 size: line D-cache DA 9:7 associativity: D-cache MD 5 ASE implemented on a to denote MDMX Used Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

Required Required Required Required Required hardware hardware hardware hardware hardware ged Resource Architecture, Rev. 6.02 R Preset by R Preset by R Preset by R Preset by R Preset by Write Reset State Compliance Read/ CP1 FIR at the processor contains at the contains processor Meaning Meaning Meaning Meaning Meaning l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. Description registers registers implemented No performanceNo counter registers implemented Watch registers implemented: 01 implemented watch registers No 01implemented not MIPS16e implemented MIPS16e 01 implemented EJTAG No implemented EJTAG 01 FPU No implemented FPU implemented 0 1 Performance counter registers implemented Encoding Encoding Encoding Encoding Encoding

This bit indicates not only th unit is but that such a support for a floating-point unit, attached. of the FPU capabilities the FPU is implemented, If an bits in the capability from the be read can

Watch register. Table 9.65Table (Continued) Descriptions Field Register Config1 Fields FP 0 FPU implemented: EP 1 implemented: EJTAG PC 4 implemented: registers Counter Performance CA 2 Code compression (MIPS16e) implemented: WR 3 Name Bits 240 MIPS® Architecture Vo For Programmers

0 Optional Required Required 4 3 ture, Rev. 6.02 Rev. ture, 241 register is required; (CP0 Register 16, Select 2) State Compliance Reset register fields. hardware hardware hardware Config3

. 8 7 L2C Config2 R Presetby R Preset by R/W Preset by Write Read / ed Resource Architec ed Resource Config5 12 11 16, Select 2) 16, Select describes the describes is implemented, or if the or is implemented, 9.47 Configuration Register 2 er Field Descriptions er Field Descriptions 4 is dependent on Table 9.66 implemented, this 128 256 512 register is imple- Config3 register is 1024 2048 4096 8192 16 15 Reserved Config2 Config3 iary cache control or status or status control cache iary register; emented it should read as zero Description 20 19 Config2 06 1 2 3 4 5 6 7 8-15 ts per way: III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Figure 9.49Figure Format Register Config2 Config3is not register Encoding Per Way Sets if a level 2 or level 3 cache or level 2 a level if Table 9.66Table Regist Config2 24 23 Required

mented, this bit should read as a 1. should mented, this bit bit should read as a 0. If the the read as a 0. If should bit present. If the bits. If this field is not impl write. ignored on and be register encodes level 2 and level 3 cache configurations. level 3 cache and 2 register encodes level shows the format of the shows otherwise. In Release 6, presence of presence 6, Release In otherwise. Config2 Fields M 31 a that to indicate is This bit reserved The Compliance Level: Optional Figure 9.49 Figure

TS 27:24 cache se Tertiary TU 30:28 tert Implementation-specific Name Bits 31 30 28 27 MTU TS TL TA SU SS SL SA 9.47 (CP0 Register 2 Register Configuration MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

equired Optional Required Required R State Compliance Reset hardware hardware hardware hardware ged Resource Architecture, Rev. 6.02 R Preset by R Preset by R Preset by R/W Preset by Write Read / 6 2 4 128 128 256 Reserved emented it should read as zero l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. Description ts per way: way: per ts 064 1 012 23 34 Mapped Direct 45 56 67 78 23456 256 7 512 1024 2048 4096 8192 014 28 No cachepresent 31 43 56 6 7 8-15 Reserved 8-15 Reserved 8-15 Encoding Per Way Sets Encoding Associativity Encoding Size Line Table 9.66Table (Continued) Descriptions Field Register Config2 bits. If this field is not impl write. ignored on and be Fields SS 11:8se Secondary cache TL 23:20 size: cache line Tertiary TA 19:16cache associativity: Tertiary SU 15:12 or status cache control secondary Implementation-specific Name Bits 242 MIPS® Architecture Vo For Programmers

equired Required R ture, Rev. 6.02 Rev. ture, 243 by (CP0 Register 16, Select 2) State Compliance Reset hardware hardware R Preset by Write Read / ed Resource Architec ed Resource 9.47 Configuration Register 2 6 2 4 128 256 Reserved Description ciativity: R Preset 012 23 34 Mapped Direct 45 56 67 78 014 28 No cachepresent 31 43 56 6 7 8-15 Reserved 8-15 III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Encoding Associativity Encoding Size Line Table 9.66Table (Continued) Descriptions Field Register Config2 Fields SL 7:4 Secondary cache line size: SA 3:0asso cache Secondary Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 244 MIPS® Architecture Vo For Programmers

tiple MT SM TL -Core Required Required Manager. M M implementa- Required for for Required tions that use CD the Coherency the Coherency Coherent Mul- Coherent SP t I n V ture, Rev. 6.02 Rev. ture, 245 I E C V ware ware ware (CP0 Register 16, Select 3) P L A register fields. register I T L T T C C X Config3 register are read-only. S P P D Rhard- by Preset Rhard- by Preset Rhard- by Preset ed Resource Architec ed Resource 2 S P P D Config3 I R X 16, Select 3) 16, Select describes the I L R U otherwise. 9.48 Configuration Register 3 ISA Table 9.67 Table Optional On Exc ISA implemented, this Config4is register o n u C M register; is implemented. implemented Meaning Meaning Config4 register is imple- turns zeros on read. 0 0 Reserved Config3 MMAR III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Description Read/Write Reset State Compliance Figure9-50 Config3 Register Format if any optional feature described by this register is implemented: 2Release of the IPLW to allow software to determine the presence of XPA (>36-bit PA support). (>36-bit PA toXPA allowtothe determine software presence of

PS™ ASE, or trace logic; logic; or trace PS™ ASE, register is not is not Config4 register Z V Table 9.67Table Descriptions Field Config3 Register LPA Required 01 MSA Module not implemented is Module MSA

01 CM GCR space is not implemented implemented is GCR space CM PW S C Encoding Config3 Encoding ration RegisterSpace is implemented. bit shouldbit read as a 0. If the as a 1. read should mented, this bit present. If the If the present. register encodes additional capabilities.fieldsthe in All I shows the of format the B P B Config3 S P A M Release 5 adds Release 5 Compliance Level: the SmartMI Architecture, The

Figure 9-50 C R G CM Fields 0 30 re zero; as be written Must M 31 a that to indicate bit is reserved This MSAP 28 MIPS SIMD Architecture (MSA) Name Bits CMGCR 29 Configu- memory-mapped Global Manager Coherency 313029282726252423222120191817161514131211109876543210 M0 9.48 (CP0 Register 3 Register Configuration MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

Required Required Required Required Required 1 1 ware ware ware ware ware (Release 6) (Release (Release 6) (Release (Pre-Release 6) (Pre-Release 6) ged Resource Architecture, Rev. 6.02 Rhard- by Preset Rhard- by Preset Rhard- by Preset Rhard- by Preset Rhard- by Preset , SegCtl0 his bit indicates indicates bit his are present. T Meaning Meaning Meaning Meaning Module not imple- Module l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. Meaning ented. This bit indicates ented. This bit implemented. This bit indi- ted. This bit indicates indicates bit This ted. Module is implemented. register not implemented register implemented PWSize is always imple- always BadInstrP is Table Walking registers registers Walking Table are present. present. are Description Read/Write Reset State Compliance and is always implemented. register not implemented not register BadInstrP BadInstrP register implemented BadInstr BadInstr mented SegCtl2 BadInstr register implemented. PWField , register implemented. This bit indicates indicates bit This implemented. register and 01 not implemented Walking Table Page is implemented Walking Table Page 1 0 1 0 01 not implemented Control Segment implemented is Control Segment 1 implemented is Module Virtualization 0 Virtualization Table 9.67Table (Continued) Descriptions Field Register Config3 Encoding Encoding Encoding Encoding Encoding whether the Segment Control registers Segment Control whether the whether the faulting prior branch instruction word regis- instruction word branch prior faulting whether the 6: Release is present. ter mented. BadInstr present. is register word instruction faulting whether the 6: Release BadInstrP SegCtl1 cates whetherPage the PWBase whether the Virtualization Virtualization whether the Fields BI 26 SC 25 Segment Control implemen BP 27 VZ 23 Module implem Virtualization PW 24 Walk Page Table HardWare Name Bits 246 MIPS® Architecture Vo For Programmers

Required if Required if Required if implemented implemented implemented implemented MCU ASE is MCU ASE is microMIPS is microMIPS is ture, Rev. 6.02 Rev. ture, 247 ware ware ware (CP0 Register 16, Select 3) Undefined Required if Rhard- by Preset Rhard- by Preset Rhard- by Preset ed Resource Architec ed Resource mented. mented. are imple- RW if both if RW if only micro- mented; Preset instruction sets sets instruction MIPS is imple- MIPS is 9.48 Configuration Register 3 fields: RIPL gnificant bit and second Meaning fields are 6-bits in fields are 8-bits in fields Meaning Meaning Meaning level is denoted by the is denoted by level dth, bits 18 and 16 of 16 and bits 18 dth, is zero, microMIPS32 is not is microMIPS32 is zero, cts all exceptions whose off- exceptions cts all . RIPL RIPL Cause III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Description Read/Write Reset State Compliance and and and

and and itecture revision level. itecture revision . t, respectively, of that field. field. that of respectively, t, t, respectively, of that field. field. that of respectively, t, Config3 IPL width. IPL width. exception vector. exception vector. exception vector. IPL Config atus field is 8-bits in width, bits 17 and 16 of field of field is 8-bits in wi field is St are and second used bit as the most-significant 01 ASE MCU is not implemented. ASE is implemented MCU 01 MIPS32is used on entrance to an entranceis used on microMIPS to an 0 Release3 0 1 are used as the most-si as are used

1-7 Reserved IPL RIPL ISA Others Reserved. Others Reserved. field of Table 9.67Table (Continued) Descriptions Field Register Config3 Encoding Encoding Encoding Encoding most-significant bi toring to an toring to an exception. Affe setsrelative are to EBase If the the If Status most-significant bi the If MIPS32 Architecture revision AR the If Cause implemented and this field is not used. 16 vec- after used Architecture Set the Instruction Reflects Fields MCU 17ASEimplemented. is MCU MIPS® IPLW 22:21 of Width Name Bits MMAR 20:18 microMIPS32 Arch ISAOnExc MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

Required Required Required if implemented microMIPS is 1 1 ware ware ware (Release 6) (Release (Release 6) (Release (Pre-Release 6) (Pre-Release 6) ged Resource Architecture, Rev. 6.02 Rhard- by Preset Rhard- by Preset R Preset by hard-

RIE bits regis- regis- XIE is always is ion Set is imple- ion Set RIE and is implemented. Coprocessor 0 reg- PageGrain PageGrain bits are not imple- bits are imple- UserLocal Meaning Meaning Meaning l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. XIE XIE register is not imple- is not register is implemented register register. Release 6: The 6: The Release register. vailability. UserLocal t A Description Read/Write Reset State Compliance RIE and RIE and

mented within the mented within the ter. ter. ter. UserLocal mented UserLocal mented. are implemented. MIPS32 ISA are implemented. MIPS32 used of reset. when coming out are implemented. microMIPS32 ISA of reset. used when coming out PageGrain register UserLocal register This implemented. Indicates whether the Indicates bits are always implemented 0 The 1 The 0 MIPS32 Instruct Only 0 1 1 microMIPS32 Only 2 ISAs Both MIPS32and microMIPS32 3 ISAs Both MIPS32and microMIPS32 XIE Table 9.67Table (Continued) Descriptions Field Register Config3 Encoding Encoding Encoding exist within the the within exist and implemented. bit indicates whether the the whether indicates bit ister is implemented. Release 6: Fields ISA 15:14Se Instruction Indicates RXI 12 6: Pre-Release ULRI 13 Pre-Release 6: Name Bits 248 MIPS® Architecture Vo For Programmers

Only) Required Required Required Required (Release 2.1 (Release ture, Rev. 6.02 Rev. ture, 249 ware ware ware ware (CP0 Register 16, Select 3) Rhard- by Preset Rhard- by Preset Rhard- by Preset Rhard- by Preset ed Resource Architec ed Resource register register

9.48 Configuration Register 3 register. field.

BadVPN2 is implemented and is and is implemented Config register is not implemented. 2 implemented. This bit 2 implemented. This bit Meaning ContextConfig Meaning Meaning Meaning ented. This bit indicates ented. Config on 2 of the MIPS DSP Module dule is implemented. implemented. is dule III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Description Read/Write Reset State Compliance mechanism implemented. This bit bit This implemented. mechanism ™ ContextConfig the used for ContextConfig is not implemented is implemented registers is implemented and the width 1 0 01implemented not is IFlowTrace MIPS implemented is IFlowTrace MIPS 01 Revision MIPS DSP Module 2 of the Revision MIPS DSP Module 2 of the 01 MIPS DSP implemented Module is not MIPS DSP is Module implemented Table 9.67Table (Continued) Descriptions Field Register Config3 Encoding Encoding Encoding Encoding MIPS® IFlowtrace . depends on the depends contents of the ContextConfig the BadVPN2 field within the of whether the MIPS DSP Mo indicates whether is implemented. the MIPS IFlowTrace indicates whether Revision indicates whether Revision is implemented. Fields ITL 8 DSPP 10implem DSP Module MIPS® Name Bits DSP2P 11Revisi DSP Module MIPS® CTXTC 9 MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

Only) Only) Required Required Required Required Required (Release 2 (Release 2 (Release 5) ware ware ware ged Resource Architecture, Rev. 6.02 Rhard- by Preset Rhard- by Preset Rhard- by Preset e to support to support ted, and th EntryLo1 Meaning Meaning l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. -writeable extensions. -writeable onal COP0 registers with with COP0 registers onal ase 1 of the Architecture, 1 of the Architecture, ase ase 1 of the Architecture, 1 of the Architecture, ase than 36 bits i.e., the XPA 36 the XPA than bits i.e., port is implemen ented. This bit indicates or modified behavior are behavior modified or terrupt controller is imple- terrupt controller is upts are implemented. Description Read/Write Reset State Compliance EntryLo0 and implemented implemented register existsThe following Coprocessor Coprocessor 0 existsThe following register MVH 01 not implemented are interrupts Vector implemented are interrupts Vectored 01 is not mode EIC interrupt for Support is mode EIC interrupt for Support LLAddr, TagLo. LLAddr, Table 9.67Table (Continued) Descriptions Field Register Config3 Encoding Encoding feature of Release 5. of Release feature PA: physical addresses larger addresses physical larger whether vectored interr of For implementations Rele read. on returns zero this bit • opti to other Modifications • PageGrain • Config5 PageGrain fields and associated control are present if this bit is a 1: • to Modifications The following instructions The following instructions required: • to extensions. for access MFHC0 MTHC0, • modification to zero MTC0 For implementations prior to Release 5 of the Architec- 5 the of prior to Release For implementations read. on returns zero bit ture, this For implementations of For implementations Rele read. on returns zero this bit contains processor This bit indicates not only that the such that but controller, an external interrupt for support attached. is controller a mented. Fields LPA 7sup Address Physical Large VInt 5implem interrupts Vectored VEIC 6in an external for Support Name Bits 250 MIPS® Architecture Vo For Programmers

Only) Required Required Required Required Required Required Reserved (Release 2 (Release 6) (Pre-Release 6) (Pre-Release ture, Rev. 6.02 Rev. ture, 251 0 ware ware ware ware ware (CP0 Register 16, Select 3) (Release 6) (Release (Pre-Release 6) Rhard- by Preset Rhard- by Preset Rhard- by Preset Rhard- by Preset R Rhard- by Preset ed Resource Architec ed Resource 9.48 Configuration Register 3 t indicates t indicates t is implemented Meaning ted. This bit ted. indicates Meaning Meaning Meaning Meaning ted. This bi This ted. ase 1 of the Architecture, 1 of the Architecture, ase is implemented, and the is implemented, and the t this bit must be 0. be this bit must III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Description Read/Write Reset State Compliance mented implemented. register exists register 01 Small is not imple- page support suppor page Small 01 is not implemented logic Trace is implemented logic Trace 01not implemented CDMM is CDMM isimplemented 01implemented is not ASE SmartMIPS is implemented ASE SmartMIPS 01implemented is not MT Module MIPS is implemented MT Module MIPS Encoding Table 9.67Table (Continued) Descriptions Field Register Config3 Encoding Encoding Encoding Encoding or data trace is trace data or whether the SmartMIPS ASE is implemented. For Release 6 and after, ReleaseFor 6 and after, whether the MIPS MT Module is implemented. indicates whether the CDMM is implemented. CDMM is implemented. whether the indicates PageGrain of Rele For implementations read. on returns zero this bit Fields SP 4 suppor Small page (1 kB) TL 0 Logic implemented. This bit indicates whether PC Trace SM 1ASE not implemented. SmartMIPS™ SM 1 ASE SmartMIPS™ implemen MT 2implemen MT Module MIPS® Name Bits CDMM 3 bit This implemented. Map Memory Device Common MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 252 MIPS® Architecture Vo For Programmers

and Required ture, Rev. 6.02 Rev. ture, 253 VTLBSizeExt (CP0 Register 16, Select 4) register fields. Config4 FTLBWays FTLBSets FTLBWays FTLBSets FTLBWays FTLBSets State Compliance Reset hardware Config4 FTLB PageSize ed Resource Architec ed Resource R by Preset FTLB FTLB Definition Depends on MMUExtDef Depends on Definition PageSize PageSize Write Read / 16, Select 4) 16, Select describes the describes 9.49 Configuration Register 4 er Field Descriptions er Field Descriptions register is ExtDef Table 9.68 161514131211109876543210 161514131211109876543210 register is imple- register Config5 register; in the VTLB is defined by concatenating VTLB is defined by concatenating in the FTLB = decode(FTLBSets) * decode(FTLBWays). = FTLB decode(FTLBSets) Config5 Config4 Description III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: if any optional feature described by this register is implemented: 2Release of the register is not implemented, this Config5 register is not implemented, this Table 9.68Table Regist Config4 Figure 9.52Figure 6) (Release Format Register Config4 Figure 9.51Figure 6) (Pre-Release Format Register Config4 otherwise. Required If MMUExtDef=3 0 If MMUExtDef=2 000 If MMUExtDef=1If MMUExtDef=0 000000 00000000000000 MMUSizeExt

. Modifying. can be used to allow VTLB size softwareinindex high to reserve the VTLB. slots present. If the bit should read as a 0. If the 0. If a as bit should read mented, this bit should read as a 1. a as read should bit this mented, Optional register encodes additional capabilities. shows the format of the shows MMUSize AE VTLBSizeExt KScrExist Reserved AE VTLBSizeExt KScrExist MMU Config4 Figure 9.52 Figure Config1 Compliance Level: Architecture; The number of page-pair entries within the page-pair entries within number of The The number of page-pair entries accessible page-pair entries accessible number of The

The Fields 109872423 3130292827 109872423 3130292827 MIE MIE M 31a that is reserved to indicate bit This Name Bits 9.49 (CP0 Register 4 Register Configuration MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

=3 =1 or MT =1 or 4 MT Config MMUExtDef Required EHINV (Release 6) (Release Required if Required if Required if (Pre-Release 6) Config Config4 These features must be must features These implemented if Segmenta- tion Control is imple- mented. recom- are features These FTLB/VTLB mended for MMUs. Always Required for implementations with i.e., TLBs; 4. (Release 6) 4. (Release Required for TLBINV, Required for TLBINV, TLBINVF, EntryHi State Compliance Reset hardware hardware hardware ged Resource Architecture, Rev. 6.02 R by Preset R by Preset Write Read /

. EHINV MMUSize = 3, this field is con- = 3, this field is extended to 10 bits. 10 to is extended R by Preset supported. Refer to Refer to Vol- supported. supported. Refer to Refer to Vol- supported. Meaning concatenatedtheto left of Config1 ASID l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. support/configuration. MMUExtDef MT = 1 or 4; otherwise, EHINV EHINV Description ction EntryHI field to indicate the size of the VTLB. the of size the to indicate field

not supported supported by hardware. In Release not TLBINV i.e., is this field reserved; 6, and TLBINVF must be supported in implementations. Release 6 EntryHi ume II for the of full description these instructions. on instructions operate TLBINV* entire MMU. ume II for the of full description these instructions. on one instructions operate TLBINV* TLB entry. EntryHi Config4 MMUSize 11 TLBINVF supported. TLBINV, 00 EntryHi TLBINVF, TLBINV, 0110 Reserved. TLBINVF supported. TLBINV, Table 9.68Table (Continued) Descriptions Field Register Config4 Encoding catenated to the left of the most-significant bit of the of the bit most-significant the of to the left catenated Config1 Release 6: This field is always of the bit most-significant the reserved. If 6: Pre-Release

27:24Config Applicable only if Fields IE 30:29 TLB invalidate instru AE 28 If this bit is set, then Name Bits VTLB- SizeExt 254 MIPS® Architecture Vo For Programmers

Required Reserved (Release 6) (Release (Pre-Release 6) ture, Rev. 6.02 Rev. ture, 255 Registers are are available Registers Required if Kernel Scratch if Required (CP0 Register 16, Select 4) State Compliance Reset hardware hardware hardware ed Resource Architec ed Resource R by Preset R by Preset R Preset by Write Read / -6

9.49 Configuration Register 4 DESAVE KScratch1 Meaning her purposes are not repre- her purposes for Coproecessor0 Register for Coproecessor0 Register 31. Bit 23 represents Select 7. 7. Select represents 23 Bit r kernel-mode software. r kernel-mode in COP0 Register 31. 17 is preset to zero. is preset 17 Description III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: scratch registers are availabletoker- Config4[12:0] - Must be written as - Must Config4[12:0] read. zeros on returns zeros, used as FTLBWays. Config4[7:4] used as FTLBPageSize. Config4[10:8] used as FTLBSets. Config4[3:0] used as FTLBWays. Config4[7:4] used as FTLBPageSize. Config4[12:8] as VTLBSizeExt. used Config4[27:24] [13:0] is to be interpreted. is to be interpreted. Config4[13:0] 0 Reserved. 12 used as MMUSizeExt. Config4[7:0] used as FTLBSets. Config4[3:0] 3 and VTLB FTLB supported. Table 9.68Table (Continued) Descriptions Field Register Config4 Encoding nel-mode software with nel-mode software select a represents bit Each 0, represents Select Bit 16 is imple- register scratch is the If the associated bit set, fo mented and available For Release 6, bits 2-7 are 1 because always must be implemented. must ot for Scratch registers meant imple- is if EJTAG example, For field. in this sented though zero even to preset is mented, Bit 16 register is implemented at Select 0. Select 1 is reserved for for is reserved 1 Select 0. Select at implemented is register not be used as a kernel future debug purposes and should bit so scratch register, Defines how 23:16 Indicates how many 15:14 Release In these 6, bitsreserved. are 15:14 MMU Extension Definition. Fields st Ext Ext Def Def KScr Exi MMU MMU Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

Def=2 (Pre-Release 6) Required if MMUExt- cific State Compliance Reset Preset by by Preset hardware, tation spe- ged Resource Architecture, Rev. 6.02 chosen value is implemen- one page- RW if FTLB FTLB FTLB FTLB Write imple- mented Read / mented. mented. multiple multiple sizes are is imple- R if only page size B B B B B k G G k k 6 5 64 kB 16 kB Reserved implement implement any subset of ted, the register field value l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. ze is implemented by writing implemented by ze is only one pagesize. Software only one updated to the desired encod- Description 14 2 3 42 51 64 7 01 Encoding Size Page UNDEFINED if therevalid areFTLB entries Table 9.68Table (Continued) Descriptions Field Register Config4 Implementations are allowed to thesesizes, even a subset of can detect si if a FTLB page imple- is size the If field. this register into desired size the mented, register field is the is not implemen size If ing. the is not changed. of any valid entries this The FTLB must be flushed before The FTLB software. by changed register field value is behavior is page programmed using a common not all which were size. 10:8 Entries. Array FTLB Indicates the of the Page Size Fields Size FTLB Name Bits Page 256 MIPS® Architecture Vo For Programmers

= 4 MT Config Def=3 (Release 6) (Release (Pre-Release 6) ture, Rev. 6.02 Rev. ture, 257 Required if MMUExt- Required if Required (CP0 Register 16, Select 4) cific State Compliance Reset Preset by by Preset hardware, tation spe- chosen value is implemen- ed Resource Architec ed Resource one page- FTLB FTLB FTLB FTLB Write imple- R/W if R/W if mented Read / mented. mented. multiple multiple sizes are is imple- R if only page size 9.49 Configuration Register 4 size. Software B B B B B B B k M M k k 6 M M 6 4 1 TB 4 TB 1 GB 4 GB 5 64 kB 16 TB 16 TB 64 16 GB 64 GB 16 kB 256 TB 256 GB 256 256 MB implement implement any subset of ted, the register field value only one page only one updated to the desired encod- Description III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: 14 2 3 42 51 86 9 01 64 71 11 10 12 13 14 15 16 17 18 19 Encoding Size Page UNDEFINED if therevalid areFTLB entries Table 9.68Table (Continued) Descriptions Field Register Config4 can detect if an size is FTLB page by writing implemented imple- is size the If field. this register into desired size the mented, register field is the is not implemen size If ing. the is not changed. of any valid entries The FTLB must be flushed this before The FTLB software. by changed register field value is behavior is page programmed using a common not all which were size. Implementations are allowed to thesesizes, even a subset of 12:8 Entries. Array FTLB Indicates the of the Page Size Fields Size FTLB Name Bits Page MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

=2 =4 =4 MT MT ExtDef Config Config MMU Def=2 Def=1 (Release 6) (Release (Release 6) (Release (Pre-Release 6) (Pre-Release 6) (Pre-Release 6) Required if MMUExt- Required if MMUExt- Required if Required if if Required Required if Required if State Compliance Reset hardware hardware hardware ged Resource Architecture, Rev. 6.02 R by Preset R by Preset R by Preset Write Read / l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. field to indicate the size of the field to indicate the size of the = 1 then this field is an extension of extension is an this field = 1 then Description field. field. 02 13 24 35 46 57 68 7-15 Reserved MMUSize-1 01 12 24 38 416 532 664 7128 8256 9512 Encoding Associativity 11 2048 1012131415 1024 4096 8192 16384 32768 MMUExtDef MMUSize-1 Encoding per Way Sets Table 9.68Table (Continued) Descriptions Field Register Config4 Config4 This field is concatenated to the left of the most-signifi- the of left the to concatenated is field This cant bit to the Config1 Array. Array. TLB-1. 7:0 If 7:4 Array. FTLB the of Associativity Set the Indicates 3:0 within the FTLB the Indicates of Sets per number Way Fields ys Sets Wa FTLB FTLB Name Bits MMU- SizeExt 258 MIPS® Architecture Vo For Programmers

ture, Rev. 6.02 Rev. ture, 259 (CP0 Register 16, Select 5) register fields. ). ). Config5 ). ). XNP). L2C UFR UFE LLB ed Resource Architec ed Resource / ). ). ). FRE VP 16, Select 5) 16, Select describes the describes SBRI ). DEC). NestedEPC , MHV 9.50 Configuration Register 5 ). Table 9.69 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XNP 0 DEC L2C UFE FRE VP SBRI MVH LLB MRP UFR 0 NFExists MRP NestedExc ( register; cache configurations) in COP0 ( configurations) cache MAARI ns ns (for example, LBE). Config5 and 0 III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Figure 9.53Figure Format Register Config5 vector control. vector if any optional feature described by this register is implemented: 3Release of the MAAR s additional capabilities: s additional capabilities: otherwise. Required

Optional shows the format of the the shows • Existence of Config2 (L2 and L3 • Existence of COP0 • control Kernel over non-kernelexecution ( of SDBBP • Support for additional LL/SCinstruction handling capabilities ( • 6 LLX/SCX familyofRelease instructions presence of Determine ( •( feature of the Nested Fault Existence • Support for COP0 capabilitiesmulti-threadingtorelated ( • Support for trap and emulatefloating-point capabilityfor ( • Existenceof MTHC0 and MFHC0 instructions ( • Support for software reset-based Endian switching ( • Cache Error exception •legacy compatibility. Control Segmentation • instructio of EVA Existence • Existenceof the User ModeFP Register mode-changing facility( Figure 9.53 Figure Compliance Level: Architecture;

The Config5 register encode M K CV EVA MSAEn 31 30 29 28 27 26 9.50 (CP0 Register 5 Register Configuration MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

) ) 4.1.4 4.1.4 mented. Control. Control. Optional is imple- Required on page 26 on page 26 Segmentation Segmentation Segmentation Segmentation MSA Module (Refer to (Refer to State Compliance Reset hardware hardware ged Resource Architecture, Rev. 6.02 R by Preset R/W 0 Required for R/W 0 Required for Write Read / dis- Cache K23 K23 K23 K23 K23 K23 er Field Descriptions er Field Descriptions value for bits Config Config yet undefined yet undefined con- Config forced to place place to forced Ku , Ku Ku , and registers are and registers are EBase Ku , Meaning Meaning Meaning control. Disables forc- logic t. With the current architec- the current With t. if is Control Segmentation =0. , Config cate that as l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. , Config K0 should always read a 0. should always as read BEV K0 Description Config abled. enabled. Configk0, Config address bits 31..29 bits 31..29 address vector in kseg1. uses address full 31..29. disabled. Executing a MSA instruc- disabled. Executing tion causes a MSA Disabled excep- tion. enabled. Status Config 1 Table 9.69Table Regist Config5 0 1 0vector exception, Cache Error On 1vector exception, Cache Error On 1 instructions MSA 0 instructions MSA Encoding Encoding Encoding Coherency Attribute control control Coherency Attribute implemented. ing use of kseg1 region in the event of a Cache Error exception when figuration registers are figuration presen tural definition, this bit definition, this bit tural Fields 0 26:13 Returns on read.zeros R0 0 Reserved K 30 Enable/disable M 31indi reserved to bit is This CV 29 Vector Exception Error Cache EVA 28 implemented Addressing instructions Enhanced Virtual R Preset by Name Bits MSAEn 27 (MSA) Enable. Architecture SIMD MIPS R/W 0 if Required 260 MIPS® Architecture Vo For Programmers

Required Required Required Required Required (Release 6) (Release 6) (Release 6) ture, Rev. 6.02 Rev. ture, 261 0 Reserved State Compliance (CP0 Register 16, Select 5) Reset hardware hardware hardware R by Preset R by Preset R by Preset R0 Write Read / ed Resource Architec ed Resource . BE 9.50 Configuration Register 5 Config mode supported. mode supported. Big-Endian modes support. This support is support. an mode by setting a bit in bit a setting by mode an bility of legacy LL/SC LL/SC of legacy bility Meaning Meaning Meaning ructions is required for ructions is required for on subsequent reset. For cur- bility of processor. bility of processor. Description III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: software should read Config2 to determine L2/L3 cache configuration. software that register mapped memory can read instead. supported. Any implementation must support Lit- Any implementation tle-endian mode. ported ported 0 can Software Config2 present. read 1 Config2 not present. Replaced by 1 Both Little and 0sup- family instruction LLX/SCX 0 Little-Endian Only 1sup- not family instruction LLX/SCX ended LL/SC family of instructions Not Present. of instructions LL/SC family ended Encoding Encoding Encoding Table 9.69Table (Continued) Descriptions Field Register Config5 Determines endian capa endian Determines If both modes are supported, then the will processor ini- soft- Thereafter, always. mode in little-endian boot tially wareforce can a change in endi state, endian rent a memory-mapped external register. The endian mode The endian mode register. external a memory-mapped change will only take effect instructions. instructions. The LLX/SCX family of inst family of The LLX/SCX atomic Double-Width Release 6 provided by extending the capa Ext Fields 0 12read. on zero Returns L2C 10 Indicates presence of COP0 Config2. DEC 11 Endian Capability Dual XNP 13 Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

(Release 5) (Release 5) State Compliance Reset ged Resource Architecture, Rev. 6.02 R/W 0 Optional R/W 0 Optional Write Read /

=0. =0. FP FP FRE FRE =0. If Statu- . User mode . User FR =0 handling on =0 handling FRE FR using CTC1 and using CTC1 and using CFC1. using is 0 or Config1 is 0

ion FP arithmetic is 0, or Config1 dditional exception FRE =1 when the MSA Module MSA Module =1 when the Meaning Meaning FREP are removed in Release 6. FREP using CTC1 and CFC1 (only) FR causes a Reserved Reserved a causes E always equals 0. E l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. FRE FRE FRE Description onfig5 using MTC0/MFC0. to 1. User mode hardwired can con- FR tions. tions. instructions. - All SWC1/SWXC1/MFC1 instruc- - All SWC1/SWXC1/MFC1 - All LWC1/LWXC1/MTC1 instruc- - All LWC1/LWXC1/MTC1 do not generate do not generate a conditions. exception: Reserved Instruction - All single-precis Instruction exception. Instruction read and CTC1, (only) using Config5 Config5 applies also to kernel use of CFC1/CTC1. use applies also to kernel is reserved if: FIR . is reserved if FIR FRE FRE UFE UFE 1 following instructions The cause a 1 to write Config5 is User allowed 0by Config5 impacted Instructions 0attempt An by user to read/write =0, then effective FR Encoding Encoding Table 9.69Table (Continued) Descriptions Field Register Config5 UFE s A kernelaccess can C Config5 CFC1 instructions. CFC1 instructions. instructions. Release 5 requires that Status ReleaseCOP1 branches by are 5 and 6 not affected Config5 instructions LWXC1/SWXC1 Config5 an FPU with Status ditionally access Config5 Config5 is enabled. Release 6 eliminates the Status can conditionally access Config5 can conditionally Fields FRE 8 Enableemulateto for user mode Status UFE 9Config5 to access user mode Enable for Name Bits 262 MIPS® Architecture Vo For Programmers

XPA Optional (Release 5) (Release 6) (Release 6) Required for for Required ture, Rev. 6.02 Rev. ture, 263 State Compliance (CP0 Register 16, Select 5) Reset hardware hardware R by Preset R by Preset R/W 0 Required Write Read / ed Resource Architec ed Resource 9.50 Configuration Register 5 r pre-Release 6. r pre-Release ode. User (or super- User (or ode. Meaning on. It prevents user (and It prevents user on. Meaning Meaning is bit determines is bit determines if multi- to restrict availability of to restrict Release 6 implementation. is reserved fo tering Debug mode using tering ons are only required for only required ons are Description must must be 0 for Release 6 and after. MT III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: ported. COP0 extensions do exist. not to 32-bit COP0 registers Extensions exist. visor, if supported) if supported) execution of visor, SDBBP will cause a Reserved Instruc- tion exception. defined to Release prior 6 m kernel in cuted only one virtual core/physical core. core/physical only one virtual There are no or ISA extensions COP0 for multi-threading. This includes CP0 Global Number register = 3, sel (reg = 1), instructions changes to EBASE to sup- DVP/EVP, core numbering. port virtual Config3 01 and MFHC0 are not sup- MTHC0 and MFHC0 are supported. MTHC0 01 as executes instruction SDBBP instruction can be exe- SDBBP only 0 multi-threading support. There is No 1 features supported. Multi-threading Encoding Encoding Encoding Table 9.69Table (Continued) Descriptions Field Register Config5 tions are implemented. are tions instructi these Currently Extended Physical (XPA). Addressing supervisor) code from en supervisor) code from The of purpose this field is operati mode to kernel SDBBP SDBBP. The new Release 6 multi-threading features replace the the replace features multi-threading 6 Release new The Module. existing Multi-threading Note that The value of this bit must be the same for all virtual pro- virtual all for same the be must bit of this value The cessors in a physical core. Th threading is supported in a Fields VP 7 bit This Processor. Virtual SBRI 6 Instruction control. Reserved instruction SDBBP MVH 5 High COP0 (MTHC0/MFHC0) instruc- Move To/From Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

Required Reserved Reserved MAAR(I) MAAR(I) LLAddr is (Release 5) (Release 6) if Required (Release 5) Required if Required Optional in Optional (Release 5) (Release 6) Nested Fault implemented implemented implemented implemented feature exists. feature is set. Otherwise Otherwise is set. UFRP 1 0 0 State Compliance Reset FIR Preset by by Preset hardware hardware =1 2 ged Resource Architecture, Rev. 6.02 accessed unmapped. R by Preset R R R R Preset Required if the UFRP Write else 0 else R/W if Read / FIR eld determines the CCA of a segment when

. r using MAAR FR when the region is LLAdd =1. VZ Status present. not present. below shows which fi below

is mandatory. =1 are recommended if =1 are recommended LLB

Config3 Meaning Meaning Meaning MAARI MAARI LLB [0]. Table 9.69 llows recognition of faulting recognition of faulting llows l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. is read-only 1. is read-only is software accessible through accessible through is software LLAddr and and Description LLB Config5 LLbit LLAddr fied. Software Software may program these registers to fetch/ attributes additional to apply to memory/IO access load/store address ranges. MAAR MAAR pre-Release 5 LL/SC compatible. • added. ERETNC instruction •CP0 • •modi- behavior is instruction SC Config5 , are , are present. 1 0 01 No new added. Hardware is support exists: support Additional 01 allowed. not FR instructions User-mode FR instructions allowed. User-mode MAARI Encoding Encoding =1, with/without a TLB, on implementations Encoding Table 9.69Table (Continued) Descriptions Field Register Config5 K and and Virtualization is supported, i.e., supported, is Virtualization CTC1 and CFC1 instructions. instructions. and CFC1 CTC1 Features enabled by 6, In Release The Nested Fault feature a within an exception behavior handler. , Segment CCA determination: K Config5 0 Indicates that the Nested Fault feature exists. is0. is R/W if an FPU is present, and if the User-mode FR changing feature is present, if i.e. present, is feature FR changing User-mode the and if is if an FPU present, R/W is =0 or Config5 UFR UFR K Fields NF LLB 4COP0 in is present (LLB) Bit Load-Linked UFR 2 to access user-mode allows feature This MRP 3Accessibility COP0 MemoryRegisters, Attribute Exists Name Bits Config5 Config5 Config5 1. Note on 2. 264 MIPS® Architecture Vo For Programmers

ture, Rev. 6.02 Rev. ture, 265 (CP0 Register 16, Select 5) =1 C0 C1 C2 C3 C4 C5 K

SegCtl0 SegCtl1 SegCtl1 SegCtl2 SegCtl2 SegCtl0 ed Resource Architec ed Resource 1 1 1 1 =0 Config5 C2 ementations containing a ementations containing K K0 Config SegCtl1 Undefined Undefined Undefined Undefined 9.50 Configuration Register 5 Segment CCA Determination Segment =1 if it is programming any of these segments to =1 if it is programming any of these segments K K plementation containing a TLB. containing plementation =0 Config5 C2 K K0 KU KU K23 K23 ese regions is mapped on impl No TLB With TLB Config Config Config Config Config SegCtl1 Config5 III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Table 9.70Table SegCtl0 1 2 3 4 5 0 Segment TLB. Software must set Config5 TLB. Software be used as unmapped on an im 1. of th state Reset Note: MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 266 MIPS® Architecture Vo For Programmers

ture, Rev. 6.02 Rev. ture, 267 defined by the architecture. defined registers are not needed for the registers are not Config3 ed Resource Architec ed Resource plement CP0 register 16,plement CP0 register Selects 2 through 5 and Config2 tion-dependent use and is not P0 Register 16, Selects 6 and 7) 16, Selects P0 Register . bits for presence detection of Selects 1 to 5. 1 to of Selects presence detection bits for 9.51 ReservedImplementations for Register (CP0 16, 6 and Selects 7) sters. That is, if the sters. That is, III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: 16, Selects 6 and 7, it is not necessary to im Implementation Dependent Implementation

bit in each of these regi these bit in each of M Compliance Level: CP0 register 16, Selects 6 and 7 are reserved for implementareserved Selects 6 and 7 are register 16, CP0 implementation, theyneed not be implemented just to provide bits. the M the use defines of the MThe architecture only only to set the In order to use CP0 register MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.51 (C for Implementations Reserved ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 268 MIPS® Architecture Vo For Programmers

0 LLB . 10 LLB in Release 6. nked instruction. nked instruction. ture, Rev. 6.02 Rev. ture, 269 Config5 Required register fields for register State Compliance Reset register fields. =1. LLAddr LLB LLAddr which is set when an LL instructionan LL set when is is which R Undefined Optional (pre Release 5) Config5 Write Read / ed Resource Architec ed Resource is register are accessed with MTHC0 and with MTHC0 are accessed is register describes the describes the the describes 9.52 Load Linked Address (CP0 Register 17, Select 0) 36 bits, is supported, is extended to support up to a 59-bit in Release 5 if in Release ition.number Theadditional of functionsupported bits is a is required. Table 9.71 stic purposes only, and serves no function duringnormal stic purposes only, Table 9.72 an implementation an implementation PAddr LLAddr Required PAddr The format of this regis- bits or format the address bits or register; register and of physical address read the by the most Li recent Load in Release 5 can be detected by software throughbedetectedsoftware in Release 5 can by e ability to read and clear the LLbit, the clear to read and e ability -order bits greater than bit 31 of th greater than bit 31 of -order bits Description LLAddr LLAddr LLAddr finds convenient. tion-dependent, and III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: is read-only 1, and CP0and is read-only 1, Figure 9-54Figure 5) Release (pre Format Register LLAddr LLB prior to Release 5. OptionalRelease prior to

Figure 9-55Figure after) 5 and (Release Format LLAddr Register recent Load Linked instruction. is ter implementa may implement as many of the any way that it in Table 9.71Table Field Descriptions LLAddr Register Config5 contains relevant bits register shows the of format the shows the of format the LLAddr Fields 31 63 The Figure 9-54

Compliance Level: In Release In Release 6, pre-Release 5 implementations. Figure 9-55 This register is implementation-dependent,diagno is for operation. than size larger a Release5 feature that permits a PA If XPA, of the physical address size. Any high MFHC0 instructions. provides software with th also Release 5 of LLB in executed. The presence PA, as specified in the in as specified MIPS64 LLAddr instructiondefin PA, PAddr 31..0 most This encodes the address read by the field physical Name Bits 9.52 0) 17, Select (CP0 Register Address Load Linked MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

=1 LLB Required Required (Release 5) (Release 6) (Release 5) (Release 6) Config5 State Compliance Reset ged Resource Architecture, Rev. 6.02 R Undefined Optional R/W 0 Required if Write Read / . an implementation an implementation a 32-bit register with The format of this regis- bits or format the address bits or s bits is implementation- re cannot be set. but to be software accessible. accessible. to be software l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. rdware events may clear LLB Description [54] = PA[59]. [54] finds convenient. tion-dependent, and = 1, then up to a 59-bit PA can be sup- = 1, then up to a 59-bit PA = 0), represents up to 36 this field bits of is then equivalent to equivalent then is LLAddr is always 32-byte aligned. LPA LPA [1] is always aligned to PA[5], which implies implies which to PA[5], aligned is always [1] [31] equal to PA[35]. equal to PA[35]. [31] can be cleared by softwa is set when the LL instruction is executed. The SC SC The executed. is LL instruction the when set is PAddr LLAddr Config3 In Release 5 implementations that do not support XPA In Release 5 implementations do not support XPA that (Config3 may implement as many of the may implement as many any way that it in LLAddr that recent Load Linked instruction. is ter implementa PA. LLAddr If ported with are writes bits, address unimplemented the For specific. zero. return and reads ignored The number of addres The number physical LLB and other ha instructions LLB This field allows the LLbit LLbit the allows field This Table 9.72 Table 5 and after) (Release Descriptions Field Register LLAddr Fields LLB 0 LLbit. PAddr 63..1 most This encodes the address read by the field physical Name Bits 270 MIPS® Architecture Vo For Programmers

MAAR must be ini- be must . While a write result. Similarly, Similarly, result. accessibility attri- accessibility ELPA MAARI ture, Rev. 6.02 Rev. ture, 271 MAAR nges but different attribute different but nges feature to allow architectural PageGrain as described above. . register fields. register fields. ster (CP0 Register 17, Select 1) to1, thenthe access should not e that defines the if included. If XPA is supported, if included. If XPA MAAR MAAR MAAR . An access with a cacheable CCA is access . An MAAR MAAR e for any region of the address space, the address e for any region of ed Resource Architec ed Resource . CP0 Register2). 17, Sel MAAR , is accessed with an MTC0 or MFC0. An EHB and subsequent execution of MTC0or MFC0 MRP the MMU yields a cacheable CCA, but a cacheable yields MMU the rdware factors in the speculate attribute of only attribute in the speculate factors rdware Index

ds specified by MAAR describes the de any equivalentde any attribute determined through other determined as described in the pseudo-code below. determinedas describedpseudo-code in the below. speculate as determined by the as determined speculate itecture include the nsions tonsions this specification allow mayflexibility the of ftware. As described, software must set the logical valid Config5 ion of theion CCA and of not allowed to speculate unless the uncacheable CCA=7 unless the uncacheable not allowed to speculate MAAR registers be paired, i.e., one specifiesi.e., registers be paired, an upper bounds of ented with contiguous address ra ( MAAR Index defines whether an instruction fetch or data load can specula- data fetch or instruction defines whether an Table 9.73 a attribute set yields speculate MAAR MAARI pair. It may, however, clear any one logical valid of the pair to inval-cleartothe one logical any pair valid of however, It may, pair. The use of both bits is conditional on MAAR MAAR implementationtospeculation. determineIt is recommended that register; ddressing (XPA), a Release 5 feature, 5 a Release (XPA), ddressing ents software fromthis using method. hysical address boun MAAR

entations of the arch 9.53 Memory Accessibility AttributeRegi may be used to specify an attribut may be used to MAAR Register 17, Select 1) 17, Select Register Register (CP0 ttribute precede the write to the lower half to maintain atomicity, the requiredprecede property the write to the lower half to maintain atomicity, requires that MAAR register number beforethe now defines speculation, along with III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: MAAR ervative outcome. For example, if ervative outcome. For MAAR to 0, then the access should not the access to 0, then (Release 5) MAARI placed between the write to can be detectedsoftware through can be by pair. Once both logicaltoare set valids 1, ha pair. Optional .

MAAR registereven with index. The logical valid is MAAR MAAR functiona valid yieldsit attribute, will overri only shows the of format the register is a read/write register included in Release 5 of the architectur read/write register includeda Release is in register must be extended by additional physical address bits. To maintainatomicity of the write to an extended mustbeextended byadditional physicaladdress bits. To MAAR must be implementedin conjunction with is impacted by Extended Physical A Physical by Extended impacted is

required.VL, twovalid and VH, are bits, MAAR MAAR MAAR MAAR the address range, andthe address the other the lower bound.exte Future not pairing registers to allow fewer registers to be implem instead of implementation-dependent definition of speculation. The Release 5 specification of to the upperhalf of the extendedcould bits prev of MTC0 to zero out extended PA It is recommended that Release 5 It is recommended implem instruction is required to be idate the whole tively access a memory region within the p the region within a memory tively access MAAR MAAR MAAR means, means, if it provides cons a more Compliance Level: the upper If the whether memory (DRAM)or memory-mapped I/O. implementations follow this description to enable portable so to 1 of each register of the pair to enable a of the pair to enable register each to 1 of Operation: The pseudocode below shows a 3-pair Figure 9-56 (UCA) is used. The final speculative attribute is a combinat is a attribute final speculative The (UCA) is used. allowed to speculate. An access with uncacheable CCA is butes of physical address regions. In particular, butesaddressIn particular, of physical regions. that specifies yields a speculate attribute set yields a MMU CCA, but an uncacheable the yields if The address The address range specified by a The presence of tialized with the appropriate speculate. a access Release 5, the CCA of In then types. The MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.53 A Accessibility Memory

region. For [63:32], MAAR MAAR 0, region must be  t load or fetch t load ) initialization to occur at MAAR MAAR region with speculation ELPA [31:0], then MAAR pair. The example assumes XPA The example assumes XPA pair. ) MAAR ged Resource Architecture, Rev. 6.02 MAAR ELPA a speculative DRAM region with the the with region DRAM a speculative MAAR tions that suppor tions that

S to memory and IO address. A load is consid- is load A and IO address. memory to PageGrain regions to overlap a speculative or not PageGrain or VH and MAARmatch dest instsruction to retire. A fetch typically always spec- always to retire. A fetch typically instsruction dest MAAR CCA or not [i] and MAAR VH tion is allowed. This allows the allowed. This allows is tion MAAR is a requirement. out of reset, it first shouldof reset, out initialize // both logical valids must be set to 1 be set must valids both logical // and (MAAR[i+1] and eculative region can be overlayed on eculative V MAAR l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. VL r speculating to IO. For implementa , and speculate [i] and (MAAR  speculate VL MAAR  1 mory prior to its being the ol physical address of the access matches against a of the access physical address MAAR CCA MAAR[i+1] pairs. = MAAR[i+1] V = [i+1][35:12] <= PA_Align)) // lower bound // lower PA_Align)) <= [i+1][35:12] (MAAR V is to control speculation on load or fetch access on load or control speculation to is  1 = MAAR[i] speculate 0 0 // default is not to speculate is not to default  0 // V MAAR MAARmatch  1 MAARmatch speculate speculate  regionenablesspeculation, to physical accesses addressesthis outside MAAR CCA instaces are invalid, then no specula invalid, are instaces MAAR endif [i][35:12] >= PA_Align) && // upper bound // upper && >= PA_Align) if ((MAAR[i][35:12] MAAR overlap is allowed. This allows non-speculative MAAR [i+1] (MAAR endif //Factor in XPA {Extended Physical Addressing} Physical XPA {Extended in //Factor [i] (MAAR if (MAAR[i] , as defined, has the following properties. endfor speculate then occurs, MAAR match or no is valid, if no MAAR // example, with this property, a non-sp a this property, with example, use of justtwo enabled. This access then can speculate. then can access This enabled. MAAR non-speculative, unless the non-speculative, unless speculate endif in MAAR Now factor //  MAARmatch speculate aligned PA is 64KB of 40-bit Example //  PA[39:16] PA_Align 3 pairs // assume i=i+2) (i=0; i<6; for // Modify speculate attribute as per CCA of memory access (Release 5) (Release access memory CCA of per as attribute speculate Modify // speculates UCA CCA and cached 5: Release // “uncached-accelerated(UCA)”)) == or (CCA “cached”) ((CCA == if any pointwithoutof timeexecution risk of the speculative path)loads (bad or fetchesfrom issuing to IO performance. lower being possibly tradeoff the with addresses, speculate speculation, support and initialization of ulates on access to memory, while neve while ulates on access to memory, • assuming XPA is supported and to be enabled. assuming XPA Software must follow the described method for reprogramming the state of a is supported. •If all all MAAR •If For software toenable speculativeregion a Programming Notes: Programming The purpose of ered speculative if it accesses me •If any any •If 272 MIPS® Architecture Vo For Programmers

32 S VL XPA sup- XPA ported; other- wise, Reserved. ture, Rev. 6.02 Rev. ture, 273 0 Required 0 Required if 0 region become non-speculative. ster (CP0 Register 17, Select 1) R MAAR R/W ed Resource Architec ed Resource 12 11 2 1 0 ADDR reg- reg- . Access to the . Access to pair to VH MAAR MAAR MAAR MAAR of any instruction of any instruction or not or struction fetch struction fetch or [31:0]. VH and Meaning VL mory access. Thus, software Thus, software access. mory MAAR MAAR [63:32] is not valid and should should and valid is not [63:32] modify and can [63:32] is valid 9.53 Memory Accessibility AttributeRegi MAAR lculated above) of the Description Read/Write Reset State Compliance gnored, read as 0. one of the register comparison. and ( and ) VL ister pair. ister MAAR not modify behavior fetch or data load. MAAR any in of behavior of the range within falls load that data addressesthe specified by III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Figure 9-56Figure Format MAAR Register MAAR ELPA as needed. as ADDR 0 1 = MAAR V ELPA Table 9.73Table MAAR Register Field Descriptions pair by clearing 56 55 Encoding [63:32] if XPA is enabled. [63:32] if XPA If XPA is supported and enabled, both VL and VH must be is supported and enabled, If XPA is valid: MAAR register a whether determining in factored MAAR PagewGrain If either valid bit (as ca bit (as valid either If ister pair is set to 0, the pair is assumed invalid and does and assumed invalid pair is to 0, the is set ister pair behavior of a me not modify can clear one valid in invalidate the along with other fields in alongfields with other MAAR VL MAAR PageGrain 0 MAAR Fields • Initialize • the Disable •Set •Set • Program O 62:56 are i Reserved. Writes 63 62 31 VH 63 high 32 bits. Valid, VH Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

0 Required ged Resource Architecture, Rev. 6.02 R R/W Undefined Required R/W Undefined Required to spec- to . . MAAR ADDR register must be ADDR pair speculation attri- pair speculation register pair address register pair address register Meaning [31] = PA[35]. allowed to speculatively to speculatively allowed ts. Treat unused PA bits as PA unused Treat ts. MAAR kB-aligned, and thus the kB-aligned, and overlap. The cumulative cumulative The overlap. is equal to PA[16]. the processor before being processor the apping regions is determined apping MAAR be allowed to speculate. lower bound, then any sourced sourced lower bound, then any y a physical address. MAAR MAAR tional 32 bits, accessible by accessible by 32 bits, tional never e upper bound, then any sourced sourced e upper bound, then any l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. can be extended to a max- ADDR can be extended MAAR may ADDR Description Read/Write Reset State Compliance gnored, read as 0. s specif s (CP0 Register 17, Select 2) for the 2) for 17, Select Register (CP0 access address range. address access matches matches matches is range range register. Index

1 that load/store data or fetch Instruction 0 that load/store data or fetch Instruction regions are allowed to [12] = PA[16]. This allows a 32-bit a 32-bit This allows PA[16]. = [12] regions are at least 64 are regions must alway MAAR MAAR Encoding butes. ify 36 bits of PA, where ify 36 bits of PA, is included, then If XPA imum of 59 address bi physical the purpose, this For reserved. to an addi by up extended in Release 5. An MTHC0 and MFHC0, which are defined is limited to a implementation that does not support XPA 32-bit speculative attribute for overl for speculative attribute ANDing individual valid by MAAR If an access is qualified as non-speculative, it must be the the be must it non-speculative, as qualified is access an If in unretired instruction oldest allowed to access memory or memory-mapped regions. method of determining which register is upper or lower in which is upper register method of determining a pair. MAAR least-significant bit of least-significant bit of address address must be greater than or equal to See If the register specifies the If the register specifies th address must be less than or equal to ADDR MAAR Table 9.73Table (Continued) Descriptions Field Register MAAR 1 Speculate. Fields 0 15:2 are i Reserved. Writes S Name Bits ADDR 55:12 Address bounds. 274 MIPS® Architecture Vo For Programmers

regis- MAAR ture, Rev. 6.02 Rev. ture, 275 0 Required ster (CP0 Register 17, Select 1) R/W ed Resource Architec ed Resource Result Result pair to pair is determined pair is by the cumulative individualspeculate register is valid: register MAAR or of any instruc- pair is determinedthe from cumulative individual or not or instruction fetch or MAAR S V MAAR VH Meaning MAAR register pair is set to 0, lid and thus will not modify access. Software may thus MAAR register is not valid and should register is not valid and register is valid and may mod- register pair. 9.53 Memory Accessibility AttributeRegi MAAR MAAR[i+1] MAAR[i+1] Description Read/Write Reset State Compliance comparison. comparison. and ( and VL te attribute for a te MAAR modify the behavi not data load/store. tion fetch or MAAR ify behavior of any the that within falls load/store data of by the range addresses specified MAAR ) III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: MAAR S V ELPA 1 0/1 speculate may access Valid 0011 0 1 0 1 Result is invalid Result is invalid Result is invalid valid is Result = MAAR 0 1 V Table 9.74 Table MAAR Pair Determination for Valid MAAR[i] MAAR[i] Encoding Table 9.75Table Determination for MAAR Pair Speculate where i iseven where i iseven invalidate the If XPA is supported and enabled, both VL and VH must be is supported and enabled, If XPA a whether in determining factored MAAR the of bit valid either If then the pair is inva pair assumed then the the behavior of any memory clear valid bit in one one register of the PageGrain Table 9.73Table (Continued) Descriptions Field Register MAAR shows howa the validfor attribute shows how the specula 0 Low 32 bits. Valid, Fields attributes. Table 9.74 Table 9.75 ter valids. VL Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

ged Resource Architecture, Rev. 6.02 speculate y never Result S 0/1ma access Valid l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. MAAR[i+1] S 0 MAAR[i] where i iseven Table 9.75Table Pair (Continued) for MAAR Determination Speculate 276 MIPS® Architecture Vo For Programmers

registers are INDEX MAAR register fields. ture, Rev. 6.02 Rev. ture, 277 register number that may register number that 65 210 MAAR MAAR Index registers (CP0 Register 17, Select er Index (CP0 Register 17, Select 2) CP0 Register 17, Select 2) 17, Select CP0 Register R/W Undefined Required MAAR . ed Resource Architec ed Resource MRP describes the the describes to theto appropriate value.

register. is used to specify a is used to specify INDEX Config5 INDEX MAAR Table 9.76 is unchanged is MAARI to determine the the determine to register pair. register pair. register MAAR Index INDEX register; Meaning INDEX gister gister range is always con- MAAR MAAR 0

(CP0 Register because 17, Select 1) is supported. This is nored, read as 0.nored, R 0 Required ttribute Register Index ( Register Index ttribute registers included is implementa- registers is greater than 1. than is greater registers Description Read/Write Reset State Compliance register to access. MAAR Index MAAR III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: 9.54 Memory Accessibility Attribute Regist bound of the of bound the of bound MAAR MAAR MTC0 or MFC0 instruction. MTC0 or MFC0 (Release 5) MAAR there is always more than there is always more one Figure 9.57 MAARI Index Register Format MFC0, software must set MFC0, software must 01 This register specifies the address upper This register specifies the lower address is encoded as follows to indicate which register of indicate follows to is encoded as can be detectedby software through

Table 9.76Table Descriptions Field MAARI Register Index Encoding Optional

registers may be implemented - may registers maximum value supported. Other than the all ones, if the if the ones, the all Other than supported. value maximum then supported, is not written value from its previous value. The re and starts tiguous at value 0. The number of The number must be an even numberbut tion-dependent in Release 5. to ones all write may Software specifies the the specifies of bit least-significant The are paired. MAAR registers INDEX the pair is being accessed. The number of The number MAARI is usedinis conjunction with an implementation thatsupports

is always required if MAAR shows the format of the shows Fields Prior to access by MTC0 or by Prior to access The The presence of MAAR Index MAAR Index Compliance Level: 1). Multiple be accessed by software with an Figure 9.57 Figure paired in Release 5, and thus and paired in Release 5, 0 31:6 ig are Writes Reserved. 63 Name Bits INDEX 5:0 MAAR Index MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.54 A Accessibility Memory ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 278 MIPS® Architecture Vo For Programmers

Watch registers are registers IRW bits are zero in the register description description register 3210 ture, Rev. 6.02 Rev. ture, 279 ERL h conditions.For micro- WatchHi register fields. and WatchHi econd half-word overlaps a econd half-word overlaps and State Compliance Reset supported by a particular EXL WatchLo bit in the WatchLo M registers, referencing them via the select them via the select registers, referencing R/W 0 Optional R/W Undefined Required Write 9.55 18) Register (CP0 Register WatchLo Read / ed Resource Architec ed Resource register address matc register address see which ones were actually set. actually were which ones see a watchpoint debugwhich facility initiatesa WatchHi describes the register, and the watch exception is deferred until register, Watch ype of reference (instruction fetch, load, store) to r a match occurs if the s theoccursr a match if and registers may be dedicated to a particular type of refer- may be dedicated registers Cause triggered by a prefetch, CACHE, or SYNCI (Release 2 and 2 (Release or SYNCI triggered by a prefetch, CACHE, determine which enables are Watch Table 9.77 Table WatchLo VAddr ess and are actually issued issued actually and are ess register; writes to writes to it must be ignored, instructions never cause s not overlap with the watched address. bitin is set the ptions are enabled for instruc- register. See the of discussion the register. WP Description WatchLo les bits and reading them back to and reading them bits les Config1 III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Figure9.58 Register Format WatchLo (CP0 Register 18) (CP0 Register ructions, and each pair of ructions, and each pair register only supportsthetypes, a subset of the reference unimplemented enablesmust be registers together provideto interface the registers together Table 9.77Table Register WatchLo Field Descriptions bit of bit the are zero. bits Watch WR Optional.

WatchHi ERL Watch exceptions). Watch If this bit is not implemented, zero. must return and reads tion fetches that match the addr by the (speculative processor this is a doubleword address, since bits [2:0] are used to used since [2:0] are this is a doubleword address, bits match. type of control the register virtual specifies the base address and the t and and shows the format of the EXL register. If either bit is a one, the one, bit is a If either register. WatchLo WatchLo Fields 31 Figure 9.58 It isIt implementation-dependent whetherdata a watch is subsequent releases only)instruction addresswhosethe matches below. The ignoredon write and return zero on read. Software may ence (e.g., instructionor data). Software determine may ofif least one pair at implemented via the implemented via the field of the MTC0/MFC0 field of the MTC0/MFC0 inst register pair by setting all three enab Status Compliance Level: The

both the watch exception if an instruction or data access matches the address specified in the registers. As such, they duplicate As such, specified in the registers. address instruction or data access matches the watch exception if an exceptions are takenonly if the debug solution. Watch some functions of theEJTAG

MIPS implementations, it is implementation-dependent whethe watched address and the first half-word doe An implementation may provide zeroor more pairs of match. If a particularIf match. I 2 If this bit is one, watch exce VAddr 31..3 Note that to match. address the virtual specifies This field Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.55 Register WatchLo

State Compliance Reset ged Resource Architecture, Rev. 6.02 R/W 0 Optional R/W 0 Optional Write Read / eld Descriptions (Continued) eld Descriptions enabled for loads writes to writes to it must be ignored, writes to writes to it must be ignored, ptions are enabled for stores ptions are l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. Description Table 9.77Table Fi Register WatchLo that match the address. the match that If this bit is not implemented, and reads must return zero. must return and reads and reads must return zero. return must and reads that match the address. the match that instruc- load PC-relative the MIPS16e of the purposes For data, a be to considered is reference PC-relative the tions, watch- is, the That reference. instruction an than rather 1. is a only if this bit is triggered point If this bit is not implemented, Fields R 1 If this bit is one, watch exce W 0 If this bit is one, watch exce Name Bits 280 MIPS® Architecture Vo For Programmers

register: an registers are registers bits are zero in the 3 2 1 0 ture, Rev. 6.02 Rev. ture, 281 ERL WatchLo WatchHi clear”, such that such that clear”, software and register fields. and State Compliance Reset register reference with a select with a select register reference tion. The optionalThe tion. mask field EXL n+1’. WatchHi is to write the value is to write the read from the ion matched. When set proces- the set by When matched. ion WatchLo t when the register was read are cleared the register t when WatchHi registers, referencing them via the select them via the select registers, referencing R Preset Required at matches the address will cause the specified matches at Write 9.56 WatchHi Register(CP0 Register 19) ) that denote the condition that caused the caused condition that that denote the ) Read / ed Resource Architec ed Resource W . a watchpoint debugwhich facility initiatesa WatchHi , and register, and the watch exception is deferred until register, describes the describes regis- R , and I registers may be dedicated to a particular type of refer- may be dedicated registers ith a select field of ‘ a select field of ith WatchLo bit is one in the in the is one bit Cause All three bits are “write one to bits are All three M register cause a watch excep a watch cause register WatchLo Watch / Table 9.78 WatchLo lifies the virtual address specified in the lifies the virtual EntryHi 16 15 12 11 WatchHi register; bitin is set the register. If the If register. WP one is implemented) and which condit pair is implemented pair w clear its value. The The clear its value. typical way to do this Description WatchHi Config1 ASID 0 Mask I R W . Indoing so, only those bits whichse were III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: bit is one, any virtual address reference th Figure 9.59Figure Format Register WatchHi G ’ ructions, and each pair of ructions, and each pair WatchLo / bit is a zero, only those virtual address references for which the ASID value in the a zero, onlyASIDis whichaddressin value bit those virtualthe references for registers together provideto interface the registers together n+1 Table 9.78Table Field Descriptions Register WatchHi G WatchHi bitof the are zero. bits WR Optional. WatchHi

EAS WatchHi ERL ters is implemented at an MTC0 or MFC0 select field ‘ value of bits are set by the processor when the corresponding bitsthe are set by the processor when watchregister condition satisfiedindicate and is 0 and W and register contains information that qua shows the format of the the shows (lobal) bit, an optionalbitsaddress ( mask, and three EXL n’, another register back to register matches the ASID value in the the in value ASID the matches register G , and R register. If either bit is a one, the one, bit is a If either register. , a , WatchHi WatchLo I Fields 31 30 29 28 27 26 25 24 23 MGWM provides address maskingprovidesaddress to qualifythe address specified in The watch register to match. If the ence (e.g., instructionor data). Software determine may ofif least one pair at implemented via the field of the MTC0/MFC0 field of the MTC0/MFC0 inst WatchHi ASID WatchHi Status Compliance Level: The when the register when the register is written back. 9.59 Figure both the watch exception if an instruction or data access matches the address specified in the registers. As such, they duplicate As such, specified in the registers. address instruction or data access matches the watch exception if an exceptions are takenonly if the debug solution. Watch some functions of theEJTAG must write a one to the bit in order to to order in the a bit to one write must which watch registerpair (if more than sor, each of these bits remain set until cleared by software. by bits remain set until cleared these each of sor,

The An implementation may provide zeroor more pairs of field of ‘ field of a watch exception. If the If watch exception. a M 31of is one, another pair this bit If Name Bits 9.56 Register 19) (CP0 Register WatchHi MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

2) 2) 2) Required = AE AE If then then

else 0 else State Compliance 1 Reset Undefined Config4 A ged Resource Architecture, Rev. 6.02 then then

0 0 Reserved If R/W Undefined Optional R/W R/W Undefined Required R/W Undefined Required W1C Undefined Required (Release W1C Undefined Required (Release W1C Undefined Required (Release else 0 0 else Write = 1 Read / E Config4

EntryHi field of ASID register. registermust register to cause a cause to register WatchHi WatchHi implemented, any bit in many mask bits are imple- is field and then reading hat matches that specified in t EntryHi cleared by software, cleared by software, which is when a store condition matches matches condition a store when bits the corresponding address the corresponding bits l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. Description required to match that in the required to match that in the field of the lization Module. lization Module. then these bits extend the the extend these bits then

field of the bit is zero in the ASID = 1 returns zero; as = 0 then Must be written G

register will cause a watch exception. If this register will cause a watch exception. AE AE ASID register. If this field is If register. WatchLo Config4 Config4 Table 9.78Table (Continued) Descriptions Field Register WatchHi this register. register. this If zero on read. accomplished by writing a 1 to the bit. register if the When pair. register watch this in values the matches dition set, the bit remains set until WatchLo inhi one a field that is this match. address the in from participating bit be it to must writes is not implemented, field If this and reads must return ignored, zero. Software may determine how th ones the by writing mented back the the result. back the values in thisWhen watch set, theregister bit pair. accom- is which software, by cleared until set remains plished by writing a 1 to the bit. the values in thisWhen watch set, theregister bit pair. accom- is which software, by cleared until set remains plished by writing a 1 to the bit. Must be written as zero; returns zero on read. 0 0 Reserved match the the match the the the is zero, bit watch exception. watch 15..12 Fields I 2 con- fetch an instruction when is This bit set hardware by 0 27..26, R 1 matches condition load a when by hardware is set bit This G 30one, any address If this bit is W 0 This bit is set by hardware WM 29:28 Virtua Reserved for EAS 25:24 If Mask 11..3 the in address the qualifies that mask bit Optional ASID 23..16 ASID value which is Name Bits 282 MIPS® Architecture Vo For Programmers

ture, Rev. 6.02 Rev. ture, 283 l Select values) l Select P0 Register values) 22, all Select ed Resource Architec ed Resource Register 22, al Register ndent use and is not defined by the architecture. defined ndent use and is not . 9.57 Reserved Implementations for (C III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Implementation Dependent Implementation

Compliance Level: CP0 registerCP0 implementation-depe 22 is reserved for MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.57 (CP0 for Implementations Reserved ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 284 MIPS® Architecture Vo For Programmers

ture, Rev. 6.02 Rev. ture, 285 on for the format and description of ed Resource Architec ed Resource 9.58 Debug Register(CP0 Register 23, Select 0) ecification. Refer to that specificati III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Optional.

register is part of the EJTAG sp partregister is of the EJTAG Debug this register. Compliance Level: The MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.58 Select 0) Register 23, (CP0 Debug Register ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 286 MIPS® Architecture Vo For Programmers

ture, Rev. 6.02 Rev. ture, 287 Register 23, Select 6) ed Resource Architec ed Resource 9.59 Debug2 Register (CP0 III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: ter (CP0 Register 23, Select 6) 23, Select Register ter (CP0 Optional.

register is part of the EJTAG specification.to that specification Refer for the format description and of registerof is part the EJTAG Debug2 Compliance Level: The this register. 9.59 Regis Debug2 MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 288 MIPS® Architecture Vo For Programmers

register to deter- to register register requires requires register format and descrip- ture, Rev. 6.02 Rev. ture, 289 DEPC DEPC registers: ISA Mode ocessing resumes after excep- a debug n, when the exception causing instruc- causing n, when the exception 9.60 Register DEPC Register (CP0 24) and ich processing resumes with the value of PC ed Resource Architec ed Resource register is set. set. is register value writtenvalue with no interpretation. Software Cause of the exception, or exception, of the and must be writable. registerwith, ssor resume address and read the DEPC ecution of the DERET instruction. the DERET ecution of bit inthe ster in Processors the That Implement E or the microMIPS32 base architecture, the base or the microMIPS32 E was was the direct cause 0 that contains the address at which pr at address that contains the Branch Delay y preceding branch or jump instructio branch y preceding register are significant ocessing resumes, as described above. register, it combines the address at wh it combines register, ferred there for the there ferred is re reader and the specification e EJTAG register, it distributesto the bits the register, DEPC III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: S32 Base Architecture , the processor writes , processor writes the the DEPC register as the result of ex  ISAMode register to change the proce DEPC register simply returnto a GPR the last 31..1 DEPC DEPC 0 e processor will resume. e processor  0 DEPC Optional.

rpreted by the processor as describedinterpretedabove. by the processor as is value which new register store a 31..1 register: DEPC register register is a read-write  DEPC tion is in a branchtionindelay a is slot, and the PC  DEPC ISAMode DEPC  resumePC DEPC DEPC ISA Mode When a debug exception occurs When The processor reads reads The processor the • virtual the instructionthe address of that • of the immediatel address virtual the writes to the tion serviced. It has been is part of th the All bits of tionof theregister. special handling. When the processor writes the Software may write the Software readsthe of “resumePC” is the address at which pr reads When the processor the In processorsIn that implement MIPS16e AS the Compliance Level: The mine at what address th mine at what address the MIPS16e ASE or microMIP 9.60.1 Handling of Regi the DEPC Special 9.60 24) (CP0 Register DEPC Register MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 290 MIPS® Architecture Vo For Programmers

register, and and register, ter overflows), the ter overflows), Cause ture, Rev. 6.02 Rev. ture, 291 bit is one bit in the Perfor- is es under a specified set of of a specified set under es M the Architecture, this the Architecture, this inter- the performance counter. the performance counter. bit in the describes the Performance ted, each performance counter lease 2 of the Architecture, 2 of lease 5 4 3 2 1 0 PCI is a one (the coun a one (the is register: Even selects access the con- Even selects register: Table 9.80 register. If the register. ed Resource Architec ed Resource PerfCnt nce counter. The counter register increments counter register The nce counter. n+3’. Config1 ontrol Register 0 ontrol ontrol Register 1 ontrol showstwo an examplecounters performance of ounter Register 0 ounter Register 1 ontrols the behavior of behavior the ontrols C C C C n’, another pair of Performance Counter Control and PerfCnt Register Usage lementationsRelease 1 of of e, extending the select field in the obvious way to obtain determineleast if atoneof Performance pair Counter 9.61 Performance Counter Register (CP0 Register 25) hardware interrupt5. InRe values of the bit in the n+2’ and ‘ Table 9.79 register. register. PC EventExt Event IE U S K EXL and a 32-bit counter register. To provide additional capability, additional provide capability, To and32-bit a counter register. rformance counters are implemen rformance TD PerfCnt 16 15 14 11 10 -significant bit of the counter register of the counter bit -significant gister (CP0 Register 25) (CP0 Register gister to even-odd select each performance counter c each performance 0PC renced via a select field of ‘ field of select a renced via . III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Select Value to the interrupt mode of the processor. Counting continuesregister aftercounter a over- theto interrupt processor. the mode of PerfCnt, Select 1 PerfCnt, Select 3 PerfCnt Register s access the counter register. register. the counter s access ined by the control register for the performa EC Recommended

Figure 9.60Figure Format Register Control Counter Performance 0 PerfCnt, Select 0 1 PerfCnt, Select 2 Counter shows the formatControlPerformance Counter of the Register; Performance Table 9.79 Table Register CP0 PerfCnt the of Usage Counter Performance Example pendinginterruptsfrom performance all counters are ORed together to become the and how they mapthe intoth values of e select are prioritized as appropriate as are prioritized flownot whether or an interruptis requestedtaken. or Each performance counter is mapped in performancecounter optionally requests an interrupt. In imp rupt is combineda implementation-dependentin way with once for each enabled event. When the most event. When the once for each enabled Compliance Level: The Control Register associated with 9.60 Figure Counter registers is implemented at the select values of ‘ values of the select implemented at is registers Counter trol register and odd select trol register and Control and Counter is implemented registers via the More or less than two performance counters are also possibl ofthe desired number performance counters. Software may consists of a pair of registers: a 32-bita pair of registers: controlregister of consists multiplemaycounters performance implemented. be events or cycl to count can Performance counters implementation-dependent be configured conditionsdeterm that are The ArchitectureThe supports implementation-dependentperformance countersprovide that capability the to count performance analysis. If pe events or cycles for use in Counter Control Register fields. Control Register Counter mance Counter Control register refe 31 30 29 25 24 23 22 M0 Impl 9.61 Re Counter Performance MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

Optional Required Required implemented. mance Counter PDTrace Perfor- PDTrace Tracing feature is Tracing State Compliance Reset hardware hardware mentation Undefined 0 if not used 0 if not by the imple- the by ged Resource Architecture, Rev. 6.02 R Preset by R Preset by RW 0 Required if RW Undefined Optional R/W Undefined Required Write Read / n+3’. Meaning +2’ and ‘ n+2’ and is implemented at an MTC0 at an MTC0 implemented is include cycles, instructions, ace event is triggered. ace event is triggered. lementation-dependent. Any Any lementation-dependent. t multiple performance coun- performance t multiple on has the 6.00 and higher) more which support than the 64 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. tion-dependent and is speci- not tion-dependent ; returns zero on read on returns zero ; 0 0 Reserved Description be counted by the corresponding corresponding the be counted by lization Module. lization Module. 0 0 Reserved unter Trace Disable. unter Trace EventExt|Event. 01 counter. this for is enabled Tracing is for this counter. disabled Tracing Encoding The PDTrace facility (revisi facility PDTrace The This bit Counter in its output. ability to trace Performance from counter performance the specified is used to disable being traced when performance counter trace is enabled counter tr and a performance Control and Counter registers registers and Counter Control of or MFC0 select field value ‘ encodings possible in the Event field, 6-bit the EventExt In such field. Event to the an extension as acts field instances the event selection is the concatenation of the two fields, i.e., is imp width field actual The as zero and are ignored not implemented read bits that are on write. is list of events implementation- The Register. Counter but typical dependent, events cache instructions, instructions, branch memory reference and TLB misses, etc. Implementations that suppor ters allow ratios of events, e.g., cache miss ratios if cache if cache miss ratios cache e.g., of events, ratios ters allow in events the as selected are references memory and miss two counters on a MIPS32/microMIPS32 processor. processor. on a MIPS32/microMIPS32 fied by the architecture. by the architecture. fied zero; as written be must implementation, used by the If not read. zero on returns Table 9.80Table Descriptions Field Register Control Counter Performance Fields

0 22..16written as zero be Must 0 30 Unused processor. MIPS64/microMIPS64 Reserved for M 31 this bit If is a one, another pair of Performance Counter EC 24..23 Virtua for Reserved Impl 29:25implementa This field is Event 10..5 Selects the event to PCTD 15 Co Performance Name Bits EventExt 14..11 In some implementations 292 MIPS® Architecture Vo For Programmers

ture, Rev. 6.02 Rev. ture, 293 State Compliance Reset R/W Undefined Required R/W Undefined Required R/W Undefined Required R/W 0 Required Write Read / ed Resource Architec ed Resource

the Status 9.61 Performance Counter Register (CP0 Register 25) gister Field Descriptions (Continued) Descriptions Field gister for the conditions bits in the ERL (the most-significant bit (the most-significant nt Supervisor Mode, this nt Supervisor Mode, Meaning Meaning Meaning Meaning , this bit enables event rnel Mode. Unlike the usual Mode. Unlike the rnel for the conditions under er Mode. er Mode. Refer to Section and operating in Supervisor operating e interrupt request when as described in Section as EXL register. register. Description Status Mode Mode Mode III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: 01 Kernel in counting event Disable Enable event counting in Kernel Mode 01 Mode in User counting event Disable Enable event counting in User Mode 01 in Supervisor counting event Disable Enable event counting in Supervisor 01disabled interrupt counter Performance counter interrupt enabled Performance 3.3on page “Supervisor Mode” 21 Encoding Encoding Encoding Encoding definition definition of Kernel Mode 3.2 “Kernel Mode” on page 21 cessors that implement Supervisor to Sec- Mode). Refer cessors implement Supervisor that tion processor is the under which on write bit must be ignored and on read. zero return the counting when only register are zero. which the processor is operating in User Mode. mode. If the does not impleme processor corresponding counter overflows counter overflows corresponding 3.4 “User Mode” on page 22 of the counter counter is one. of the This is bit 31 for wide coun- a 32-bit denoted by the W bit ter or bit 63 of a 64-bit wide counter, register). this in The request. interrupt the enables bit simply this that Note masks interrupt normal the by gated is still interrupt actual in the and enable Table 9.80Table Control Re Counter Performance Fields S 2 those pro- Mode (for counting in Supervisor Enables event K 1 Enables event counting in Ke U 3 Enables event counting in Us IE 4 th Enables Enable. Interrupt Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

Figure 9.61 0 s visible when the IE visible s State Compliance Reset ged Resource Architecture, Rev. 6.02 R/W Undefined Required describes the Performance Counter Coun- Write interrupt state change Read / R/W Undefined Required Write Reset State Compliance Read/ ents once for each enabled event.

. = 1, = 1, Table 9.81 Status Status EXL EXL er Register Field Descriptions Field Descriptions er Register register is gister Field Descriptions (Continued) Descriptions Field gister bit in the bit in the Status ERL EXL Event Count . When the most-signifi- Meaning counters and indicated by counters and indicated by rrupt request is ORed with is rrupt request register is one. is Debug register bit in the in the bit l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. ERL Description = 0 = 0 Description e Event Count Field of the Counter register are written. See sECTION bit in the in the bit Cause register. ERL ERL the Interrupt System” on pagethe Interrupt 82 DM e, the EHB instruction can be used to make 1while counting Enable event 0 event counting while Disable Encoding Figure 9.61Figure Format Register Counter Counter Performance corresponding Control Control Register corresponding performance other from those the in bit PCI the cant bit is one, a pending inte register is one and the register is one and Counting is the Counting never enabled when the register or zero. Table 9.81Table Count Counter Performance 31..0 by the is enabled that event for each once Increments Table 9.80Table Control Re Counter Performance Fields Fields 31 Programming Note: Programming In Release 2 of the Architectur The Counter Register associated with performance counter increm The Counter each shows the format of the Performance Counter Counter Register; ter Register fields. field of the Control register or th 6.1.2.1 “Software Hazards and Event Event Count Name Bits EXL 0 Enables counting when the event Name Bits 294 MIPS® Architecture Vo For Programmers

register is imple- ture, Rev. 6.02 Rev. ture, 295 tionthe formatfor of this ErrCtl in conjunction with specific encodings of of with specific encodings in conjunction ed Resource Architec ed Resource 9.62 ErrCtl Register (CP0 Register 26, Select 0) evious implementationsread and write parity to or od. The exact format of the The exact format of od. fer to the processor specifica to the processor fer ster has pr ster has been used in III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: r implementation-dependentmeth Optional.

register provides an implementation-dependent diagnostic interface with the error detection mechanisms the error detection interface with implementation-dependent diagnostic an register provides ErrCtl implemented by the processor. This regi This by the processor. implemented ECC information to and from the primary or secondary cache data arrays cache data secondary or the primary information to and from ECC othe or the Cache instruction Compliance Level: The mentation-dependent and not specified by the architecture. Re fields. the a description of register and MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.62 Select 0) 26, (CP0 Register ErrCtl Register ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 296 MIPS® Architecture Vo For Programmers

ture, Rev. 6.02 Rev. ture, 297 at may be implemented by a pro- by a may be implemented at ed Resource Architec ed Resource 9.63 CacheErr Register (CP0 Register 27, Select 0) dependent and not Referspecified to by the architecture. the cache error detection logic th error detection the cache III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: register is implementation- e format of thisregister and a descriptionof the fields. CacheErr Optional.

register provides an interface with an register provides CacheErr cessor. the The exact format of the processor specification for th the processor specification Compliance Level: The 9.63 27, Select 0) Register Register (CP0 CacheErr MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 298 MIPS® Architecture Vo For Programmers

field is PTagLo ture, Rev. 6.02 Rev. ture, 299 occupy the even select val- even select the occupy interface to all caches, or a or to all caches, interface registers as the source or sink source the as registers must accept a write of zero to must accept a write of zero all implementations. software ndefined Optional e tags at powerup. e cache tag array. The Index Store Index Store The cache tag array. e TagHi ndex Store Tag operation to cache Tag ndex Store . Refer to the processor core specifi- core processor . Refer to the PState L Impl 0 P d select 2 addressing the data cache. 876 5 4 3 2 10 and R/W Undefined Optional R/W Undefined Optional R/W Undefined Optional Write Reset State Compliance Read/ ed Resource Architec ed Resource TagLo otherwise. 9.64 TagLo RegisterSelect (CP0 Register0, 28, 2) initializing the cach initializing the register that acts as the that acts register e register fields. However, in However, e register fields. registers are registers implemented, they Optional TagLo MIPS64 definition.MIPS64The number of additionalsupported bits not for each cache, processors s that act as the interface to th as act that s registers, and then use the I the use and then registers, TagLo up.If there is support for XPA (PA > 36 bits), the > 36 bits), (PA there is supportup.If for XPA TagHi scription for the detailed the scription for ion for the detailed defini- ion for the detailed defini- ss bits of the cache tag. Refer ss bits address size. XPA is a Release 5 feature. Release5 feature. is a size. XPA address and r implementations. U registers is implementation-dependent gister 28, Select 0, 2) 28, Select 0, gister Description lect 0 addressing the instruction cache an the instruction lect 0 addressing a physical address of up to 36 bits. TagLo PTagLo TagHi III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: and if a cache is implemented; implemented; is a cache if as part of the software process of software process the part of as Figure 9-62Figure Format Register TagLo Example registers are implemented or registers are implemented TagLo TagLo registers are read/write registers are read/write register Required

TagLo definition. With a page size of 4 kBs, the field as With definition. shown can contain to the processor-specific de processor-specific the to tion. processor-specific descript processor-specific tion. processor-specific descript processor-specific Table 9.82 Table Descriptions Field Register TagLo Example register for each cache. If for each cache. multiple register TagHi and TagLo TagLo Fields 0 2:1 on read. returns zero zero; as Must be written 0 0 Reserved L 5 to the Refer tag. bit for the cache the lock Specifies initialize the cache tags to valida state at power- Tag and Index Load Tag operations of the CACHE instruction and use the Index Load Tag Tag of tag information, respectively. The exact format of the dedicated select 0 and select 2 of Compliance Level: The ues for this register encoding, with se this register ues for Whether individual cation for the format of this register and a descriptionandthecation of th format a ofregister for this must beablemust into to write zeros the It isIt implementation-dependent whetherisa single there is a function of the implementedfunction of physicalis a extended to support up to a 59-bit PA, as specified in the extended to supportPA, 59-bit up to a 31 Impl 4:3 fo reserved field is This PState 7:6 Specifies the state bits for the cache tag. Refer to the Name Bits PTagLo 31..8 upper addre Specifies the MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.64Re (CP0 Register TagLo

ged Resource Architecture, Rev. 6.02 R/W Undefined Optional Write Reset State Compliance Read/ ion for the detailed defini- l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. Description -specific descript -specific tion. processor Table 9.82Table (Continued) Field Descriptions Register TagLo Example Fields P 0 the to Refer tag. cache the for bit parity the Specifies Name Bits 300 MIPS® Architecture Vo For Programmers

ture, Rev. 6.02 Rev. ture, 301 the corresponding data val- they occupy the odd select and select 3 addressing the data cache. and select ed Resource Architec ed Resource ace to the cache data array and are intended for register that acts as the interface to all caches, or a caches, or to all as the interface register that acts 9.65 DataLo RegisterSelect Register (CP0 1, 3) 28, registers are implemented, registers are implemented, the CACHE instruction reads instruction reads the CACHE registers is implementation-dependent. Refer to the proces-

DataLo DataLo DataHi and gister a description and of the fields. DataLo select 1 addressing the instruction cache the instruction select 1 addressing III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: registers. DataHi registers are registers that act as the interf act as that registers are registers Optional.

d operation of the and register for each cache. If multiple DataHi DataLo and DataLo DataLo values with encoding, values this register for diagnostic operation only. The Index Load Tag operation of The Index Load Tag diagnostic operation only. ues into theues into Compliance Level: The sor specification for the formatthis of re isIt implementation-dependent whetherisa single there The exact format an dedicated MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.65 1, 3) 28, Select (CP0 Register Register DataLo ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 302 MIPS® Architecture Vo For Programmers

t a write of zero to ture, Rev. 6.02 Rev. ture, 303 occupy the even val- select registers as the source or sink source the as registers interface to all caches, or a e cache tag array. The Index Store Index Store The cache tag array. e TagHi . Refer to the processor specification processor . Refer to the d select 2 addressing the data cache. and ware must be able to write zeros into the to write zeros into able be ware must e, processors must accep processors e, ed Resource Architec ed Resource TagLo e tags to a valid state to cache tags initialize the ation to otherwise. 9.66 TagHi RegisterSelect Register (CP0 0, 2) 29, initializing the cache tags at powerup. register that acts as the acts register that are implemented, registers they Optional TagHi s that act as the interface to th as act that s TagHi registers is implementation-dependent

lect 0 addressing the instruction cache an the instruction lect 0 addressing TagHi III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: and if a cache is implemented; implemented; is a cache if as part of the software process of process software part of the as and a description of the fields. However, soft However, fields. the of description a and registers are implemented or not for each cach or not registers are implemented TagLo TagHi registers are read/write registers are read/write register Required

TagHi registers and the use the Index Store Tag oper cache Tag registers and Store the use the Index

register for cache. If multiple each TagHi

TagHi and TagHi and

TagLo dedicated select 0 and select 2 of Tag and Index Load Tag operations of the CACHE instruction and use the Index Load Tag Tag of tag information, respectively. The exact format of the TagLo Compliance Level: The It isIt implementation-dependent whetherisa single there at powerup. for format the register of this ues for this register encoding, with se this register ues for Whether individual 9.66 0, 2) 29, Select (CP0 Register Register TagHi MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 304 MIPS® Architecture Vo For Programmers

ture, Rev. 6.02 Rev. ture, 305 the corresponding data val- ed Resource Architec ed Resource ace to the cache data array and are intended for 9.67 Register DataHi Select Register (CP0 1, 3) 29, the CACHE instruction reads instruction reads the CACHE registers is implementation-dependent. Refer to the proces- DataHi and gister a description and of the fields. DataLo Register 29, Select 1, 3) 29, Select Register III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: registers. DataHi registers are registers that act as the interf act as that registers are registers Optional.

d operation of the and DataHi DataLo and DataLo diagnostic operation only. The Index Load Tag operation of The Index Load Tag diagnostic operation only. ues into theues into Compliance Level: The sor specification for the formatthis of re The exact format an MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.67 Register (CP0 DataHi ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 306 MIPS® Architecture Vo For Programmers

0 register to register requires register. All bits of register. ErrorEPC ture, Rev. 6.02 Rev. ture, 307 register fields. State Compliance Reset ErrorEPC ErrorEPC y referred to as error exceptions). referred to as error exceptions). y ErrorEPC when the error causing instruction is when the error causing essors That Implement the Write which processing resumes with the value value the with resumes processing which Read / ed Resource Architec ed Resource 9.68 ErrorEPC(CP0 Register 30, Select 0) se architecture, the se register with: describes the the describes of the exception, or exception, of the register, at which processing resumes after a Reset, after at which processing resumes register, ssor resume address and read the and address ssor resume EPC ErrorEPC Table 9.83 ErrorEPC 0 register; was was the direct cause ASE or microMIPS32 ba or microMIPS32 ASE ) or Cache Error exceptions (collectivel ) register, it combines the address at it combines the address register, Description am Counter R/W Undefined Required ErrorEPC Register in Proc ocessing resumes, as described above. register, similar to the the to similar register, ErrorEPC and must be writable. and must be  ISAMode register as theexecution result instruction. of ERET of the register to change the proce to register III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: S32 Base Architecture Figure Figure 9.63 Format Register ErrorEPC ErrorEPC 31..1 rs, the processor writes the rs, the processor writes the processor will resume the processor Table 9.83Table Field Descriptions Register ErrorEPC ErrorEPC ErrorEPC register: register, thereno is correspondingbranch delay slot indication register, for the register is a read-write register are significant register shows the format of the the shows EPC ISA Mode ErrorEPC  resumePC ErrorEPC ErrorEPC in a branch slot. delay ErrorEPC Fields of the the When an error exception When an error exception occu Soft Reset, Nonmaskable Interrupt (NMI Unlike the “resumePC” is the address at which pr In processorsIn that implement the MIPS16e Compliance Level: Required. Compliance The • virtual the instructionthe address of that • preceding branch or jump instruction of the immediately virtual address the The processor reads reads The processor the special handling. When the processor writes the Figure 9.63 Figure determine at what address

Software may write the 31 Name Bits ErrorEPC 31..0 Progr Error Exception 9.68.1 Handling of the Special MIPS16e ASE or microMIP 9.68 ErrorEPC (CP0 Select 0) Register 30, MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

registers: ISAMode ged Resource Architecture, Rev. 6.02 and PC reted by the processor as described above. as processor the by reted tes the bits to thetes the bits to l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. register, it distribu register, register simply return to a GPR the last value written with no interpretation. Software ErrorEPC 0  0

registerwhicha new valueis interp store 31..1 ErrorEPC ErrorEPC  ErrorEPC ISAMode  ErrorEPC ISAMode PC writes to the Softwarethe reads of When the processor reads reads processor the When the 308 MIPS® Architecture Vo For Programmers

ture, Rev. 6.02 Rev. ture, 309 n for the format and description of software can use those registers. those registers. can use software 9.69 Register DESAVE Register (CP0 31) ed Resource Architec ed Resource Mode. If kernel mode software uses this register, it it register, this uses software mode kernel If Mode. reason, it is strongly recommended that kernel mode registers are implemented, are implemented, kernel registers ecification. Refer to that specificatio ecification. Refer to KScratch* III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: registers are mandatory.) are registers Optional.

KScratch* registerto is meant be used solely whileDebug in register is part of the EJTAG sp EJTAG register is part of the DESAVE DESAVE (For Release 6, the Release (For this register. The Compliance Level: The would conflict with debugging kernel mode software. For that If the softwarethis not register. use MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.69 31) (CP0 Register Register DESAVE ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 310 MIPS® Architecture Vo For Programmers

0 register. If register. Required (Release 6) (Pre-Release 6) ture, Rev. 6.02 Rev. ture, 311 DESAVE State Compliance Reset register. register. Undefined Optional

kernelsoftware. mode These reg- Config4 R/W Write Read / ed Resource Architec ed Resource register. Select 1 is being reserved for future debug register. field within the the within field Register Format KScratch n 9.70 KScratchn Registers (CP0 Register 7) 2 to 31, Selects populated with a kernel scratch register. populated with a kernel scratchregister. Data KScrExist RegisterField Descriptions available for scratch pad storage by storage pad for scratch available n Register 31, Selects 2 to 7) 31, Selects Register register. register. Description Optional, KScratch1 and KScratch2 at selects 2, 3 are recommended. recommended. Optional, KScratch1KScratch2 and selects at 2, 3 are III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: KScratch Required. Figure 9.64Figure KScratch Table 9.84Table KScratch Release 6 - Registers (CP0 Registers registers are read/write registers are read/write registers registers n field specifies which of the selects are selects which of the specifies field KScrExist KScratchn KScratchn Fields EJTAG is implemented, select 0 should not be used for a EJTAG use and shouldbe used for a not

The Compliance Level: Pre-Release 6 - Compliance Level: Pre-Release Debug Mode software should not use these registers, instead debug software should use the isters are 32bits32-bitwidth infor isters are processors and 64bits forprocessors. 64-bit The existence is indicated by of these registers the The 31 Data 31:0 software. data saved by kernel Scratch pad Name Bits MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For 9.70 KScratch ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 312 MIPS® Architecture Vo For Programmers

bit is zero in the the in zero is bit ture, Rev. 6.02 Rev. ture, 313 ERL in an address error = 1 ERL through 0x0000 0000 0x0000 FFFF 0x7FFF bit is one in the Status register. inisone bit the Status er Mode still results ERL ed Resource Architec ed Resource through through te that address error checkingaddress error is stillte that done before 0x0000 0000 0x0000 FFFF 0x1FFF 0000 0x0000 0x0x1FFF FFFF 0x0x1FFF = 0 Status l mannerl MMU: to the TLB-based both they to map the ERL Generates PhysicalAddress through 32/microMIPS32supports Architecture a lightweight mem- Status 0x4000 0000 0x4000 FFFF 0xBFFF mapped using an identity mapping. ing an identitymapping when the through through through III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: 0x0000 0000 0x0000 FFFF 0x7FFF 0000 0x8000 FFFF 0x9FFF 0xA000 0000 0xA000 FFFF 0xBFFF useg Table A.1Table Addresses Virtual from Generation Address Physical suseg kuseg kseg0 kseg1 Segment Name Address Virtual lists all mappings from virtual to physicalNo addresses. Status register, and are mapped us register, Status low 512MB of physical memory. • Useg/Suseg/Kuseg addresses are mapped byadding 1GBvirtual to the address whenthe Address translation using the Fixed Mapping MMU is done as follows: done MMU is Mapping Fixed the using translation Address • in an identica translated are addresses Kseg1 and Kseg0 As an alternative to the full TLB-based MMU, the MIPS to alternative As an The main body of this specification describes the TLB-based MMU organization. Thismain appendixbodyThe TLB-based MMU organization. of this specificationother the describes describes potential MMU organizations. ory managementmechanism with fixed virtual-to-physicaltranslation, address memory and no protectionbeyond iswhat providedaddress by the error of checks required all MMUs. may This be useful for those applications which do not requirecapabilities the of a full TLB-based MMU. • addresses are Sseg/Ksseg/Kseg2/Kseg3 Supervisor Mode is not supported witha Fixed Mapping MMU. Table A.1 Usthe translation process. Therefore, an attempt kseg0 fromreference to MMU. TLB-based exception, just as it does with a A.1.1 Fixed Address Translation MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For A.1 Fixed Mapping MMU Alternative MMU Organizations MMU Alternative Appendix A Appendix

shows the memory 0xBFFF FFFF are 0xBFFF = 1 Figure A.2 ERL ged Resource Architecture, Rev. 6.02 are inaccessible inaccessible 0x3FFF FFFF are through register is zero; through through 0x8000 0000 through 0x8000 0xC000 0000 0xC000 FFFF 0xDFFF 0xE000 0000 0xE000 FFFF 0xFFFF = 0 Status Status ERL Generates PhysicalAddress 0x2000 0000 bit in the Status ERL register. Status l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. register, and physical addresses register, through through 0xC000 0000 0xC000 FFFF 0xDFFF 0xE000 0000 0xE000 FFFF 0xFFFF Status s that physical addresses addresses that physical s bit is on bit in the is bit is one. ERL ERL sseg ksseg kseg2 kseg3 bit is off in the in bit is off shows the memory mapping when the Segment NameSegment Address Virtual ERL Table A.1 Table (Continued) Addresses Virtual from Generation Address Physical inaccessible when the Figure A.1 Note that this mapping mean mapping this that Note mapping when the when the 314 MIPS® Architecture Vo For Programmers Alternative MMU Organizations Alternative

. For register fields. Config ture, Rev. 6.02 Rev. ture, 317 reuses much of the hard- UNDEFINED cause a Reserved Instruc- a Reserved cause anism. This mechanism has eg1 are always uncached. always are eg1 registers registers are no longer required A.2 Block Address Translation s are necessary to the CP0 register necessary are s EntryHi describes the describes new R/W Undefined Required R/W Undefined Required Write Reset State Compliance manner as for a TLB-based MMU: the the MMU: a TLB-based for manner as Read/ ed Resource Architec ed Resource , and to these to these registers are Table A.2 Wired , and references to ks to , and references , cation for instruction referencesdatareferences. and cation for instructioncation for references and data references, Config virtual addresses. It contains pairs of instruction/data rtual page number, a base page frame number (whose rtual page number, rtual address translation mech rtual translation (BAT) mechanism that translation (BAT) register; Field Descriptions Field Descriptions locationkseg2and of kseg3 virtual address regions. PageMask , ncy attribute. See BE AT AR MT 0 VI K0 Config s of a read or write of a s field of K0 16 15 14 13 12 10 9 7 6 4 3 2 0 Context , gisters were Reserved for Architecture. Reserved were if the registers reads return 0 as ignored, e for the Table 9.12 on page 133 for for the encoding of this field. this of encoding the for slation mechanism, the following change Description nd in the kseg1 are provided same nd coherency attribute nd coherency when 0 EntryLo1 e of the TLB-Based interface, both in hardware and software. and both in hardware of the TLB-Based interface, e , cheability and cohere cheability and III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: Figure A.3Figure Additions Register Config the additionsthe to 0 Register Interface is zero. See See is zero. Table A.2Table Register Config ERL EntryLo0 , Status Table 9.12 on page 133 encoding of this field. encoding Random , shows the format of Index Release 6, writes to these registers ar registers Release 6, writes to these tion Exception. and may be removed. Pre-Release 6, the effect Pre-Release 6, removed. and may be Fields Figure A.3

interface: • The provideentries which the base-and-bounds checking and relo Each entry contains a page-aligned bounds vi respectively. The BAT is an indexed structure which is used to translate indexed structure is an BAT The This section describes the architecture for a block the architecture address This section describes Relative to the TLB-based address tran address TLB-based Relative to the cacheability attribute for kseg0 comes from the The cacheability attributes for kseg0 a attributes cacheability The • and TLBRinstructionsno longerare required and must The TLBWR, TLBWI, TLBP, ware and software interface that exists for a TLB-Based vi for exists software interface that and ware the following features: •much as possibl as preserves It •provides It independent base-and-bounds checking and relo •provides It optionalsupport for base-and-bounds re KU 27:25 a cacheability Kuseg M K23 KU 31 30 28 27 25 24 K23 30:28 Kseg2/Kseg3 ca Name Bits A.2.1 Organization BAT A.1.3 to the CP Changes MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For A.2 Block Translation Address

V D . Figure A.4 C Table A.3 lid bit is off in the entry, a inlid the bit entry, is off can as follows: be described the selected entry, shifted to align selectedthe entry, ged Resource Architecture, Rev. 6.02 te to the reference type and address and type the reference te to t implemented, it is implementation- y (D) bit, and a valid (V) bit. (V) and a valid y (D) bit, (or kseg2 and kseg3) ed bounds address, or if the va sical address. The BAT process address. The BAT sical ional andional may be implemented addressas necessary to the ated. One alternative is to combine the mapping for kseg2 and ated. One alternative is to combine the mapping ftware may determine how many BAT entries are implementedare entries ftwaredetermine may howBAT many register. Type Region Address Reference Reference 12 itiated. Otherwise, base PFN from the Config1 BasePFN l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. If entries for kseg2 and kseg3 are no are kseg3 and If entries for kseg2 quested, the BAT entry that is appropria entry quested,BAT the a cache coherence field (C), a dirt field (C), a a cache coherence || 1 || BoundsVPN Table A.3Table Entry Assignments BAT ) Figure A.4Figure Entry of a BAT Contents 01Data 23Data Instruction45Data Instruction useg/kuseg Instruction kseg2 kseg3 12 Entry Index BoundsVPN BoundsVPN ement of a BAT entry. ement of a BAT BasePFN C D V BAT[i] BAT[i] BAT[i] SelectIndex (reftype, va) (reftype, SelectIndex InitiateTLBInvalidException(reftype) InitiateTLBModifiedException() va + (pfn || 0  va + (pfn bounds  BAT[i] bounds c  d  v  then = 0) (v or (va > bounds) if endif then = store) and (reftype (d = 0) if endif pa i   BAT[i] pfn with bit 12, is added to the virtual address to form the phy is added to the virtual address to formbitwith 12, region is read. If the virtual address is greater than the select in off is and the D bit a store TLB Invalidthereference is exception appropriate referenceinitiated. typethe of is If in exception is TLB Modified a the entry, When a virtual address translation is re address translation is a virtual When kseg3 into a singleinstruction/datapair of entries. So by lookingoffield the at the MMU Size dependent how, if at all, these address regions are transl if at all, these address dependent how, width is implementation-dependent), width is implementation-dependent), The BAT is indexedtyperegion reference by the as shown and the address to be checked in BAT The shows the logicalarrang required.2, 3, 4 andare and0 Entries 5 are opt 1 Entries needs of the particular implementation. A.2.2 Translation Address 318 MIPS® Architecture Vo For Programmers Alternative MMU Organizations Alternative

UNDE- ture, Rev. 6.02 Rev. ture, 319 WI and TLBR instructions. WI and e registers are ignored, reads are ignored, reads e registers well as allows for a TLB that can that for a TLB allows well as sses. In small and low-cost systems, and low-cost systems, In small sses. s are necessary to the CP0 register to necessary are s ly, such fully-associative structures can fully-associative such ly, ed Resource Architec ed Resource emented is not large. emented is not large. registers are eliminated. Pre-Release 6 the effects of a 6 the effects Pre-Release registers are eliminated. read or written by the TLB read or written by the a minimum. a This section an optional describes alternative A.3 TLBs Fixed-Page-Size and Variable-Page-Size Dual clearing the valid bit in the BAT entry. Settingthe bounds entry. clearing the validin bit the BAT to implement and can dissipate a lot of power. The number The number a lot of power. dissipate can and to implement Wired ssary. The TLBWI and TLBR instructions reference the BAT TLBWI The reference the BAT and TLBRinstructions ssary. , and register. The effects of executing a TLBP or TLBWR are The effects register. FTLB use a shared, common page size. size. a shared, common page use FTLB can be practically impl Index implementation costs of implementation costs a small TLB as ble to minimizeble tothe frequencymi of TLB slation mechanism, the slation mechanism, following change . For Release . For Release 6, UNDEFINED writes to thes and Fixed-Page-Size TLBs PageMask so implementation specific. so implementation , t a fully associativea fully t Joint TLB. Unfortunate III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: tion uses twotion TLB structures. uses were Reserved for Architecture. were Reserved Context , CP0 Register Interface CP0 Register EntryLo1 register is the interface to the BasePFN and C, D, and V fields of the BAT entry. The register has has The register entry. BAT D,of the and V fields and C, the BasePFN to is the interface register , register is the interface to the BoundsVPN field in the BAT entry. entry. register is the interface to the BoundsVPN field in the BAT register is used to index the BAT entry tobe register is used to index the BAT , but processors, should signalInstructiona Reserved Exception. EntryLo0 Random Index EntryHi read or write to these registers are or write to read •isnot The FTLB fully-associative, but rather set associative. • Theways numberperimplementation of set is specific. • Thesets number is implementation of specific. • The commonpagesize is al • the within entries all time, one any At the same format as for a TLB-based MMU. for a TLB-based the same format as FINED entry whose index is containedthe in return 0 as if the registers • The • The 1.Fixed-Page-Sizethe This first TLB is calledor the FTLB. TLB This alternative MMUThis alternative configura be slow, can require a large amountlogic components of can require a large be slow, of entries for fully a array that associative Most MIPS CPU cores implemen CPU cores Most MIPS Relative to the TLB-based address tran address TLB-based Relative to the interface: • The Inhighperformance systems, it is desira Making out-of-bounds all addresses onlycanby be done value tovalue first zero leaves the virtual page mapped. • The •and TLBWRinstructions are unnece The TLBP map number a very large of pages to be reasonably implemented. it is desirable to keep the implementation costs of a TLB to a TLB of the implementation costs keep it is desirable to MMU configuration which decreases the A.3.1 Organization MMU A.2.3Changes to the A.3 Dual Variable-Page-Size MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

. bits of the specified virtual the specified bits of ing systems, on-demand pag- systems, on-demand ing and a FTLB with a larger FTLB with a larger and a e FTLB. are Implementations eam and the data stream. For data stream. the eam and register. The size of the VTLB register. ged Resource Architecture, Rev. 6.02 Config4 array size. The methodThe of choosing array size. - in FTLB page that case, the is fixed size by hard- configuration by software can only be done after a after done be only can software by configuration nd fixed-sized pages as wellsmall as for number a of the FTLB. In most operat In most the FTLB. use a page size that is dif- is a page size that use VTLB entry can That is, one ies is not guaranteed to work where the implementation dual FTLB and VTLB is denoted by the value of 0x4 in any valid entries within th nfigurable.thechoice The common of is done page size purpose. Someof the address a smallerof entries number TLB with many entries can be much less than that of than less much entries can be with many TLB register is used to program the page size used for a partic- between the instructionstr “ChangesRegisters”the to COP0 page on 323 LB entries is implementation specific. C0_PageMask l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. presented to presented both the FTLB and VTLB in parallel. Entries in both structures ed in the FTLB fields within the new llowable at a specific TLB index. llowable at a specific able-Page-Size TLB or the VTLB. able-Page-Size TLB LB as appropriate for FTLB the chosen field. The presence of the field. The ch for the physical address. lly-associative TLB. lly-associative MMUSize-1 Config1 register field. are describedThese registers in once for the entire FTLB, not on a per-entry basis. This basis. once for the entirea per-entry on not FTLB, full flush/initializationthe before there FTLB, are of also allowedFTLB the to support one only for page size ware and not software configurable. configurable. software not and ware invalid TLB to represent reserved address values entr can limit what addresses are a what addresses can limit ferent from the size used by another VTLB entry. entry. VTLB by another used the size ferent from MT • The commonpageallowed size is software co to be • The required EHINVis FTLB implementation. for TLB invalidatefeature legacy The method of using implementing a large fu implementing a large • The VTLB is fully-associative. • Theisentries implementation number of specific. • TheofVT set allowable sizes for page • basis. Thepage choiceper-entry onis done of size a without consuming a large numberwithoutin of entries the FTLB. consuminga large ular VTLB entry. ular VTLB entry. The configuration of the FTLB is reflect ing only uses one page size so the FTLB is sufficient for this ing for only uses one pagesize so the FTLB is sufficient indexaddress are used to into FT the which FTLB way to modify is implementation specific. The VTLB is very similar to the The JTLB. is reflected in the is Config large address blockslarge toMMU. the be simultaneously mapped by Most implementationswouldchoose to build a VTLB with combinationThis ofnumber entries. allows for many on-dema 2.Vari the TLB is called The second •sections of physical memory pages to mapthe large The capabilitya VTLB retains existence of oflarge using in MMU mainly the happens in of pages Random replacement The use of two TLB structures has these benefits: • The implementationbuilding costs of a set-associative address translation, the virtual address is translation, the virtual address address parallel to sear in are accessed Just as for the JTLB, both the FTLB and VTLB are shared JTLB, both for the Just as 320 MIPS® Architecture Vo For Programmers Alternative MMU Organizations Alternative

regis- regis- 1 / C0_Random C0_EntryLo0 ture, Rev. 6.02 Rev. ture, 321 and x bits needed to select the needed to x bits plementation specific whether a plementation specific C0_EntryHi acy method of representing an invalid acy method ed FTLB way and set, and incremented and ed FTLB way Inanyindexing scheme, the least signifi- and TLBWRinstructions. ed Resource Architec ed Resource tries. This register to choose is also used which BWR instruction modifies entries within the FTLB ll be modified for thiscase. struction, it is possible for software to choose an inap-software struction,for it is possible (VIndex) leastsignificant(VIndex) bits of the 2 FTLB. Since it is implementationas to whether defined a A.3 TLBs Fixed-Page-Size and Variable-Page-Size Dual anteed to work. anteed to (FPageSize)+1. The number of inde number of (FPageSize)+1. The 2 array are accessed through the through array are accessed accessed with the TLBWI accessed ndex to VIndex + (FSetSize * FWays)-1. (FSetSize * FWays)-1. + to VIndex ndex lue is the concatenation of the select for a specific virtual address, the leg specific virtual address, for a (FSetSize). which canbeusedby the TLBWI instruction without modification by soft- 2 ss value is not guar notis ss value e FTLB as well as the VTLB use one tag (VPN2) to map two physical pages tag (VPN2) to map one use as the VTLB as well FTLB e ted for the TLBWI instruction. ple, {selected FTLB Way, selected FTLB Set} selected + VIndex. ple, {selected FTLB Way, III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: s in one way of the FTLB. of s in one way ructions; the VTLB occupies indices 0 to ructions; the VTLB occupies indices 0 to and inst TLBR TLBWI the TLBP, registers, on specific whether the VTLB wi array is indexed is array is indexed is implementation specific. used by the FTLB entries LB. The entries in either in entries LB. The C0_Wired , the isnotto set the page size used by the FTLB, the TLBWR instructionwithin modifies entries the is set to the page size used by the FTLB, the TL page size used by the FTLB, to the is set register is used to set the page size for the VTLB en the page size for the VTLB register is used to set C0_Index PageMask C0_PageMask C0_PageMask The VTLB. The VTLB entry to be written is specified by the log How the FTLB set-associative by the size of the VTLB. For exam size of by the If VTLB. It is implementati the or log can be used for indexing is that bit cant address VIndex-1. The FTLB occupiesVIndex-1. VI indices The TLBP instruction produces a value referringware. When to the FTLB, the va Since the FTLB array canbemodified throughthe TLBWI in propriate FTLB indexim value forit is the specified virtualcase, In this address. Machine Check exception is genera Machine required for a is feature invalidate TLB entry EHINV The particular FTLB index value can be used (PFN), just as in the JT (PFN), just as The software The software programming interface used for the JTLB is fully-associative maintained as much as to possible amountdecrease the of software porting. th each entry in Also for that purpose, correct set withinFTLB thearray is log ter value. ters. Entries in either array (FTLB or VTLB) can be array (FTLB or VTLB) to write for the TLBWR instruction. the TLBWR for to write VTLB) or (FTLB array used:Forare followingofthe this section, the rest parameters 3.size FPageSize - the page 4.of entrie FSetSize - Number 5.FTLB. Numberthe - of ways within a set of FWays 6.Number VIndex - of entriesVTLB. in the For the The method of choosing which FTLB way to modify is implementation specific. If TLB entryusing by a predefined addre A.3.2Interface Programming MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

. (FTLB and VTLB) arrays and VTLB) arrays (FTLB C0_Index (a value within VIndex to VIn- ged Resource Architecture, Rev. 6.02 using virtual19:13.address bits The eck exception is generated for these is exception these cases. generated for eck for way selection within the FTLB. the within selection way for e specified virtual e specified address. . de the selected FTLB set as opposed to which bits are tation specific whether both tation values VIndex to VIndex+(FSetSize * FWays)-1 access VIndex to VIndex+(FSetSize * FWays)-1 values on specific, but must match what is expected by the specific, but must match what is expected on reflects the page used by the size FTLB. C0_EntryHi iswide 3 bitsentry to select the within the VTLB. specifiestheentry within the VTLB (a value withinto VIndex-1). 0 specifies the entry within the FTLB specifies the entry within the read depending on the specified index in read depending C0_PageMask ich starts at virtual12. address bit l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. FTLB set-associative array is indexed array is FTLB set-associative C0_Index C0_Index are probed in parallel for th for are probed in parallel C0_Random ructions; the VTLB occupies indices 0 to ructions; the VTLB occupies indices 0 to and inst TLBR TLBWI the TLBP, registers, implementation chooses these values: these values: implementation chooses gn uses a cycle counter of 2 bits of 2 bits counter a cycle gn uses e address bits held in overlapping entries and overlapping whether Ch a Machine index bits are needed. index C0_Wired , the register field within C0_Index Random If the address hits in the the in FTLB, hits the address If Index values of 0 to VIndex-1 access the VTLB. Index the VTLB. to VIndex-1 access 0 of Index values the FTLB. Both the the the VTLB and FTLB Both FTLB entry is a VTLB entry or Either a If the address hits in the VTLB, the in VTLB, hits the address If ping (512 entries x 2 pages/entry x 4 kB/page) 4MB of address space simultaneously. space 4MBof address x 4 kB/page) pages/entry 2 x ping (512 entries dex+(FSetSize * FWays)-1). Which bits are used to enco dex+(FSetSize * FWays)-1). used to encode the selected FTLB way is implementati the selected used to encode TLBWI instructionimplementation. TLBWR instruction uses thes 7. The FTLB occupies indices7. 519. 8 to The FTLB entries have a VPN2 field wh index the FTLB significantbitvirtualleastbe used for FTLB indexingcan address that virtual13.The is To address 7 set-associative array, thisIn simple the example,uses design contiguous address virtual bits directly for indexingthe (it FTLB cre- does not ate for the FTLB indexing). a hash The TLBWI TLBP TLBR As an example, let’s assume an assume As example, an let’s 1.FTLBentries - 4 kB used by the FPageSize 2.thein FTLB. - 128 FSetSize of one way 3.4 ways within FTLB. (TheFTLB the - ways/set)4 of a set xhas (128 512 sets entries, capableof map- FWays 4.VTLB.8 entries in the - VIndex For the are checked for duplicate or duplicate for are checked For both the TLBWR and TLBWI instruction, it is implemen In this simple example, the desi The A.3.2.1sizes VTLB and FTLB chosen with Example A.3.3 to the TLB Instructions Changes 322 MIPS® Architecture Vo For Programmers Alternative MMU Organizations Alternative

is not for more for field is not field is Config4 fields reflect the . VPN2 . ture, Rev. 6.02 Rev. ture, 323 d to reflect only the size FTLBSets for is appropriate the specified and register field mustbeset to a register. C0_Index C0_Random e TLBWR instruction modifies modifies a e TLBWR instruction Config4 C0_EntryHi MMUExtDef FTLBWays ed Resource Architec ed Resource , tion is implemented. If either registerredefine field is TLBWR modifies either a FTLB entry or a VLTB or a VLTB entry FTLB TLBWR modifies either a Config4 field of values VIndex to VIndex+(FSetSize * FWays)-1 access VIndex to VIndex+(FSetSize* FWays)-1 values VPN2 fied. The FTLB set-associative array is indexed in an indexed array is fied. The FTLB set-associative A.3 TLBs Fixed-Page-Size and Variable-Page-Size Dual FTLBPageSize MMUSize-1 nding on the specified page size in C0_PageMask. C0_PageMask. size in page nding on the specified generate a machine-check exception if the a machine-check exception generate than that used by the FTLB, th the FTLB, used by than that bythe Random register within field s a Machine Check exception for these cases. for these Machine Check exception s a s a Machine Check exception for these cases. for these exception Machine Check s a field is not fixed to 2 or 3, the Dualfieldtheor VTLB/FTLB configuration2 is not fixed to 3, is not “Configuration Register 4 (CP0 Register 16, Select 4)” on page 253 is reserved; for the see the description e hardware checks(FTLB and VTLB) for valid both duplicateor over- arrays

flect the FTLB configuration. the Dual VTLB and FTLBconfigura the Dual VTLB and III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: if the hardware the if the hardware checks MMUExtDef specific which array is modi array is specific which MMUExtDef is fixedofa value to 2 or 3, the is fixed to a value of 2 or 3, the 3, is2 or fixed to a valueof

Config4 is set to any page size other is set to the page size used by the FTLB, the to the page is set Config4 is fixed to a value of 4, the implemented MMU Type is the dual FTLB and VTLB configuration.FTLB is the dual value4, the implementedis fixedto of a MMU Type

MMUExtDef MMUExtDef MT Config Config4 C0_PageMask C0_PageMask Config4 detail on thisregister. For Release 6, value ofvaluethatreflect 2 or 3 to set within the FTLB. The implementationset within FTLB. The the may implemented or the If implemented. If Index values of 0 to VIndex-1 access the VTLB. Index the VTLB. access to VIndex-1 0 of Index values the FTLB. It is implementation specific Either the VTLB or FTLB entry is writtenorEitherFTLB entry is depending the VTLB the specified index on in appropriate for the specified set. specified appropriate for the It is implementation-specifithe hardwarec if and VTLB) for(FTLB checks both valid arrays over- duplicate or lappingentriesif the hardware signal and A new register introducedre to of the VTLB. If FTLB configuration. Please refer to VTLB entry. The VTLB entry is specified VTLB entry. implementation-specific manner. implementation-specific manner. selectingThe methodwhich of modify FTLB way to is implementation specific. It is implementation specific if th lappingentriesif the hardware signal and entry. It is implementation entry. If Either the VTLB or FTLB entry is writtenorEither FTLB entry is depe the VTLB If C0_Config4 (CP0Register 16, Select 4) C0_Config (CP0 Register 16, Select 0) C0_Config1 (CP0Register 16, Select 1) TLBWR A.3.4Registers to the COP0 Changes MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

C0_Index C0_RANDOM odified by a TLBWR ld a value of VIndex-1orld a value of zes are available in the VTLB. register field. field. register select the VTLB entry which is mod- ged Resource Architecture, Rev. 6.02 or the FTLB is m is FTLB the or the FTLB, and a TLBWR instruction is exe- TLBWR instruction is FTLB, and a the FPageSize e FTLB, and a TLBWR instruction is exe- FTLB, and a TLBWRinstruction is e MMU are the values reported in the the TLBWI instructionimplementation. ementation specific the whether Config4 register field can only ho entry in the FTLB or the VTLB. Index values of 0 to FTLBor the VTLB. Index values entry in the VIndex+(FSetSize * FWays)-1 access the FTLB. access the * FWays)-1 VIndex+(FSetSize fields reflect what page si this alternative MMU configuration, the value reflects both Wired MaskX and Random register field is used to sizes which are available in the FTLB. Mask register field value is VIndex. register field value is entry is modified. It is impl l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. ispage-size set to theth used by is not set to the page-size used by set when a FTLB entry is specified. set when a FTLB entry is anges introduced by this alternative alternative introduced by this anges but mustbut match what is expected by Random field values determine whether the VTLB field values determine whether the entries.TLB address matchFTLB operationthe The for affect fields do not register ster 5, Select 0) is fixedofa value to 2 or 3, the is fixedofa value to 2 or 3, the register is redefinedin this way: is fixedofa valueregister 2 or 3, the toin is redefined way: this is fixedofa value or 3, the register to 2 is redefinedin this way: MaskX MaskX C0_PageMask C0_PageMask and and MMUExtDef MMUExtDef MMUExtDef MMUExtDef Mask Mask

The VIndex-1 access the VTLB. Index values VIndex to values VIndex Index VTLB. the VIndex-1 access Which bits in the register field which encode the FTLB set as opposed to which bits encode the wayFTLB is implementation specific, The value held in the Index field can refer to either an in the Index field can The value held If the value in The software writeable bits in the cuted, a FTLB entry or a VTLB or a entry cuted, a FTLB cuted, a VTLB entry is modified. The is entry VTLB cuted, a ified. the value in If register is used to select the FTLB entry. FTLBentry. register is used to select the boundThe upper of the These fields do not reflect the page not reflect the do fields These page size used by the FTLB entries are specified by the entries are specified by the page size used by the FTLB instruction. The Config4 Config4 Config4 Config4 For Release 6, this register has beenthis register deprecated. has For Release 6, If If less. That is, only VTLB entries can be wired down. If If C0_Random (CP0 Register 1, Select1, 0) C0_Random(CP0 Register C0_PageMask (CP0 Regi (CP0 C0_PageMask a selected way as well as a selected well as selected way as a register. Previously, it was just a simple linear index. For Previously, register. One of the main software visible ch C0_Index (CP0 Register 0, Select 0) Select Register 0, (CP0 C0_Index C0_Wired (CP0 Register 6, Select 0) C0_Wired A.3.5 Compatibility Software 324 MIPS® Architecture Vo For Programmers Alternative MMU Organizations Alternative

registerfields must VPN2 bits to VPN2 bits index ture, Rev. 6.02 Rev. ture, 325 FTLBSets EntryHi register. register. Config4 acy method of representing an invalid of representing acy method and C0_Index ed Resource Architec ed Resource FTLBWays ction. Software then justissuesinstruc- TLBWI the ed for wired-down pages, so this restriction should not Config4 , FTLB. Since it is implementation-definedto whether as a A.3 TLBs Fixed-Page-Size and Variable-Page-Size Dual anteed to work. work. anteed to , that page, thatbe programmed must into the the VTLB using field no longer field no longer initial- size. For TLB reports the entire MMU MMUSize-1 appropriately modified. appropriately MMUSize-1 Config1 for a specific virtual address, the leg address, specific virtual for a of TLB entries that must be initialized. TLB initialization and flushing are ss value is not guar notis ss value III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: registers have been have registers * C0_EnLo registerupon instru a TLBP by hardware is generated Another software visible change is that the change is that the software visible Another ization flushing, and TLB contentsthe of tion once the Only the VTLB entriesOnlymay the VTLB be wired down. This limitation toisduesome using of the Fortunately, this Indexfrequently valueisn’t generated by software norFortunately, byread software. Instead, the contents of the C0_Index all be number read to the entire calculate the onlysoftware times to generate an Index needs write to value into the TLBWI instruction, as the TLBWR would instruction only access the situation and could not any in that FTLB access instruction The TLBWI is normally us wired-down TLB entry. existing software. affect required for a is feature invalidate TLB entry EHINV The particular FTLB index can be used value the FTLB array. downwiredto a pageusing be the FTLB page-size is If TLB entry byusing a predefined addre MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

ged Resource Architecture, Rev. 6.02 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. 326 MIPS® Architecture Vo For Programmers Alternative MMU Organizations Alternative

, IntCtl, PageGrain, chitecture. Changes Changes chitecture. pseudo pseudo code to deal ture, Rev. 6.02 Rev. ture, 327 ft Reset Exceptions. ft Reset acknowledge the fact acknowledge the ng and virtual tags. location discussion. location show an example of the need need of the example an show ve been updated ve to reflect the documentation. Release 2 of the Ar of the Release 2 ed: Cause, Config, Config2, Config3, Config3, Config2, ed: Cause, Config, the list of exceptions that do not go through the list of exceptions that do not go through both virtual both virtual indexi rewritten to reflect the Release 2 changes. Release the to reflect rewritten chitecture added: EBase, HWREna ed Resource Architec ed Resource s between Reset and So neral exception processing exception neral e TLB lookup process to , PerfCnt, Status, WatchHi, WatchLo. WatchHi, , PerfCnt, Status, note that both BadVPN2 and R fields are UNPRE- fields and R note that both BadVPN2 Description B entries to be 3, not 2, and entries to be 3, not 2, and B supported with a Fixed Mapping MMU. supported with a Fixed Mapping gisters were modifi gisters were mory, exceptions, and hazards ha exceptions, and mory, may support all page sizes. all page may support implementation-dependent. organized and updated ar and updated organized for external review release ation with the changes introduced in the changes introduced with ation to denote an instruction cache with cache instruction an to denote VI sed on review feedback: sed III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: with extended MIPS16e instructions. with extended MIPS16e SRSCtl, SRSMap. the general exception processing mechanism. error after an address exception. DICTABLE EntryHi, EntryLo0, EntryLo1, PageMask 2. Release in changes that not all implementations for 3. for • Config Add in this revision include: • new Coprocessor 0 registers following were The • Coprocessor 0 following The re • me descriptions of Virtual The •adjustment in ge offset incorrect branch Fix • description to register XContext Correct • that Note Supervisor Mode is not • bits 4..3 as Define TagLo • Describe the intended usage model difference •added. shadow registers has been GPR chapter on A • chapter on has been The CP0 hazards completely • vector Debug entry the EJTAG in Change ProbEn to ProbeTrap • exceptions Debug to error and EJTAG cache Add •of TL Correct the minimum number • Modify the description of PageMask and th 0.9512, 2001 March document Clean up 1.0029, 2002 August ba Update 0.92 January 200120, copy of re Internal review 1.90 September 1, 2002 specific Update the Revision Date MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For Revision History Revision Appendix B Appendix

to the Fixed Mapping Mapping Fixed to the red in certain combinations of red in certain combinations the time that the processor that the the time be gated by be gated by enable. 1K page ference for the purposes of the purposes the for ference d that software which preserves d that software which preserves Config registers should be field and a RDPGPR and WRP- register should be a R/W bit, not a register rrupt via an ERET. bit to indicate that bit the controls PSS and ged Resource Architecture, Rev. 6.02 registers. PCI IP1 0 Status to zero in all bit positions less than or equal equal or than less positions bit all in zero to set to 0b11 on a Release 2 chip in ker- which set to 0b11 Status definition as a pointer definition as rnal Interrupt Controller Interrupt Mode to rnal Controller Interrupt Interrupt note that the SRSCtl register is not updated at ange hazards for writes ange hazards to interrupt-related Cause the software interrupt handler runs. interrupt Software the software table, and document that DERET, ERET, and and ERET, table, and document that DERET, PS MT and MIPS® DSP present bits in the in the bits DSP present MIPS® PS MT and PerfCnt ility of triggering a triggering ility of the probab ich reduced = 1. 15 12 nges. These include: nges. These BEV , and Description en using VI modes. or EIC Interrupt able to Operating Modes chapter. Modes to Operating able mply dismiss the inte register as access enablesimplementation-depen-for the the registerscorrectly. willalso run Status upt being deasserted between deasserted between upt being ve reference load is a data re ll hazards before the instruction fetch at the target instruction. target at the fetch the instruction before ll hazards sk register power up zero and up zero register power sk elease 2 cha elease 2 e vector offset. This is only e vector requi offset. Compare vs. an execution hazard. dependent bits in the the bits in dependent HWREna clude R ftware must set EBase Cause, , going to the EIC, rather than Status than rather EIC, the to going Status IP1 0 l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. registers. Watch Config3 register. detects the interrupt request and the time that that time the and request the interrupt detects si and case this for prepared be must a clear exceptions and interrupts R bit. This eliminates the This eliminates of problem having these bits support. page enabled 1K not has software nel 0xBFC0.0300,. not 0xBFC0.0200. in which the end of an exception GPR and instruction hazard GPR and change that introduced EBase. that introduced change the in fields dent hardware registers 31 and 30. and registers 31 hardware dent will run, an standard boot software such a way that defined in the value of the field when writing MMU appendix. allowed. are the performance counter, not the timer interrupt. timer not the counter, performance the show Cause to the most significant in th bit most significant to the vector number and vector spacing wh machine check. • a hardware interr note about Add • list Add of MIPS® MT CP0 registers and MI • that so restriction Add • hazards the CP0 of organization Improve the • PageMa of the bits 12..11 Make • cache be address of the error vector when the the is It should Correct BEV bit 1. • to shadow registers to introduction the Correct • 2 Release the reflect to description exception error cache the in pseudo-code the Correct • Document that EHB clears instruction state ch • Clarify thatPC-relati a MIPS16e • Update allfiles to FrameMaker 7.1. •requirements. reset 2 Release missing reflect to list exception reset Update • bits 31..30 in the Define • that Note implementation- • in the FR bit the Architecture 2 of the Release With • for Coprocessor definition Add 0 En • K23 Add and KU fields to main Config register • specific note about Add all shadow sets between the need to implement 0 and HSS - no holes • SRSCtl the to write software a from hazard the Change • Interrupt the figure Generation Correct for Exte • suggested software Add TLB init routine wh • the encoding table description for Correct the 2.00 9, 2003 June Complete the update to in 2.50 July 1, 2005 Changes in this revision: Revision Date 328 MIPS® Architecture Vo For Programmers Revision History

, FDCI bit bit , FDCI Config4 register for ture, Rev. 6.02 Rev. ture, 329 C0_Config3 EIC an explicit vec- EIC driving MT was incorrect in saying only saying incorrect in was ion Vector. Changed to Changed ion Vector. Config tion description. tion Exception Type table. Type Exception register. register. register affected. ed Resource Architec ed Resource C options - RIPL=VectorNum, Explicit Vector- Explicit - RIPL=VectorNum, C options IntCtl ’t have a fixed reset value. ’t iguration to Appendix A iguration to Appendix and TLB; just can’t be used for mapping. be used for TLB; just can’t selected debug selected debug except HWENA cess is allowed to CDMM region. Description COP0 Register, CDMM bit in CDMM bit COP0 Register, nal meanings for CCA values. values. CCA for meanings nal ation pseudo-code for EIC Option_3 (EIC sends entire vec- sends entire (EIC Option_3 EIC for pseudo-code ation COPUnusable Excep COPUnusable ProbEn . CDMMBase COP0 register ng EJTAG & PDTrace Registers & PDTrace ng EJTAG Config4. denoted by 0x4 in configuration CDMMBase release for internal review: release release for internal review: release release for internal review: release release for internal review: release for internal review: release release for internal review: release

a bunch of missing ones missing of bunch a register and access to it viathe instruction. RDHWR C0_PerfCtl are actually R/W actually are e ERL behavior description behavior description register description, the ERL . accessed through $3 not $4 - UserLocal Status ProbTrap III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: C0_Cause register field in and IPFDC Num; Explicit VectorOffset. Num; Explicit VectorOffset. tor offset (not using VectorNumbers). VectorNumbers). using (not tor offset Add the Add C0_DataLo/Hi ECR tor). in these new MMU configurations 29 bits of kuseg becomes 29 bits of kuseg becomes uncached and unmapped. •ECR incorrectly saying was Table • Clarified the text and diagrams 3 for the EI • 2.70, was actually missing the option of - revision mode new EIC • fixed. typos Various • ksseg/sseg about - footnote Modes Operating • extensions customer for usable longer COP3 no •RIPL != VectorNum Mode allows EIC • - added missi CP0Regs Table • • table Hazards - added • scratch registers. kernel as 2 & 3 31, Select Reg CP0 Added • conf optional MMU VTLB/FTLB Added • Added TLBP -> TLBWI hazard • in field KScrExist Added • Added statement that only uncached ac • traditio MIPS Technologies Added • to Added list of COP2 instruction •Oper Handling Exception Updated • • Fixedcomments for ASE. •Enable Bit in CDMM Added •used to init can be values Reserved CCA •doesn Field CDMMBase_Upper_Address • to C0_Cause Disabled Exception Added DSP State • • chapter, CDMM Added • to bit added PCTD 2.802009 July 20, •VTLB MMU and FTLB 2.722009 April 20, MIPS Technologies-only 2.712009 January 28, MIPS Technologies-only 2.61 August 01, 2008 • In the 2.702009 January 22, MIPS Technologies-only 2.732.742009 April 22, MIPS Technologies-only 03, 2009 June MIPS Technologies-only 2.7512, 2009 June MIPS Technologies-only 2.60 June 25, 2008 Changes in this revision: 2.62 2,009 January • CCRes is Revision Date MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

onships with the ended, but additional r future debugger use. r future correct. PTEVld bit is only PTEVld correct. go into the BadVPN2 field was BadVPN2 field go into the ster and the relati able if Config3.CTXTC=1 and Config3.CTXTC=1 able if ged Resource Architecture, Rev. 6.02 32-bit architectures. lect 1 is reserved fo - selects 2&3 are recomm are 2&3 - selects for RI & XI bits. & XI RI for onControl/EVA. onControl/EVA. Description t. Config5 register added. updated for RI & XI bits. RI & XI for updated evious description wasn’t fully description wasn’t evious implemented as XIE and RIE bits are allowed to be Read- allowed are RIE bits as XIE and implemented for internal review: for internal pdated for SmartMIPS behavior. SmartMIPS behavior. pdated for ption codes instead of exception using own their to use programmed gister allowed to be write- in EntryHi and WatchHi. in EntryHi and WatchHi. r Segmentati ctures, for no changes d for RIE and XIE bits. XIE RIE and d for description added. description Table Walking Feature Walking Table release release for internal review: release release for internal review: release release for internal review: release for internal review: release release for internal review: release to C0 Register list. list. to C0 Register

fg1, SegCfg2 registers fg1, SegCfg2 the BadVPN2 field within Context regi the BadVPN2 field scriptions updated scriptions updated ContextConfig register. ContextConfig e moved from e moved SmartMIPS ASE. se register added. se register l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. dInstr & BadInstrP registers. scratch registers are scratch allowed. used for Directory PTE entries as leaf PTE entries are always loaded from memory. from memory. loaded always are entries PTE leaf as entries PTE Directory for used TLBL code. Only. Config3.SM=0. writable bits within incorrect for the case when the ContextConfig register is used. The correct VA bits 31:31- are bits VA correct The is used. register when the ContextConfig case the for incorrect MIPS32. for ((X-Y)-1) • register updated Config3 for CTXTC and RXI bits. • C0_Status. and ASE bits in C0_Cause Reserve MCU • Clean up description for KScratch registers • register. Debug2 Added •register update PageMask • description and pseudo-code TLB • - pr Walker Hardware Page Table • ContextConfig Register • u description Context Register • register de EntryLo* • Added TLB init routine fo • features added microMIPS • ASE MCU features added. • and RI exceptions can XI be • and RI can XI be independently • added Register TCOpt • bit. Status.FR of change after UNPREDICTABLE are registers FPR • not support CCA=0 did 1004K • - Registers, Config4 KScratch mention that se • bits Context Register - the bit VA subscripts describing which • suppor Exception handling Nested •cache way. one (0x7) for 32 sets for Added encoding • bits of C0_Context Lower re • Hardware Page Added •added: scheme Control, EVA Segmentation a) Adds SegCfg0, SegC • extended ASID field Added b) SegCtl - Modifies EBase, Config3. • Invalidate TLB feature. 3.112011 April 24, Technologies-only MIPS 2.8122, 2009 September Technologies-only MIPS 3.002010 March 8, • RI/XI featur 2.822010 January 19, MIPS Technologies-only 3.51 October 2, 2012 MIPS Technologies-only 3.1417, 2012 February Technologies-only MIPS 3.132011 November 10, Technologies-only MIPS 3.10 July 27, 2010 • of the limits Explain 3.052010 July 07, • CMGCRBa 3.12 April 201128, • Changes for 64-bit archite 3.50 201220, September • Ba Added Revision Date 330 MIPS® Architecture Vo For Programmers Revision History

in Register table. in Register s the largest value sup- largest s the ture, Rev. 6.02 Rev. ture, 331 eld Descriptions, FR r zeroing out read-only read-only out zeroing r if is sup- floating-point oldest in machine. Meaning- machine. oldest in in Cause exception types. Cause in riptions, AR bit (Architecture revision extension bits (of EntryLo,TagLo) if extension bits (of EntryLo,TagLo) write of all 1s return all of write Release 5. Like Release 3, all features intro- features all 3, Release Like 5. Release sufficient for their purpose. Less testing. sufficient t to 0, but the current POR solution is for 9.41 Status Register Register Fi Status 9.41 Directory PTE entries can represent power-of- represent PTE entries can Directory 0. Since mth/mfhc0 may be used indepen- ed Resource Architec ed Resource registers and control bits and registers le. HW is responsible fo e, not supported in MIPS32, in MIPS64 only Registers match on 2nd half Registers match of microMIPS odel required is required, is required, odel required not mean mthc0/mfhc0 are implemented. implemented. are mthc0/mfhc0 mean not from list of extensions. COP0 registers requiring Description to initialize the Watch , TagLo, CDMMBase, CMGCRBase CDMMBase, , TagLo, d to record different types of Machine Check Exceptions. Check Exceptions. types of Machine d to record different Register Field Desc Field Register e available in kernelmode. Re-iterate that. that. Re-iterate in kernelmode. e available hould not contain comment about nd Virtualization exceptions nd Virtualization r a ig3.LPA, Config5.MVH ig3.LPA, DSP ASEs -> Modules now deprecated. ng Dual Page Method. ng Dual ent change: ude MSA and Virtualization ude MSA and Virtualization t template III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: ported. Section 3.5.2 64-bit FPR Enable. Table Section 3.5.2 64-bit ported. FPR Table Enable. (floating-point register mode) bit. register mode) (floating-point level). AR=1 indicates Release 2 or Release 3 or 3 or Release 2 level). AR=1 indicates Release duced in Release 5 are optional. instruction. region, usi memory 4 ful to Speculate=0. Moved outside sub-table. ful outside to Moved Speculate=0. PageGrain.ELPA=0. HW had been asked to rese to been asked HW had PageGrain.ELPA=0. mtc0 to 0 out the extension bits that are writab that are bits the extension 0 out to mtc0 ported. bits on operation that updates the bits. which is up to 36b The two registers support PA Fur- of multiple. instead one bit to query for software it is easier in the future, of XPA dently on 64-bit HW need ther Config3.LPA=1 AAR initial version AAR initial •- MT and changes R5 •MDMX - changes R5 • by hardware” -> “Preset “Preset” •logos cover Update •text copyright Update •- include R5 changes MSA a •Config 9.57 Table R5 extension: •featur Pages Big BPG, 9.59 Table Correction: • FTLB/VTLB - if PageMask set to FTLB size, allowed to modify VTLB. • whether implementation-dependent • PTE. of 4-byte - give example Walker Hardware Page Table • - added option so Walker Hardware Page Table •PageGrain.MCCause fiel Optional •- MAARI.Index to sw write of condition a Added • MAAR, MAARI and Config5.MRP Add •s 1.1 typo. Speculate=1 Table • extended EntryLo0/1, LLAddr Add • Conf PageGrain.ELPA, •having about SW comment Remove • Remove CDMMBaseCMGCRBase and • for mth/mfhc Config5.MVH, bit, a config Add 5.01 December 16, 2012 • technical cont No 5.02 2012 April • m FPU register changes: FR=1 R5 64-bit 5.00 December 14, 2012 • incl - changes R5 5.04 September 29, 2013 M 5.03 September 9, 2013 • Update documen 3.52 12, 2012 November • segment(s) Overlay SegCtl 5.04 November 12, 2013Version. initial XPA Revision Date MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

). Table 9.2 field. n bits now are required. ). register. SW must now must must now must SW register. Mask ged Resource Architecture, Rev. 6.02 Table 9.2 : no longer required : required to no longer write specified values while s/w can only set to 1. only s/w can while d significantly. required, all other values are optional all optional and required, other values are must be 1. must P register leaves it unmodified. it leaves register

does not modify register. ported values to the Wired field. Wired ported values to the ULRI EntryHi Index , : hardware unsupported values to the C : hardware ignores writes of C n encoding 2 has changed. before changing a value in this changing before Config3 bit field. d if an value d if an unsupported is written. CFG

, : now required. : must now be 1. PageMask n tionality has change , : HW ignores a write of 1; ; now R/W0 (see R/W0 ; now of 1; write a : HW ignores Limit BI RXI explicitly using TLBWI. NMI bit. bit. register. SegCtl , RP TS Cofig3 and KScratch BadInstrP, BidInstr, UserLocal, PTEI Config3 KU Status / : now required. : write of unsupported value : new field. : write of 0 value is ignored. EntryLo0/1 andom , : HW ignores writes of unsupported values to the to values unsupported writes of : HW ignores and and : now required. : now will be unchange and : now required, and required, now : : HW ignores a write of the value. the of a write : HW ignores l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. : HW ignores a write of 1; R/W0 (see now K23 Status Status R n upported values of this field. values of unsupported of ignore writes : HW must : now required. Also, now required. : : in field size. change and / ULR : writing unsupported values to this : now required. : now PTW PTEI BP SBRI C : HW ignores writes of values. reserved WP AR ULRI K0 bit 28: new name and changed functionality. and name new bit 28: changed functionality. and name new bit 27: now reserved. 21: and bit bit 25 CU SR KSU PWField : added a required : hardware ignores writes of unsup ignores writes : hardware : If value greater than, or equal to, the number of TLB entries is written, HW leaves this this leaves HW is written, entries TLB of number the to, or equal than, greater value : If Reset value changed to 2. is 2 illegal, are values 0,1 that Clarified implementation-specific. PTEI VS Config5 Wired RDHWR Wired Config3 Cause Cofig3 Config4format and func : field. Index register unchanged. EntryLo BadInstr required. BadInstrP: now Status Status Status Status Status Coprocessor 0 Coprocessor UserLocal Status IntCtl KScratch PageMask PWSize Config PWField PWSize invalidate TLB entries entries TLB invalidate to certain fields and flush TLB TLB flush and fields certain to Config PageGrain • • • • • • • Removed • Removed • • • COP0Index: Clarification - h/w clears • • • • • • • • • • • • •COP0 •COP0 • • • • • • • • • 6.00 March 31, 2014 • Removed Revision Date Description 332 MIPS® Architecture Vo For Programmers Revision History

ture, Rev. 6.02 Rev. ture, 333 l page support. Addr and LLB fields are are LLB fields Addr and . . ; added clarifications to ; added clarifications MAAR COP0 . . PWField dded optional smal dded optional ed Resource Architec ed Resource UFE/FRE PTW to indicated both the LL ching capability. range cannot speculate. range LLB Config5 PWSize MAAR tr, XNP capabilities (new) XNP capabilities tr, Config5 for endian swit for register for R6 multi-threading R6 multi-threading register for support. and to eliminate 1 kB pages; a kB 1 eliminate to . to detect presence of L2 Config2 in to detect presence for R6 multi-threading for R6 multi-threading support. : in Release 6 with multi-threading, this is replaced by VPNum. by VPNum. is replaced this 6 with multi-threading, : in Release VP L2c DEC/CES LLAddr MAAR . bal Number PageMask PTEI Config5 Config5 Glo Config5 Default is not to speculate not to speculate is Default by be specified it must to speculate, If an address is Addresses outside of the Addresses outside of the III: MIPS32® / microMIPS32™ Privileg / MIPS32® III: EBaseCPUNum mandatory for R6. for mandatory PWField • COP0 Updated • Made minor change to reset state of •minor Made changes to reset state in allfieldsof •added XNP. CES and - rm Config5 Updated • support: Added Modeless Evil Twin •(new) MT for VPControl CP0 Added •PerfC HWREna with Updated • Modified • • CP0 Updated • Added • Added • Added 6.022015 July 10, • (new) DebugContextID BEVVA, CP0 Added 6.01 17, 2014 October • Added Revision Date Description MIPS® Architecture For Programmers Vol. Programmers MIPS® Architecture For

ged Resource Architecture, Rev. 6.02 reserved. rights All Inc. Computing, www.wavecomp.ai Wave l. III: MIPS32® / microMIPS32™ Privile / MIPS32® III: l. © Copyright 334 MIPS® Architecture Vo For Programmers Revision History