MIPS® Architecture For Programmers Vol. III: MIPS32® / microMIPS32™ Privileged Resource Architecture Document Number: MD00090 Revision 6.02 July 10, 2015 Public. This publication contains proprietary information which is subject to change without notice and is supplied ‘as is’, without any warranty of any kind. Template: nB1.03, Built with tags: 2B ARCH MIPS32 2 MIPS® Architecture For Programmers Vol. III: MIPS32® / microMIPS32™ Privileged Resource Architecture, Rev. 6.02 Contents Chapter 1: About This Book ................................................................................................................ 13 1.1: Typographical Conventions ....................................................................................................................... 14 1.1.1: Italic Text.......................................................................................................................................... 14 1.1.2: Bold Text.......................................................................................................................................... 14 1.1.3: Courier Text ..................................................................................................................................... 14 1.2: UNPREDICTABLE and UNDEFINED ....................................................................................................... 14 1.2.1: UNPREDICTABLE........................................................................................................................... 14 1.2.2: UNDEFINED .................................................................................................................................... 15 1.2.3: UNSTABLE ...................................................................................................................................... 15 1.3: Special Symbols in Pseudocode Notation................................................................................................. 15 1.4: For More Information ................................................................................................................................. 18 Chapter 2: The MIPS32 and microMIPS32 Privileged Resource Architecture ................................ 19 2.1: Introduction................................................................................................................................................ 19 2.2: The MIPS Coprocessor Model .................................................................................................................. 19 2.2.1: CP0 - The System Coprocessor ...................................................................................................... 19 2.2.2: CP0 Registers.................................................................................................................................. 19 Chapter 3: MIPS32 and microMIPS32 Operating Modes................................................................... 21 3.1: Debug Mode ............................................................................................................................................. 21 3.2: Kernel Mode .............................................................................................................................................. 21 3.3: Supervisor Mode ....................................................................................................................................... 21 3.4: User Mode ................................................................................................................................................. 22 3.5: Other Modes.............................................................................................................................................. 22 3.5.1: 64-bit Floating-Point Operations Enable .......................................................................................... 22 3.5.2: 64-bit FPR Enable............................................................................................................................ 22 3.5.3: Coprocessor 0 Enable...................................................................................................................... 23 3.5.4: ISA Mode ......................................................................................................................................... 23 Chapter 4: Virtual Memory ................................................................................................................... 25 4.1: Differences between Releases of the Architecture.................................................................................... 25 4.1.1: Virtual Memory................................................................................................................................. 25 4.1.2: Protection of Virtual Memory Pages................................................................................................. 25 4.1.3: Context Register .............................................................................................................................. 25 4.1.4: Segmentation Control ...................................................................................................................... 26 4.1.5: Enhanced Virtual Addressing........................................................................................................... 26 4.2: Terminology............................................................................................................................................... 26 4.2.1: Address Space................................................................................................................................. 26 4.2.2: Segment and Segment Size ............................................................................................................ 26 4.2.3: Physical Address Size (PABITS) ..................................................................................................... 26 4.3: Virtual Address Spaces ............................................................................................................................. 26 4.4: Compliance................................................................................................................................................ 29 4.5: Access Control as a Function of Address and Operating Mode................................................................ 30 4.6: Address Translation and Cacheability and Coherency Attributes for the kseg0 and kseg1 Segments..... 30 4.7: Address Translation for the kuseg Segment when StatusERL = 1............................................................. 31 4.8: Special Behavior for the kseg3 Segment when DebugDM = 1................................................................... 31 MIPS® Architecture For Programmers Vol. III: MIPS32® / microMIPS32™ Privileged Resource Architecture, Rev. 6.02 3 4.9: TLB-Based Virtual Address Translation .................................................................................................... 31 4.9.1: Address Space Identifiers (ASID) .................................................................................................... 32 4.9.2: TLB Organization ............................................................................................................................. 32 4.9.3: TLB Initialization............................................................................................................................... 33 4.9.4: Address Translation ......................................................................................................................... 36 4.10: Segmentation Control ............................................................................................................................. 40 4.10.1: Exception Behavior under Segmentation Control .......................................................................... 43 4.11: Enhanced Virtual Addressing .................................................................................................................. 48 4.11.1: EVA Segmentation Control Configuration...................................................................................... 48 4.11.2: Enhanced Virtual Address (EVA) Instructions................................................................................ 50 4.12: Hardware Page Table Walker ................................................................................................................. 52 4.12.1: Multi-Level Page Table support ..................................................................................................... 53 4.12.2: PTE and Directory Entry Format.................................................................................................... 57 4.12.3: Hardware page table walking process ........................................................................................... 60 Chapter 5: Common Device Memory Map.......................................................................................... 67 5.1: CDMMBase Register................................................................................................................................. 67 5.2: CDMM - Access Control and Device Register Blocks ............................................................................... 68 5.2.1: Access Control and Status Registers............................................................................................... 69 Chapter 6: Interrupts and Exceptions................................................................................................