Mechatronics 1387Spring
8051 +P+K J1+@8$ O5
> .K8Š$ J1+@8$ %+@F(! 28P1 -.S O1O5
YData bus Y ROM Y RAM Y CPU ! (+' l@C E, G$) .K8Š$ J1+@8$ u' "FS •Dc Peripheral & Interface Ciruits YControl bus Y Address bus
Address bus Data bus Countrol bus CPU
Interface RAM ROM circuitry
Peripheral devices
(CPU) Central Processing Unit :$%&' ( )$* + , #!"
! CPU u' "FS * >7 8P /^ %.C"$ •.`T$ + .8Š$ J1+@8$ u' •Dc 9'+hh "3 3 (Fetch & Execute Instructions) hhhhm); *+hc 1 2[^ y (98$+h^ ') " h8F(! * hh>J 7^ ' , (1 (Arithmatic/Logic Operations) "hh?G $ 1 " hh 3 T$ R hh8F(! w hhh<) (2 (Sequence/ Timing Control) + .8Š$ J jFKk$ •Dc jFKk$ R 8F(! * , B $ 1 ˆ8 + -+K J (3
: ! CPU u' "F:% •Dc Instruction Program Register (IR) Counter (PC) *+, m); *%/ : CPU "F:% * hh>2[^ y ' Registers C h,"$ "S : \ hhŽ$ *+, +p'% *%/ 1 "$.(! \ hhŽ$ Special purpose (Stack pointer ' Status Register hh ) $) Instruction Registers decode and */, v: a %; I) mp) : (PC) program Counter countrol unit 2[^ y % (next instrudion) */, " h8F(! J ' 2$ )+, General purpose Arithmatic Registers and Logic unit B $+^ *+, binary J : (IR) Instruction Register .%.C "$ * mp) IR % Y+c - y % (instruction)
G.R. Vossoughi, Sharif Univ. of Tech. 5 Mechatronics 1387Spring
instruction *+, binary hJ (2h(c+ ) +8 / lh$ ! : Instruction Decode/Control unit instruction B% 1; % +hhc 2, 7mc (I+8€ 1 "hhP+K J R 8F(!) 8) % .$ R 8F(! w <) 1 IR % %.c.$ +[)% .$
98$+^ E z +,) "_ ' 1 "?G $ R 8F(! B% 1; % +hhc 2, l$ ! : Arithmatic Logic Unit (ALU) (Instruction decoder / Control unit "K^ ' %
*+c 1 2[^ y 98$+^ ' " 8F(! * hhhh>J ", ' , CPU J 9'+ I(! C I hhC •A H 2J .G) hh(> .%.C "$ 2K#W fetching 2[^ y " 8F(! * >J ' instruction ", ' , 2, . C , "$ m);
.C , "$ +' ly+$ l$ C %.: 2[^ y 98$+^ B%+J (Fetch) ", ' , 2Fy+$ ' R 8F(! .%.C "$ 2KCVW Address bus *1 +, Program Counter (PC) *.KT$ O1 .%%+W "$ - /^ READ "P+K J - p83 O2 I%% +H data bus *1 +, 1 IC Ih).: 2hz.,+$ a %; (data) K'% ' (instruction) 98$+h^ O3 .%.C "$
IR "hhF:% +hhhK`8c B1 % 2, data bus *1 (instruction code) .hh,D$ B hh$+^ O4 .%%+W "$ l?K $ (Instruction Register) (*/, Fetch l@83 *+, "hhhW% $; 7mc) %.C "$ I%% &'D^ (Program Counter) PC *.KT$ O5
CPU Address bus N Program Data bus Counter Opcode Instruction RAM Register N+2 Control bus Clock N+1 Opcode N Read N-1
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IC ", ' , B $+^ ' J +8 / l$ C (Execution stage) 98$+^ *+c 2Fy+$ ' R h8F(! *.hhKT$ - 3 7mc h8)% .$ "hP+K J * hhhmP p83 8P. Y (instruction decoding) *+c 7mc 8)% .$ "P+K J * hhmP p83 8P. 1 e@/P , 1 ALU B1 % 2, "F:% * h>register .C , "$ ALU v3. "_ ' 1 "?G $ R 8F(!
v3. l$ J .G, CPU %+@F(! 1 >%"$ l8@n 2$ )+, u' Y 98$+^ 1 " 8F(! * >J 2!.(<$ Program “drives” the CPU : %%+W "$ }kn$ 2$ )+,
(Address, Data & Control bus) "$ ( ) 12 3 . /0/ :$%&' ()$* + , #-
2K^+W @, "J+Kn$ \> , 2J - h p83 7'> •.G: ' Z83 *%/ 73 l@nK$ (bus) I W VW u' .'%+W }kn$ instruction Fetch &k, % *y .,D$ I W VW 23 u' +> &?) 1 %+@F(! . ).C "$
+tJy ">% a %; "' hh). .,D$ cpu YC , 78, n * % cpu u' *+, a , a %; 2@8 .S % 9' VhP 1 73 "K8,16 a , a %; 8051 +hhhP+K J1+@8$ *+, . 7C% hh>.: 7' , 2n 65535 .C , 2KC% 2[^ y 64Kb = ' 65535=216 +tJy ). "$ +P+K J1+@8$ 1024 lh@83 +> % 2J 73 w.m#$ 9', 9' YC , 78, n * % CPU u' *+, a , hK'% 2hh@8 .S % 1 HD ) h$) I/O " ) c RD8m< 1 2[^ hhy Y CPU 98, I%% 78, n v?^ write ' Read Zm$ l$.! "@' ( a , K'% •.G: %/ ') data bus ’+! VP .%%+W "$ l?K $ (... 1 .hK8) $ I J 988/ Zm$ * h>2Žkn$ 1 '%+W •.`T$ + .8Š$ J1+@8$ u' B1 % R !Az -% hh 7!+3 .`31+f1+@8$ 2J %.C"$ 2K#W "KH1 •A h t $ .%%+W "$ •.`T$ CPU v3. R !Az 0%+f 7!+3 .73 "K8, 32 data bus .`31+f1+hh@8$ 9' % 2J 73 w.m#$ 9', 9' 73 "K8, 32 Y P-IV .73 "K8, 8 a , K'% 8051 %
. 73 2^+z 1% I .(> a , K'% 2@8 .S % (uni-directional) 73 2^+hhhG@' I .(> a , a %;
G.R. Vossoughi, Sharif Univ. of Tech. 7 Mechatronics 1387Spring
- hhh?K) jFKk$ R 8F(! I J “ > (> &?) 2J 73 "' hhhmP p83 * 2!.(<$ l$ C a , -+K J B. "$ mP p83 2hhh).p ' *2hh).() . C ,"$ % Im! a , K'% 1 a , a %; *1 +, R !Az 1 I%., ‰. K$ 8`, m); &?) 1 "P+K J * hhmP p83 %/ 1 w ) .%+, w ) WRITE 1 READ 1 Clock .% % CPU ‰.) 2, *% ' "pK`,
,)$8 )) 5 67% :$%&' ()$* + , #4
CD-ROM Y HDD Y FDD ) $ : (mass storage) I. ) * hh3I+8:” RDh8m< -
Y Keyboard Y+hhK '+f Y- 8$+ ) $ : (Human interface) B `) , • RD8m< - speaker Y Mouse :• l$.! * >%+, ' > $ * >R+f 1 profi Y 7)+K ' * hhh>2@ C : (Communication) " z RD8m< - 2G31 - '+3 1 *.$
>+pF(! 1 > .` 3 ‰.) ) $ : “ ' .K8).$ 1 "P+K J RD8m< -
: 9$ :$%&' ()$* + , # Application B. /, % hh3 "$ +H+, user , Z8?K`$ • hh 2J * Dhh^ w+) i].(/$ • % D^ 7k3 , * D^w+) 2'] 1% E'+z D^ w+) 9' Y%.C "$ 2K: hh C Software .73 ‚'+n l, H l, ?$ w+W '% v3. K: 3 9' .C , "$
Application Software Dh^ 7k3 hh, Z8?K`$ .hhhhG, Input/output Subroutines (user interface) a ( % (... 1 A/D 1 D/A %+, 1 HD YCRT Y keyboard ) $) Operating System 98 † E'+z +h .8Š$ J u' * >"c1+: 1 > *%1 1 28FJ 1 I%., hh> Subroutine 2hh).p ' .%+8W "$ w <) "' hhh>Subroutine Input/output routines ' Basic I/O System ) hh$) IC * mp) ROM % “• $.(!“ (access to hardware) .).C "$ 2KC.) assembly B , 2, • $.(! 1 (IBM-PC % BIOS Hardware * hhh>+K$ f %1 1 , • $.(! I/O subroutines I% hhh#K3 B%+J initialize E'+z (Subroutine parameters ) 2hhhz.,+$ E'+z 2FS y •' K) Y subroutine call w <) ef 1 I'%+hW h€; CPU * hhhh>+K`8c *%/ .%.C "$ 7^ ' , RAM % "Žkn$ * h> a %; E'+z ' 1 CPU * hhhh>+K`8c +p'% *%/
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B%+hhhJ reset ef 2n8(> 2J 73 start-up 2$ )+, u' *1 y ROM Y h> I/O subroutine +, I1A! 2, (pc) program counter I .hhhh(> Y CPU B%+hhhhhJ reset ef .%%+hhhW "$ - hhh/^ CPU B (> ) .,D$ a %; % %.c.$ 2h$ )+, VP 1 2K^ h' +88— – 0000H •].(/$ – ROM B1 % "hhŽkn$ a %; *+p'% a %; 2, jmp u' 0000H a %; % ˆF€ 2K P) '%+W >.: +c CPU v3. (startup 2$ )+, 1 2[^ y B%+J u† B.‹(> " hh8F(! w <) +, I1A! Start up 2$ hhhhh)+, ( ... 1 %+8W "$ w <) ROM % Track Y Bootstrap Loader w , ROM B1 % +p'% routine u' B% S , Y-.(/$ * hh> ", 'ˆ8! Operating "K(`H 2$ )+, 9' .) Š3"$ B, -+K J 1 I).:+^ RAM lh:% 2, uh`'% -1 .) Š3"$ B; 2, -+K J 1 I).:+^ (RAM) 2[^ y l:% 2, u`'% *1 system
(DOS Command Language hhh ) hh$) user interface 9h8$ h +, I1A! Operating Sytem .C , "$ Application Software 8P. 1 "`'.)2$ )+, 2, B8nk, 7P.m3 7mc "' hh> D, * %
+P+K J1+@8$ 1 .`31+f1+@8$ 98, R1 # O2O5
" 8$ %) 7`8) IC I%% +H IC u' *1 +, 2J CPU u' Dc *D8† .h`31+f1+@8$ •].S (73 %+, 9' † "Ky 1 IC 9' † l@nK$ %.: CPU > main frame 1 >+ .Š8$ J
+P+K J1+@8$ u' % Z8), +' w+W '% % IC I%% B n) •Dc l@nK$ + .8Š$ J1+@8$ u' +W hh ) $) R hhh8S.Ž: 8`, % • $.(! 2K P . 73 IC I%% * c IC u' % I%+ $ ) •Dc 28FJ u' (interrupt ' 2#H1 •.G: %/ 1 - '+3 * hhhhhh>R+f %/ Y ROM 1 RAM &' < W h, .,D$ * > 7'%1T$ 2K P .C , + .8Š$ J1+@8$ u' + %1T$ 8`, 73 9@($ +P+K J1+@8$ .73 28c. l, H ("P+K J * >ZK`83 %) >+P+K J1+@8$ %+, J % .$ 2, 2c.
External External Serial Parallel Clocks interrupts Device Device Internal Clocks
Interrupt Serial Parallel Timers control interface interface
CPU
RAM ROM
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* c IC u' % (+hhhP+K J1+@8$ %+,) "P+K J %+, u' 7: 3 *+, 8) % .$ •Dc ˆF€ 2@ ' 2, 2c. , 1 "y+z 2 'D> 9' 2J C ,"$ 7: 3 l, H IC "(J 8`, %/ , +P+K J1+@8$ * >%+, VP IC I%% .% %"$ 2p) 98' f 8`, >%+, 2).p ' 7: 3
"' ). 9' h, .73 (interrupts) 2#H1 0%+f % m); "' ). Y >+P+K J1+@8$ "FJ * > 2Žkn$ "@' ' clock * hhhhh>e P f ) $) jFKk$ (events) b' H1 2, ). "$ (+hhhP+K J1+@8$) "P+K J ZhhK`83 .C , .pk3 f • /'+3 ( * +G_ * >78/_1
98$+^ ' " 8F(! J %/ 1 j8z % +P+K J1+@8$ 1 .hhh`31+f1+@8$ u' 98, * > R1 # +p'% "@' , B%+J J "' ). Y(98p 3) R !Az 0%+f \> , .hhh`31+f1+@8$ u' .73 (instruction set) 1 I'%+W "y+z ... 1 (arrays) • D, * >2' ; , B%+J J 7P.m3 Y"K' , 8 1 "K' , 4 Y"K' ,2 * >I%% . C , "$ >%+, J 2).p ' *+, "S : (instruction) " 8F(! * >J * % VP
C , 2, n$ * > J 1 2P u' B%+J 0.$ : 1 9C1 \> 73 9@($ +hP+K J1+@8$ u' % 2@); - y u' % %.c.$ ">% a %; * >$ 1 > instruction * 8`, Y2hh 'D> 9KCmp) 98' f .[ (, Y1 9' v3. l?K`$ .G, > 78, -+K J "' ). 2@); - y Y%.C "() I'% +hhhP+K J1+@8$ u' % .`31+f1+@8$ 1 hhhh> instruction %/ &'D^ , ) .73 +'Vf B @$ +P+K J1+@8$ % "S : * hhhhh> instruction %1y 8051 +P+K J1+@8$ u' % - t$ *+, . , ' "$ &'D^ • / , + 3 ... 1 7: 3 1 "y+z * hh> 2 'D> 80286 .hh`31+f1+@8$ u' % 2K^ @, .K`'D)+ %/ 2@); - y 1 2K^ @, .hK`'D)+ 60/000 .K`'D)+ B.8F8$3/1 %1y pentuim u' % 1 B.8F8$1/2 %1y 80486 u' % 1134/000 %1y (. 73 IC \+Ž$ B.8F8$ 42 %1y Pentium IV .K`'D)+ B.8F8$ 5/5 %1y pentiume pro % 1
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MSC-51 I%.) : * >+P+K J1+@8$ * D^7k3 R Žkn$ O3O5
, 2, INTEL 7J+C v3. 1980 2>% l'1 % 2J K`> >+P+K J1+@8$ *I %.) : MSC-51 8K$ 9hK^+W , philips 1 Fujitsu Y AMD Ye (' ) $ jFKk$ * hhh>7J+C eŠ3 1 IC 2_+! : )%.() 2_+! , 2, (%.: ™ : * >"' ). , u' +>) B; jhFKk$ "' mP$ Y 7: 3
Memory Timers/event Device Internal ROM Interrupts RAM Counters
8031 - 128 x 8-bit 2x16-bit 5
8032 - 256 x 8-bit 3x16-bit 6
8051 4K x 8 ROM 128 x 8-bit 2x16-bit 5
8052 8K x 8 ROM 256 x 8-bit 3x16-bit 6
8751 4K x 8 UV-EPROM 128 x 8-bit 2x16-bit 5
8752 8K x 8 UV-EPROM 256 x 8-bit 3x16-bit 6
.C , "$ +' l@C E, G$ MCS-51 I%.) : * D^7k3 R Žkn$ 1 ")1 % K: 3 •Dc
Internal bus
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2J %.C"$ 2_+! " 8f 44 PLCC 1 " 8f 40 DIP w+^ 1% % MCS-51( I%.) : • $.(! 1) 8051 98f 4 PLCC ‰.) *hh , 2K`, % .C , "$ (packaging) *hhh , 2K`, I.T) % m); I(! R1 # (NC ≡No connection) 73 I% #K3 A, pin 44 : 73 +' ž+n, ŽK: 2, 8051 +P+K J1+@8$ % 2K^ @, 98f 40 u' +> &?)
8032/8052 only
T2 T2EX
Y%%+W I% h#K3 "F:% ROM 1 RAM • ^ + S 2@8 .S % "$.(! \ Ž$ 7mc *.$ "K8,8 Port u' B. /, P∅ 78, 8 B. /, • J + K n $ P∅ R .Ž ' +8€ % . 73 I% #K3 l, H 8 a , K'% u' 1 (2[^ hy -1 l@83 Z8) %) a , a %; -1 1 RAM , • 7mc (2[^ y w1% l@83 Z8) %) "K8, 7mc “ALE” - p83 .' () "$ l(! "c hhh: ROM .%.C "$ I% #K3 K'% 1 a %; B%+J demultiplex
1 "$.(! \ Ž$ 7mc *.$ "K8, 8 Port u' P1 R+f (bit addressable) "c : * > D^ 7k3 , •
Y%%+W I% hhh#K3 "F:% ROM 1 RAM • ^ + S 2@8 .S % l, H "$.(! \ Ž$ 7mc *.$ "K8, 8 Port u' B. /, P2 a %; w1% 78, 8 B. /, P2 R .Ž '+8€ % . 73 I% #K3 .' () "$ l(! ("c : ROM 1 RAM , • 7mc ) a ,
G.R. Vossoughi, Sharif Univ. of Tech. 12 Mechatronics 1387Spring
12 MHz •].(/$ Oscillator e) J+^ .C , "$ 16 MHz
*1 +, bH1 (Output enable) OE 98f 2, 98f 9' Instruction w hhp m, .%%+W "$ lŽK$ "c h: ROM Program - hhh p83 9' (ROM " 8F(! J ", ' ,) Fetch Store Enable .%.C"$ Low Address Latch u' 2, a %; B%+J Latch 1 B%+J demultiplex *+, Enable ef .%1 "$ hh@, ( P0 *1 ) "c : +hK`8c Master reset ALE Y P0 *1 +hh, B; BC h' f 1 a %; .Ÿy .%%+W "$ Hi Y address latch - hhhhhhh p83 B. /,
* >+K`8c Pin 9hh' BhhC Hi hhhhh, +hhf IC 988/ &8f *+'% ?$ , "F:% (start-up R 8F(! *+, ) )%+W "$
ROM 8051 Y%.C 2KCmp) Hi Y EA +hhhhW " 8' f 4K ) 2$ )+, B).: 7mc "hhhhhF:% Low EA 2h@8 .S % .' ()"$ I% hhh#K3 (2hh[^ y PSEN - h p83 I% #K3 , Y%.C 2KCmp) " 8' f 4K %) 2$ h)+, ").: , 7mc "c : ROM "F:% ROM " hhh /, ) .' ()"$ I% hh#K3 (2[^ y ( %%+W "$ - /^+8€ External access BIT BIT NAME ALTERNATE FUNCTION ADDRESS P3.0 RXD B0H Receive data for serial port P3.1 TXD B1H Transmit data for serial port P3.2 INT0 B2H External Exterrupt 0 P3.3 INT1 B3H External intereupt 1 P3.4 T0 B4H Timer/counter 0 external input P3.5 T1 B5H Timer/counter 1 external input P3.6 WR B6H External data memory write strobe P3.7 RD B7H External data memory read strobe P1.0 T2 90H Timer/counter 2 external input P1.1 T2EX 91H Timer/counter 2 capture/ reload
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8 $, )RAM 8
(B-register) used in MUL AB; DIV AB Accumulator(A register) 1 2 , 8
Program Status Word) ' 2 Used By serial 1 Communication 7
, Interrupt Priority Reister Prog. in ROM ' s t c i 8 b 7 Port P3 ` 8 K 2 +
M Interrupt Enable Reister 1 > A Port P2 h h R h h % h Serial Port Buffer h : Serial Port Control Register F * "
Port P1 % ) , : F +
Timer 0 & 1 " * )
High and Low byte , $ Ž $
Timer Mode Register Ž
Timer Control Register \ Power Control Register ! \ ( .
Data Pointer : $ High and Low byte " ( Stack Pointer ™ Port P0 ( RAM (128 Bytes) (21 Bytes)
.73 I'%+W Z8`? 28y ) 23 2, %.: Y"F:% RAM 7' , 128
.% % %.c1 2[^ y 28y ) 9' I% #K3 01 1% :(7F H "P 30H a %;) General purpose RAM •
: ) $ (Direct Addressing) Z8?K`$ ">%a %; (1) mov A, 5FH ; Move the content of the 5FH address into Accumulator mov 5FH, A ; Move the content of the Accumulator into 5FH address mov R1, 5FH ; Move the content of the 5FH address into the R1 register mov 5FH, R1 ; Move the content of the R1 register into 5FH address
: ) $ (Indirect Addressing) Z8?K`$+8€ ">% a %; (2) mov R0, #5FH ; Move number 5FH into the R0 Register mov A, @R0 ; Move the content of the memory location whose address is inside R0 into the Accumulator (i.e. move content of 5FH into Accum.) . K`> I% #K3 l, H E'+z 1% 98(> 2, RAM 7' , 128 lJ 2K P
bit B%+J CLEAR hhh' B%+J SET 7mc At$ :(2FH "hhhP 20H a %;) bit addressable RAM • .%.C "$ I% #K3 “CLR 67H” 1“SETB 67H” 98$+^ ("F:% RAM ) 2CH I (C 7, , ZK#>
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8051 instruction set summary
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A Sample Program: test.asm ; This program turns on the LEDs attached to port P1 in a decreasing-binary-number order ORG 2000H DEL EQU 040H ;DELAY TIME OR SPEED FACTOR
START: MOV DEL,#01 MOV P1,#0FFH L: DEC P1 CALL DELAY SJMP L
DELAY: MOV R0,DEL DEL1: MOV R1,#0FFH DEL2: DJNZ R1,DEL2 ; Internal Loop DJNZ R0,DEL1 ; External Loop RET END. C> T51 tst ; Assembles and Locates the program C> sim ; program simulator …followed by F7….”P”….”N”….”test”….”F5” C> EVTRNC2 ; Download the program from COM2: port onto the 8051 board RAM
> Timer %+@F(! O6O5
B, 4O5O6 &k, % 2hhhJ 73 “ripple counter” u' %+@F(! 2, n$ hhh8`, Timer %+h@F(! B. /, ). "$ 0 hh(C BD8$ Y98/$ e) J+^ , Clock eP f 2, Timer *%1 1 - Ž , . C 2K:%+f 2 P •A t $ ) +hpC (C 2, *%1 1 2@8 .S % "hh^+z .%+8W +H I% hhh#K3 % .$ B $ 2 3 T$ *+, "' $ l, H Event Counter u' B. /, +hhhpC (C I hhhp); C , 2/H1 u' ‰.H1 (- p83 u' I)1 98' f 7mc + 98' f e) J+^ , "P p83 ). "$ e) J+^ Z`?$ u' B.hh /, +pC (C • (_ . %., >.: I% #K3 .' () 8P. +p'% \ Ž$
. K`> I% #K3 l, H jFKk$ \> 23 *+, "F:% * > Timer Y8051 %
98/$ lS.^ % (B $ \+/$) "c1+: - p83 8P. 7mc ... Interval Timing (jP
(73 ™ : pin u' *1 +, I)1 98' f * > 2 P B (> 2J) b' H1 0 (C *+, ... Event Counting (•
\+/$ 2J 98/$ e) J+^ , "P hhh p83 8P. ... Baud rate generation for built-in serial port (¬ . C , "$ - '+3 R+f *+, baud rate
.C , "$ timer 1 1 timer 0 * m$ , "K8, 16 +(' 1% * % 8051
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I.T) Z8[ *+, ) TMOD +K`8c % 2z.,+$ * hhh> 78, ' , K, >timer I% h#K3 7mc • .%.C"$ w <) 2$ )+, *K, % 1 @' v?^ h@ ' .).C set +[)% .$ +'% ?$ 2, ( >+(' %+@F(!
R+f % baud rate Z8[ *+, (Timer 1) 1 +hh(' aAJ 9' % I% #K3 % .$ "C.$; %+, % • 2c1 8m, ' ) VP .(+P+K J1+@8$ %+, 1 PC +hh .8Š$ J 98, • % <' *+, ) %.C "$ I% h#K3 - '+3 .).C * hhh@K3% (7 "P 4 * mK8, ) TMOD +K`8c % Timer 1 2, 2z.,+$ * hhh>78,
Interrupts O7-5
+d % 2J (}kn$+8€ ") $ % • $.(!) (event) 2/H1 u' 1+, 7h` ! 2hh#H1 ' interuupt u' • 2J (ISR) Interrupt service routine w , *+p'% X$ )+, 1 IC hh> • KH.$ Y+c - y % X$ )+, B; Interrupt w , 2J ISR 2$ )+, .'" $ % +c 2, IC 2KC.) (event) 2#H1 2, ">% ´3 f 7mc ‰.H1 l H +c - hhy % 2$ )+,) X8P1 2$ )+, 2, -+K J Y+c ef %.C "$ 2K: h C D8) Handler . )%+W"$+, (2#H1
%.hc., "h(>. 98 † YhC , 2hKC% 2#H1 2, "'.pk3 f "' ). 2J *+hh .8Š$ J ZK`83 u' 2J %.C "$ 2K#W • hh$.(! .>% "$ w <) jFKk$ J 9' † B h$D(> .G, + .8Š$ J 2J % 1; "$ % ISR * > 2$ hhhh)+, 1 (Foreground ' ) base-level % +hhhhc 73% % "FS X$ hhhh)+, : ).C "$ +c (background ') Interrupt-level
ISR ISR Interrupt level Execution * ** * ** main main main Base level Execution Time
* Interrupt ** Return from Interrupt service routine
: % % %.c1 2#H1 ' interrupt 8P. *+, jFKk$ b $ 5 Y 8051 %
Two Timer interrupt Two Ext. Interrupt One. Serial port interrupt ++2F83., IC 8P. 2#H1 1% "c : 2#H1 1% (- '+3 R+f v3. IC 8P. 2#H1 u') INT 0 , INT1 Timer 0 1 Timer1 Over flow w p m,
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.%.() (disable) - /^+8€ ' (enabled) - /^ B. "$ .hh,D$ b $ 5 u' +> E'+z 2#H1 ‰.H1 8 .%.C "$ w hhh<) 0A8H a %; % bH1 (Interrupt Enable) IE +hhhhK`8c v3. l(! 9' 1 C , "$ .hhh,D$ * hhhh>2#H1 u' +> 9K: 3 - /^+8€ ' - /^ *+, -1 78, 5 Y IE +K`8c 78, : %1 "$ @, * hhhh> 2#H1 28FJ * 3- /^+8€ ' * 3- hhh/^ 7mc (ZKn> 78,) +:; 78,
DESCRIPTION BIT SYMBOL BIT ADDRESS (1=ENABLE, 0=DISABLE) IE.7 EA AFH Global enable/disable IE.6 - AEH Undefined IE.5 ET2 ADH Enable Timer 2 Interrupt (8052) IE.4 ES ACH Enable serial port interrupt IE.3 ET1 ABH Enable Timer 1 interrupt IE.2 EX1 AAH Enable external 1 interrupt IE.1 ET0 A9H Enable Timer 0 interrupt IE.0 EX0 A8H Enable external 0 interrupt
78, Z> 1 ET0 78, Z> ' , Timer 0 E'+z 2#H1 B%+J - /^ 7mc Y- t$ *+, Y„.^ -1c E z +, : ).C Set B $D(> EA SETB ET0 SETB EA v3. 2J (- '+3 R+f 2#H1 ) $) +p'% * > 2#H1 Y+[)% .$ * > 2#H1 B%+J - /^ % 2J %.() 2c. ' , • ( _ . %.n) I%% +88— Y%+8W "$ +H I% #K3 % .$ - '+3 R+f 2$ )+,
ˆF€ % VhhP Y C , % .h:+, *+hhh ] , 7'.P1 73 9@($ b' hhhH1 "Ÿ/, 1+, 2hh@8U <); Yh)).8Š, ‰.H., B $D(> .G, 2#H1 1% +W 2hh@'.T , % % %.c1 >2#H1 * , 7'.P1 B @$ > .`31+f1+@8$ 2z.,+$ (Interrupt service routines) * > ISR B% S *+, "S : ˆ8 + Y7'.P1 a 3 +, B.K, 2#H1 u' YISR w <) w p m, +W 2J % `8$ Z>+^ B @$ 9' 98 ‹(> > 2#H1 B%+J * , 7'.P1 . C lU H > + 98' f 78P1 , 2#H1 2, 2z.,+$ ISR Y • KH.$ ).K, .h`31+f1+@8$ Y%).8Š, ‰.H., *+hhh ] , 7'.P1 , .%%+Š, + ] , 7'.P1 , X#H1 2, "'.pk3 f 2, 1 2K: 3
G.R. Vossoughi, Sharif Univ. of Tech. 30 Mechatronics 1387Spring
* hhhh> 2#H1 *+, (Two priority levels) 7'.P1 ‚G3 1% v?^ •A J 8051 +hhP+K J1+@8$ % u' +h> 2, •.,+$ * > 78, Y2#H1 8P. b $ 5 u' +> * , 7'.P1 7mc . 73 988 l, H jFKk$ .%% +88— 1 ' 0 2, B. "$ (Interrupt priority register) +K`8c % > 2#H1
DESCRIPTION BIT SYMBOL BIT ADDRESS (1=HIGHER LEVEL, 0=LOWER LEVEL) IP.7 Undefined IP.6 Undefined IP.5 PT2 0BDH Poriority for Timer 2 interrupt : (8052) IP.4 PS 0BCH Poriority for Serial port intrrupt IP.3 PT1 0BBH Poriority for Timer 1 interrupt IP.2 PX1 0BAH Poriority for external 1 interrupt IP.1 PT0 0B9H Poriority for Timer 0 interrupt IP.0 PX0 0B8H Poriority for external 0 interrupt
8P. 2#H1 7'.P1 “SETB PX0” 1 “CLR PT0” B $+^ w hh<) , - t$ *+, „.^ -1c 2, 2c. , INT 0 "c hh: - hh p83 vhh3. IC 8P. 2#H1 7'.P1 1 ”+hh#S“ +hhh,+, Timer 0 v3. IC hh>.: Timer 0 2hhh#H1 7'.hhP1 + ] , INT 0 2#H1 7'.hP1 ˆ8 + 9', 1 . %., h>.: “1” +,+, .C >.: Z8[ “0” +,+, hhh>2#H1 28FJ 7'.P1 8051 +P+K J1+@8$ B%+J reset - ), .%.,
B%+hJ Poll 7mc "S : ˆ8 + +P+K J1+@8$ YB $D(> .G, B `@' 7'.P1 , 2#H1 1% ‰.H1 R .S % Y Timer 1 Y INT1 Y Timer 0 Y INT0 7` ! Polling ˆ8 + .' () "$ 7' ! hh>2#H1 * >2#H1 2, "W83 ˆ8 + I J 988/ .,D$ ˆ8 + VP Y (8052 *+hh, Timer 2 1) Serial port .C , "$ +P+K J1+@8$ v3. ( K`> B `@' 7'.P1 * % 2J ) jFKk$
2J) SCON 1 TCON * h> +K`8c % +?K`$ . 2z.,+$ (Flag) * >78, v3. Y > 2#H1 28FJ 78/_1 2#H1 u' B%., - /^+8€ R .S % . C h, "$ ", hhhh8K3% l, H ( K`> 2#H1 I J 8P. b, $ B (> "3 +, 1 " 8, , l, H * D^ w+) R .Ž, 2hhz.,+$ (Flag ') 78, $ Y%.C"() 8P. 2z.,+$ 2#H1 Y™ : ( %.C 2/c+$ +' -1c 2,) 73
INTERRUPT FLAG REGISTER NSME AND BIT POSITON External 0 IE0 TCON.1 External 1 IE1 Ext.Int TCON.3 Timer 1 TF1 TCON.7 Timer 0 TF0 Timer overflows TCON.5 Serial port T1 SCON.1 Serial port RI OR SCON.0 Timer 2 TF2 T2CON.7 (8052) Timer 2 EXF2 T2CON.6 (8052)
G.R. Vossoughi, Sharif Univ. of Tech. 31 Mechatronics 1387Spring
2#H1 0%+f I.T)
0%+f 2, 1 2K: 3 > +c - y % 2$ )+, ( > .`31+f1+@8$ 28FJ • $.(! 1) +P+K J1+@8$ 2#H1 u' 1+, , :%%+f"$ +' ly+$ E z +, ISR
.%%+W "$ l8(@ "FS 2$ )+, +c - y % B $+^ (jP
(ISR *+c ef 7nW , a %;) %%+W "$ I+8:” stack *1 +, Program Counter (•
(Interrupt status >2#H1 (Status ') 78/_1 . %.n8$ lS y > 2#H1 w ( Flag BC OR 2#H1 (¬ ...)%+W "$ I+8:” "Fhhh:% .G, C , "$ l H 2T#S -1c % IC +J” * hhh> flag B (> 2J Register) .%%+W "$ 988/ a 3 98(> +, 2#H1 I J 8P. bhh $ •/,
. ).C"$ 2J.F, + 98' f , B `@' 7'.P1 , * >2#H1 (%
Program lh:% % 2hh#H1 I J8P. b $ a hh3 +, (Interrupt service routine) ISR a %; (I ISR *+, "Žkn$ a %; * % 2hhh#H1 Ihh J 8P. b $ 5 u' +hh> .%.C "$ I%% +hH Counter C ,"$
.%.C "$ +c ISR 2$ )+, (1 B h' f % RET B $+^ 2, n$) (return from interrupt)RETI B $+^ *+c , 1 ISR B ' f % ( 28P1 ?$ 1 IC ", ' , stack *1 Program Counter 28P1 ?$ (Subroutine %) "hhhFS 2$ )+, 2, -+K J 2<8K) % .%.C "$ (restore) ", ' , D8) Interrupt status register .%.C "$ I)%+W , (2#H1 ‰.H1 lT$
Interrupt Vector
Program ?$ 2h@K`); Y2#H1 u' 0%+f ly+$ 2F(c YC I C l H 2T#S % 2J .G) (> a %; 2h#H1 I J 8P. b $ a 3 +, 1 YIC I%% +H stack *1 +, 2#H1 ‰.H1 2[TP % Counter 2, .%.C"$ I%% +H Program Counter % (Interrupt Service Routine a %; B h(>) 'c .%.C "$ 2K#W Interrupt Vectors .,D$ * >a %;
: 73 +' ž+n, 805x +P+K J1+@8$ *+, Interrupt Vectors 2, •.,+$ * >a %; -1c
G.R. Vossoughi, Sharif Univ. of Tech. 32