Design and Implementation of Ternary Logic Integrated Circuits by Using Novel Two-Dimensional Materials

applied sciences

Article Design and Implementation of Ternary Logic Integrated Circuits by Using Novel Two-Dimensional Materials

Mingqiang Huang 1, Xingli Wang 1, Guangchao Zhao 1, Philippe Coquet 1,2 and Bengkang Tay 1,*

1 CNRS-International-NTU-THALES-Research-Alliance (CINTRA), Nanyang Technological University, Singapore 639798, Singapore; [email protected] (M.H.); [email protected] (X.W.); [email protected] (G.Z.); [email protected] (P.C.) 2 Institut d’Electronique, de Microélectronique et de Nanotechnologie (IEMN), CNRS UMR 8520-Université de Lille, 59650 Villeneuve d’Ascq, France * Correspondence: [email protected]; Tel.: +65-6790-4533

Received: 29 August 2019; Accepted: 4 October 2019; Published: 9 October 2019

Abstract: With the approaching end of Moore’s Law (that the number of transistors in a dense integrated circuit doubles every two years), the logic data density in modern binary digital integrated circuits can hardly be further improved due to the physical limitation. In this aspect, ternary logic (0, 1, 2) is a promising substitute to binary (0, 1) because of its higher number of logic states. In this work, we carry out a systematical study on the emerging two-dimensional (2D) materials (MoS2 and Black Phosphorus)-based ternary logic from individual ternary logic devices to large scale ternary integrated circuits. Various ternary logic devices, including the standard ternary inverter (STI), negative ternary inverter (NTI), positive ternary inverter (PTI) and especially the ternary decrement cycling inverter (DCI), have been successfully implemented using the 2D materials. Then, by taking advantage of the optimized ternary adder algorithm and the novel ternary cycling inverter, we design a novel ternary ripple-carry adder with great circuitry simplicity. Our design shows about a 50% reduction in the required number of transistors compared to the existing ternary technology. This work paves a new way for the ternary integrated circuits design, and shows potential to fulﬁll higher logic data density and a smaller chip area in the future.

Keywords: 2D materials; black phosphorus; inverter; ternary logic; adder

1. Introduction Integrated circuits (IC) are the cornerstone of modern information society and are widely used in almost all of the electronic systems. Binary digital integrated circuits are the most prevalent computing technology today, because the binary signals exist naturally in semiconductor electronic devices, and binary Boolean Algebra can be easily implemented by using binary logic gates. However, the performance of binary logic is fundamentally limited by its low density of logic states, that is, only two logic levels (0, 1) can be transmitted over a given set of lines [1]. Therefore, it needs a large number of logic gates and transistors to reach the required data size. Besides, even more interconnected wirings between the system components are required in integrated circuits. For example, in a very large scale integrated (VLSI) circuit, approximately 70 percent of the area is devoted to interconnection, 20 percent to insulation, and only 10 percent to device [1–3], which exceedingly increases the complexity, both in design and manufacture. A ternary digit, which is also called as a trit, owns three signiﬁcant values (0, 1, 2), and can represent log2(3) = 1.58 bits [4–6]. Thus, more information can be transmitted over the interconnections,

Appl. Sci. 2019, 9, 4212; doi:10.3390/app9204212 www.mdpi.com/journal/applsci Appl. Sci. 2019, 9, 4212 2 of 13 and less devices are required for a given data length. For instance, a ternary system with a digit size = 19 can represent a data size about 319~1 G. Meanwhile, that of a binary system is only 219~0.5 M. Ternary logic has been widely studied for decades, but is still severely blocked by the fact that the designs of ternary are much more complex than those of binary. In the 1980s, the design of silicon CMOS ternary occurred as a moderate breakthrough, where one p-MOSFET, two resistors and one n-MOSFET were in-series connected [4,5]. Such circuits simplified the design, but it required two passive resistive resistors, and increased the production complexity. More seriously, it largely increased the static power consumption because of the two resistors with relative low resistance. In the 1990s, the carbon nanotube field effect transistor (CNTFET) showed itself to be promising for its ballistic transport, high mobility and low off-current properties [7,8]. And it was then found that the threshold voltage of CNTFET could be well determined by its diameter, which was quite suitable for the ternary threshold logic design [9,10]. Based upon that, many groups have focused their attention on the demonstration of ternary logic gates using multi-threshold CNTFETs [11–15]. In their designs, no passive resistive components were needed, but the simplest ternary NOT gate still needed six CNTFETs, which was much more complicated than that of a classical CMOS binary NOT gate (two FETs). Therefore, both the silicon ternary and CNT ternary are not cost-efficient enough to establish a practical ternary application: It needs four transistors in silicon ternary and six transistors in CNT ternary to process one trit (which equals 1.58 bits) of information. Meanwhile, one can use the same four (or six) transistors to process two (or three) bits of information in binary logic circuits. A recent breakthrough on ternary logic is the demonstration of a ternary NOT gate by using the commercial CMOS processes [16]. But it suffers from the low operation frequency due to the ultra-low current, and the other types of ternary logic functions are still undiscovered. Recently, the emerging two-dimensional (2D) semiconducting materials, such as graphene, transitional metal dichalcogenides (TMDs) and black phosphorus (BP), have attracted enormous attention due to their excellent electronic properties [17–23], and this also opens up new possibilities in logic circuits in terms of both CMOS binary [24,25] and ternary logic design [26–31]. For example, Tomas Palacios et al. [26] presented the first 2D-materials-based standard ternary inverter in 2016. Huang et al. [28] designed and fabricated the novel tunable MoS2/BP-based ternary devices (tuned by the electric field and device channel length). Jin-Hong Park et al. [29] demonstrated the graphene/WSe2-based light triggered ternary device. However, all of these previous works are mainly focused on the demonstration of a standard ternary inverter (STI). To accomplish simplicity in circuit design and increase the data density in practical integrated circuits, further research on ternary logic devices, circuits and algorithms needs to be explored. In this work, we propose to perform a systematical study on the 2D-based ternary logic from individual ternary logic gates to large scale ternary integrated circuits. We will firstly utilize the unique electronic properties of ambipolar BP transistors and N-type MoS2 transistors to build various ternary logic gates. Then we will integrate the as-demonstrated logic gates to design and realize the dyadic ternary operators such as T-NAND, T-NOR and other ternary functions. Finally, we will focus on the design of large scale ternary integrated circuits applications. The decrement cycling inverter and the optimized ternary adder algorithm will be used to design the 19-trit ternary adder.

2. Demonstration of Ternary Logic Gates In conventional binary Boolean Logic, there are a total of 22 = 4 monadic functions. While in ternary logic [6], the number of monadic functions is 33 = 27. These 27 ternary functions are enumerated from 0 to 9 and then A to Z, as shown in Figure1a. Strictly speaking, we do not need all of these functions because there are strong relationships between such operations in Boolean Algebra. Several of them are nontrivial and meaningful [6]. For example, functions 0, D, and Z are the trivial, constant-valued functions; Function P is identity; Function 5 is the standard ternary inverter (STI); Functions 2 and 8 are the negative threshold inverter (NTI) and positive threshold inverter (PTI), respectively; Functions 7 and B are increment cycling inverter (ICI) and decrement cycling inverter Appl. Sci. 2019, 9, 4212 3 of 13

Appl. Sci. 2019, 9, x FOR PEER REVIEW 3 of 13 (DCI), respectively. It is widely accepted that the most important and fundamental components in ternaryternary logiclogic areare STI,STI, NTINTI andand PTI PTI [ 9[9–12].–12]. TheThe output-inputoutput-input characteristiccharacteristic curvescurves ofof suchsuch ternaryternary functionsfunctions have have been been shown shown in in Figure Figure1 b.1b. STISTI isis actuallyactually aa ternaryternary NOTNOT functionfunction thatthat invertsinverts itsits input,input, returningreturning “0”“0” whenwhen givengiven “2”“2” andand vicevice versa,versa, whilewhile leavingleaving “1”“1” inputsinputs unchanged;unchanged; NTINTI invertsinverts thethe inputinput ofof “2”“2” andand “0”“0” asas samesame asas thethe NOTNOT function,function, butbut returnsreturns “0”“0” whenwhen givengiven “0”;“0”; PTIPTI invertsinverts thethe inputinput ofof “2”“2” andand “0”,“0”, butbut returnsreturns “2”“2” whenwhen givengiven “1”.“1”. CyclingCycling ternaryternary (CT)(CT) gatesgates cancan operate operate the the increment increment function function (output (output= =input input+ + 1)1) oror decrementdecrement functionfunction (output(output= = inputinput -- 1),1), whichwhich areare especiallyespecially suitablesuitable forfor thethe ternaryternary ripple-carryripple-carry adder.adder. WhileWhile wewe stillstill do do not not need need both both of of them, them, since since (a (a −1) 1)= =((a ((a+ + 1)1) ++ 1) = −((−aa ++ 1),1), which which means means a − − − adecrement decrement gate gate can can be be achieved achieved by by two two increment increment gates, or by two NOTNOT gatesgates togethertogether withwith oneone incrementincrement gate.gate. Similarly for for the the increment increment gate, gate, it it can can be be achieved achieved by by using using two two decrement decrement gates, gates, or orby by two two NOT NOT gates gates plus plus one one decrement decrement gate gate because because (a (a+ 1)+ 1)= ((a= ((a − 1) −1) 1) =1) −(=−a −( 1).a 1). − − − − −

(a) (b) Logic 0 = GND TERNARY INPUT out Logic 1 = 0.5*Vdd Logic 2 = Vdd 01 2 00 0 0 11 0 0 NTI 2 (NTI) 2 0 0 30 1 0 41 1 0 in 5 (STI) 2 1 0 out T 60 2 0 E 71 2 0 R 8 (PTI) 2 2 0 STI N 90 0 1 A A1 0 1 R B (DCI) 2 0 1 Y C0 1 1 in D1 1 1 out O E2 1 1 U T F0 2 1 PTI P G1 2 1 U H2 2 1 T K0 0 2 M1 0 2 in 3 3 =27 N2 0 2 out P0 1 2 R1 1 2 DCI T2 1 2 V0 2 2 X1 2 2 Z2 2 2 in

Figure 1. (a) List of the 27 ternary operators. (b) Characteristic curves of ideal negative ternary inverter Figure 1. (a) List of the 27 ternary operators. (b) Characteristic curves of ideal negative ternary inverter (NTI), standard ternary inverter (STI), positive ternary inverter (PTI) and decrement cycling inverter (NTI), standard ternary inverter (STI), positive ternary inverter (PTI) and decrement cycling inverter (DCI) from top to down. (DCI) from top to down.

By utilizing the unique electronic properties of ambipolar BP transistors and N-type MoS2 By utilizing the unique electronic properties of ambipolar BP transistors and N-type MoS2 transistors, the above-mentioned ternary logic gates have been successfully designed and fabricated transistors, the above-mentioned ternary logic gates have been successfully designed and fabricated in this work. The specific fabrication process is described as following. Firstly, commercial-available in this work. The specific fabrication process is described as following. Firstly, commercial-available few-layer black phosphorus and MoS2 flakes were mechanically exfoliated onto a silicon substrate with few-layer black phosphorus and MoS2 flakes were mechanically exfoliated onto a silicon substrate a 20 nm HfO2 high-k dielectric layer. Then the flakes were identified under a microscope in a glove with a 20 nm HfO2 high-k dielectric layer. Then the flakes were identified under a microscope in a box, where the oxygen and humidity were always kept below 0.1 ppm. Next, standard electron-beam glove box, where the oxygen and humidity were always kept below 0.1 ppm. Next, standard electron- lithography and electron-beam evaporation of 20 nm/60 nm Ni/Au were used to form the device beam lithography and electron-beam evaporation of 20 nm/60 nm Ni/Au were used to form the structures and metal contacts. After that, the current-voltage performance of the devices was measured device structures and metal contacts. After that, the current-voltage performance of the devices was measured in a probe station under high vacuum. BP FETs and MoS2 FETs with a suitable threshold Appl. Sci. 2019, 9, 4212 4 of 13

in a probe station under high vacuum. BP FETs and MoS2 FETs with a suitable threshold voltage and on-offAppl.ratio, Sci. 2019 as well, 9, x FOR as PEER a high REVIEW mobility, were chosen for the second electron-beam lithography4 of 13 and electron-beam evaporation to fabricate the interconnections. voltage and on-off ratio, as well as a high mobility, were chosen for the second electron-beam Becauselithography the and BP flakeselectron-beam were easily evaporation deteriorated to fabricate in air the conditions, interconnections. great attention should be taken to protect theBecause samples the during BP flakes the were whole easily fabrication. deteriorated The in samples air conditions, should great always attention be kept should in the be glovetaken box, and theto protect time of the exposure samples toduring air in-between the whole fabrication. process steps The shouldsamples beshould minimized. always be kept in the glove Forbox, the and BP-MoS the time2-based of exposure standard to air ternary in-between inverter process (Figure steps2 shoulda,b), unlike be minimized. previous studies of a CMOS inverter basedFor the on BP-MoS a MoS2-based2 n-type standard MOSFET ternary and inverter a BP p-type(Figure 2a, MOSFETb), unlike [ 24previous,25], the studies BP channel of a CMOS here is dividedinverter into twobased regions on a MoS with2 n-type a short MOSFET channel and of 0.1a BPµ mp-type and aMOSFET long channel [24,25], of the 1.8 BPµ m.channel We may here simplyis divided into two regions with a short channel of 0.1 μm and a long channel of 1.8 μm. We may simply name the in-series MoS2 FET plus BP1 FET as Part 1, and the BP2 FET as the Part 2, respectively. Note name the in-series MoS2 FET plus BP1 FET as Part 1, and the BP2 FET as the Part 2, respectively. Note that in our circuit design, the output voltage is always represented as Vout = Vdd*R1/(R1 + R2), where that in our circuit design, the output voltage is always represented as Vout = Vdd*R1/(R1 + R2), where R1 R1 and R2 is the resistance of Part 1 and Part 2, respectively. If the ratio of R1/R2 is constant, then and R2 is the resistance of Part 1 and Part 2, respectively. If the ratio of R1/R2 is constant, then the output the output voltage will also be a constant. Therefore, it will show a middle logic output (“1”) when voltage will also be a constant. Therefore, it will show a middle logic output (“1”) when Vin is middle. Vin isIn middle. addition, In it addition,is easily to itget is the easily other to two get states the other, namely two “highest states, logic namely level” “highest (“2”) and logic “lowest level” logic (“2”) and “lowestlevel” (“0”). logic Thus, level” the(“0”). output Thus, voltage the will output show voltagethree stable will states. show The three NTI stable and PTI states. differ Thefrom NTI STI and PTI dionlyffer when from the STI input only is when middle. the Note input that is R middle.1 and R2 are Note mainly that controlled R1 and R 2byare the mainly BP1 and controlled BP2, and the by the BP1 andMoS BP2,2 resistance and the is almost MoS2 negligibleresistance when is almost input negligibleis middle [19,20]. when Therefore, input is middlewe can tune [19, 20the]. middle Therefore, we canoutput tune logic the middlelevel to outputbe very logichigh for level the toPTI be (Fig veryure high2c) or for very the low PTI for (Figure the NTI2c) (Figure or very 2d) low in our for the NTI (Figuredesign.2 d) in our design.

FigureFigure 2. Demonstration 2. Demonstration of diofﬀ differeerentnt ternary ternary logic logic gates.gates. (a)).. SchematicSchematic view view of ofa BP-MoS a BP-MoS2 standard2 standard ternaryternary inverter. inverter. Vout V-Voutin-Vcharacteristicin characteristic curves curves of the ( (bb)) STI, STI, (c ()c )PTI PTI and and (d () dNTI.) NTI. (e). ( eSchematic). Schematic view view of a BP-MoS2 decrement cycling ternary inverter. (f). Vout-Vin characteristic curves of the DCI. of a BP-MoS2 decrement cycling ternary inverter. (f). Vout-Vin characteristic curves of the DCI. Appl. Sci. 2019, 9, 4212 5 of 13

Furthermore, beneficial from the ambipolar behavior of a BP transistor with high mobility of both hole and electron, we design and fabricate a decrement cycling inverter (DCI) with a quite simple device structure (Figure2e,f). There is only one BP transistor, together with one N-type MoS 2 transistor used for the design of the DCI, which is just the same as a CMOS binary inverter [24,25]. When Vin is low, MoS2 FET is off while BP FET is on, then the output is high (logic “2”); when Vin is middle, MoS2 FET is on while BP FET is off, then output is low (logic “0”); when Vin is further higher, both MoS2 FET and BP FETs are fully turned on as the n-type transistor [23], then there will be a voltage distribution in between the resistance of MoS2 and BP. We will get a middle output if the RMoS2 = RBP on its n-type which forms the third state of the inverter (logic “1”). So far, we have designed and fabricated four types of inverters (STI/NTI/PTI/DCI) by using 2D materials. Compared to the existing silicon ternary [4,5] and CNT ternary [9–15], our design has largely simplified the ternary logic design complexity. There are only two or three FETs involved in one ternary logic gate, which is only about half of that in silicon ternary or CNT ternary. Therefore, it is possible to accomplish simplicity in modern digital design by using ternary logic due to the reduced circuit overhead and chip area.

3. Design of Ternary Logic Circuits

3.1. Functional Ternary Logic Gates The truth table of ternary NOT-AND (NAND) and ternary NOT-OR (NOR) gates are given in Figure3a. The two-input ternary logic functions of T-NAND and T-NOR gates [ 11] are defined by the following two equations: Y = min A, B (1) NAND { } Y = max A, B (2) NOR { } For the T-NAND, it contains two steps of logic operations: Firstly it minimizes the two inputs of A and B, and then outputs the result after a NOT transformation. If the minimum input is “0”, the output is “2”. If the minimum input is “1”, the output is “1”. If the two inputs are all “2”, the output is “0”. The designed circuits are shown in Figure3b, where 4 BP transistors and 2 MoS 2 transistors are involved. According to our pre-demonstrated STI as shown in section II, the parameters of the transistors are designed to be Lch = 0.1 µm for BP1 and BP10,Lch = 1.8 µm for BP2 and BP20 and Lch = 1 µm for the two MoS2 FETs. The core question of T-NAND simulation will be the calculation of the resistance of each part at different input voltage. Here, one important thing which needs to be pointed out is that the effective source voltage Vs of the pull-up part will be Vout, while that of the pull-down part is always Vs = 0. When input of A is “0”, the MoS20 FET is fully turned off, so the output is “2”, no matter what B is; When the input of A is “1”, the BP10 FET plus the MoS20 FET is half turned on, so the output will not be “0” (but it will be “1” or “2”, dependent upon B); When the input of A is “2”, the BP10 FET plus the MoS20 FET is turned on as n-type, so the output is dependent on the input of B (Figure3c). Appl. Sci. 2019, 9, 4212 6 of 13 Appl. Sci. 2019, 9, x FOR PEER REVIEW 6 of 13

(a) (b) (c) Vdd T-NAND input output BP2’ 2 BP2 A = 0

Vout ABTNANDTNOR A B BP1 1 A = 1 MoS2

00 2 2 output BP1’ 01 2 1 0 A = 2 MoS2’ 012 input of B 02 2 0 GND 10 2 1(d) (e) V dd T-NOR 11 1 1 B BP2 2 A = 0 12 1 0 BP2’ 20 2 0 1 A = 1 Vout 21 1 0 A BP1’ BP1 output MoS ’ A = 2 2 MoS2 0 22 0 0 012 GND input of B

Figure 3. (a()a )The The truth truth table table of of2-input 2-input ternary ternary NOT- NOT-ANDAND (NAND) (NAND) and andNOT-OR NOT-OR (NOR) (NOR) gates. gates. The Thedesigned designed circuits circuits (b) and (b) V andout-V Vinout characteristic-Vin characteristic curves curves (c) of the (c) T-NAND of the T-NAND gate. The gate. designed The designed circuits circuits(d) and (Vdout) and-Vin Vcharacteristicout-Vin characteristic curves (e curves) of the ( eT-NOR) of the gate. T-NOR gate.

For thethe T-NOR,T-NOR, it it also also contains contains two-step two-step of of logic logic operations: operations: It maximizesIt maximizes the the two two inputs inputs of A of and A B,and and B, thenand outputsthen outputs the result the result after aafter NOT a transformation.NOT transformation. If the maximumIf the maximum input isinput “2”, theis “2”, output the isoutput “0”. Ifis the“0”. maximum If the maximum input input is “1”, is the “1”, output the output is “1”. is “1”. If the If twothe two inputs inputs are are both both “0”, “0”, the the output output is “2”.is “2”. The The designed designed circuits circuits for for the the T-NOR T-NOR are are shown shown in Figure in Figure3d,where 3d, where four BPfour transistors BP transistors and twoand MoStwo MoS2 transistors2 transistors are involved.are involved. The The transistors’ transistors’ parameters parameters are similarare similar to that to that of a of T-NAND. a T-NAND. When When the inputthe input of A of is A “2”, is “2”, the BP2the BP20 FET′ FET is fully is fully turned turned off, off, so the so outputthe output is “0”, is “0”, no matter no matter what what B is; B When is; When the inputthe input of A of is A “1”, is “1”, the BP2the 0BP2FET′ FET is half is half turned turned on, soon, the so outputthe output will will not benot “2” be (yet“2” (yet it will it will be “0” be or“0” “1”, or dependent“1”, dependent on B); on When B); When the inputthe input of A of is A “0”, is “0”, the the BP2 BP20 FET′ FET is turned is turned on on as aas p-type, a p-type, so so the the output output is dependentis dependent on on B (FigureB (Figure3e). 3e). Ternary AND and and ternary ternary OR OR gates gates are are known known as asthe the minimum minimum and and maximum maximum gates. gates. These These two twogates gates can canbe generated be generated by adding by adding one one ternary ternary NO NOTT gate gate after after T-NAND T-NAND and and T-NOR, T-NOR, respectively. respectively. Therefore, the two-input T-AND gate needs nine FETsFETs (six(six forfor T-NAND andand threethree forfor NOT), and the T-OR gategate alsoalso needsneeds ninenine FETs.FETs. SimilarSimilar designdesign methodsmethods cancan bebe usedused toto implementimplement thethe multi-inputmulti-input T-AND andand T-ORT-OR logiclogic gates.gates. The ternary logic gates presented in Figure4 4a,ba,bcan canbe be used used for for designing designing ternary ternaryarithmetic arithmetic circuits. As As required required for for the the ternary ternary circuits, circuits, a design a design of a ternary of a ternary decoder decoder [9–11] [ 9is– presented11] is presented in Figure in Figure4a. The4a. ternary The ternary decoder decoder is a isone-input, a one-input, three-output three-output combinational combinational circuit, circuit, and and generates unaryunary functions forfor anan inputinput XXkk. The The response response of of the the ternary ternary decoder decoder to to the the input X is given by ( 2 if X= k = 2 i f X = k Xk X=k  (3)(3) 00 i fif X X ≠, kk where kk cancan taketake logiclogic valuesvalues ofof “0”,“0”, “1”“1” oror “2”.“2”. Note that the outputs of the decoder have only two logic valuesvalues (namely “2” and “0”),“0”), correspondingcorresponding to highesthighest logiclogic statestate (“2”)(“2”) andand lowestlowest logiclogic statestate (“0”)(“0”) inin binarybinary logic,logic, therefore,therefore, binary binary OR OR gates gates can can be be used used here. here. A A ternary ternary bu bufferffer is alsois also presented presented in Figurein Figure4a. 4a. The The ternary ternary bu bufferffer contains contains one one DCI DCI and and one one STI. STI. It isIt easyis easy to deduceto deduce that that the the response response of theof the bu ffbufferer is givenis given by by ( 1 i f X = 2 = in = Xout 1 if X in 2 (4) X = 0 i f Xin = 0 out  = (4) 0 if X in 0 Appl. Sci. 2019, 9, 4212 7 of 13 Appl. Sci. 2019, 9, x FOR PEER REVIEW 7 of 13

Figure 4. (a) Design of the ternary decoder and ternary buffer. (b) Symbols of all the ternary logic gates Figure 4. (a) Design of the ternary decoder and ternary buffer. (b) Symbols of all the ternary logic discussed in this work. Note: The unlabeled logic gates represent the normal binary logic gate. gates discussed in this work. Note: The unlabeled logic gates represent the normal binary logic gate. 3.2. Conventional Design of Ternary Adder 3.2. Conventional Design of Ternary Adder Adder is the most important arithmetic logical unit in a microprocessor, because all the mathematicAdder is operators the most and important computations arithmetic can be logica finallyl reducedunit in intoa microprocessor, addition. Ternary because logic decreases all the mathematicthe requirement operators of componentsand computations and interconnections can be finally reduced by realizing into addition. more Ternary data transmission logic decreases over thean requirement interconnection of components wire. Therefore, and itinterconnections is promising in highby realizing speed and more high data effi cienttransmission data processing. over an interconnectionThere are wire. several Therefore, ternary itadders is promising which in have high speed been designedand high efficient in thepublished data processing. literatures, whichThere can are be generallyseveral ternary categorized adders intowhich two have types: been Capacitive-based designed in the andpublished transistors-based literatures, circuits.which canThe be capacitive-based generally categorized design benefitsinto two low types: complexity Capacitive-based and low device and transistors-based count [15], however circuits. it exhibits The capacitive-basedhigh variation sensitivity design benefits and high low area-cost complexity because and low of the device existing count of capacitor.[15], however Most it of exhibits the previous high variationworks focused sensitivity on the and transistor-based high area-cost circuitsbecause where of the various existing logic of capacitor. gates are Most utilized of tothe process previous the worksinput focused and output on the voltage transistor-based information [circuits11–14]. wher In a conventionale various logic wisdom gates designare utilized of a transistor-basedto process the inputternary and ripple-carry output voltage adder, information the two input [11–14]. numbers In a conventional are summed wisdom together design bit by of bit, a transistor-based from the lowest ternaryaddress ripple-carry to the highest adder, address. the two Though input numbers ternary intrinsicallyare summed contains together largerbit by logicbit, from states the densities, lowest addressthe existing to the designs highest ofaddress. the ternary Though adder ternary are not intrin cost-esicallyfficient contains when larger compared logic states to the densities, binary adder. the existingFigure5 designs presents of thethe conventionalternary adder ternary are not half-addercost-efficient design when [ 11compared]. The ternary to the inputbinary A adder. and B Figure signals 5are presents firstly the decoded conventional by the ternaryternary decoderhalf-adder (the de twosign blue[11]. dashedThe ternary box regions).input A and Then B theysignals will are be firstlytransferred decoded to theby nextthe logicternary unit decoder (red dashed (the boxtwo region)blue dashed for computing. box regions). The outputThen they equations will be are transferredgiven by Sum to the= (A2 nextB0 logic+ A1 unitB1 + (redA0 B2)dashed+ 1 (A1 boxB0 region)+ A0 B1for+ computing.A2 B2) and The Carry output= 1 (A2 equationsB1 + A2 areB2 + · · · · · · · · · · givenA1 B2). by NoteSum that= (A2·B0 the output + A1·B1 of + the A0·B2) decoder + 1·(A1·B0 has only + twoA0·B1 logic + A2·B2) values, and i.e., Carry “2” and = 1·(A2·B1 “0”, corresponding + A2·B2 + · A1·B2).to logic Note “1” that and the “0” output in binary of the logic. decoder Therefore, has on binaryly two logic AND values,/OR gates i.e., can“2” beand used “0”, herecorresponding (Note: The tologic logic states “1” and are still “0” named in binary as logic logic. “2” Therefore, and logic binary “0” in thoseAND/OR binary gates logic can gates). be used Finally here the (Note: calculated The logicbinary states results are still will named be re-transferred as logic “2” into and a ternarylogic “0” signal in those as the binary output. logic Two gates). ternary Finally buff theers calculated are needed binaryhere, oneresults for thewill sum1 be re-transferred result (A1 B0 + intoA0 B1a tern+ A2aryB2) signal and the as otherthe output. one for theTwo carry ternary (A2 B1buffers+ A2 areB2 + · · · · · neededA1 B2), here, because one thefor binarythe sum1 signal result of sum1(A1·B0 and + A0·B1 carry + can A2·B2) only and be “0” the or other “1”, one and for will the never carry be (A2·B1 “2”. + A2·B2· + A1·B2), because the binary signal of sum1 and carry can only be “0” or “1”, and will never be “2”. Appl. Sci. 2019, 9, 4212 8 of 13

Appl. Sci. 2019, 9, x FOR PEER REVIEW 8 of 13

Figure 5.5.Conventional Conventional design design of ternaryof ternary half-adder. half-adder. The ternaryThe ternary input (inputA, B) signals(A, B) aresignals ﬁrstly are decoded firstly bydecoded the ternary by the decoder ternary (thedecoder two (the blue two dashed blue boxdash regions).ed box regions). Then the Then signals the signals are transferred are transferred to the logicto the computation logic computation unit (red unit dashed (red dashed box region). box region Finally). Finally the calculated the calculated results results are re-transferred are re-transferred to be ato ternary be a ternary signal signal (green (green dashed dashed box region) box region) as output. as output. Note: Note: The unlabeledThe unlabe logicled logic gates gates represent represent the normalthe normal binary binary logic logic gate. gate.

Such ternary adder design has largely increased thethe circuitrycircuitry complexitycomplexity becausebecause itit avoidedavoided the advantages of ternary logic. In fact, the main co computationmputation part is indeed made of binary logic gates. ItIt hashas alsoalso largelylargely increasedincreased thethe requiredrequired transistors.transistors. For instance, a silicon-based, ternary half-adder requiresrequires 114 transistors and a a 1-trit 1-trit full-adder full-adder requ requiresires more more than than 200 200 transistors transistors [5]. [5]. Meanwhile, Meanwhile, a aclassical classical silicon silicon CMOS CMOS binary binary only only requires requires 28 28 tran transistorssistors for for the the half-adder, half-adder, and 62 transistors for thethe 1-bit full-adder. To To simplify simplify the the circuit circuit design design an andd reduce reduce the the required required transistors, transistors, we we develop develop a amixed mixed ternary-binary ternary-binary computation computation system system where where ternary ternary cycling cycling gates gates and and the improved ternaryternary adder algorithmalgorithm areare used.used.

3.3. Our Optimized Design of Ternary AdderAdder Firstly, forfor thethe ternaryternary cyclingcycling gates,gates, asas we have discussed before, they can operate the increment functionfunction (output(output == input + 1) or decrement function (output(output == input − 1)1) which which are especially suitable − forfor thethe ternaryternary adder.adder. However, itit requiresrequires moremore thanthan 2020 extraextra transistorstransistors toto buildbuild suchsuch aa cyclingcycling gategate inin thethe currentcurrent existingexisting ternaryternary technologytechnology [[11],11], thereforetherefore itit isis notnot cost-ecost-efficientﬃcient toto bebe appliedapplied intointo thethe ternaryternary adder.adder. Whereas, inin ourour design,design, wewe cancan generategenerate thethe ternaryternary decrement cyclingcycling logiclogic functionfunction by using only two transistors,transistors, asas discusseddiscussed inin FigureFigure2 2e.e.Hence Hencethe the DCIDCI cancan bebe usedused inin thethe half-adderhalf-adder toto replacereplace thethe originaloriginal requiredrequired ANDAND gates,gates, asas shownshown inin FigureFigure6 6a.a. TheThe redred dasheddashed boxbox presentspresents ourour ternaryternary computationcomputation method. method. If If the the input input A A= =0, 0, the the sum sum of of A A+ +B B is is B. B. If If the the input input A A= 1,= 1, the the sum sum of of A +AB + isB Bis+ B1 + which 1 which needs needs one one ICI ICI gate gate (or (or two two DCI DCI gates). gates). If the If inputthe input A = A2, = the 2, sumthe sum of A of+ AB is+ B +is 2B =+ B2 = B1 which− 1 which needs needs only only one one DCI DCI gate. gate. The The calculated calculat resultsed results are controlled are controlled by the by transmission the transmission gate − (1gate enhancement-mode (1 enhancement-mode N-type N-type transistor) transistor) and summarized and summarized in a ternary in a ternary OR gate. OR gate. Appl. Sci. 2019, 9, 4212 9 of 13 Appl. Sci. 2019, 9, x FOR PEER REVIEW 9 of 13

FigureFigure 6. 6.( a()a Ternary) Ternary half-adder half-adder Design Design 1, with 1, thewith cycling the DCIcycling gate DCI as the gate computation as the computation part. (b) Ternary part. half-adder(b) Ternary Design half-adder 2, with Design the improved 2, with the ternary improved adder ternary algorithm, adder that algorithm, the carry ofthat the the ternary carry adderof the canternary only adder be logic can “0” only or logicbe logic “1”. “0” (c) or Truth logic tables “1”. ( ofc) theTruth half tables adder. of the half adder.

Next,Next, notenote that the logic state state of of carry carry in in the the ternary ternary adder adder (Figure (Figure 6c)6c) can can only only be be“0” “0” or “1”. or “1”. For Forexample, example, the thecarry carry of 0 of + 00,+ 00, + 01,+ 0 1,+ 02 +and2 and1 + 1 is+ 1“0”, is “0”,and andonly only the thecarry carry of 1 of+ 12 +or2 2 or+ 2 +is 2“1”. is “1”.Therefore, Therefore, it is it not is not necessary necessary to touse use the the full full ternary ternary decoder. decoder. The The improved improved ternary half adderadder isis presentedpresented in in Figure Figure6b. 6b. When When C C is is “0”, “0”, the the sum sum is A;is A; when when C isC“1”, is “1”, the the sum sum is A is +A1. + While1. While the the carry carry is alwaysis always C1 C1+ A2. + A2. Finally,Finally, the the two two as-designed as-designed half-adders half-adders can can be combined be combined into ainto 1-trit a ternary1-trit ternary full-adder, full-adder, as shown as inshown Figure in7a. Figure The operating 7a. The operating principle canprinciple be explained can be as explained follows: Stepas follows: 1, the input Step A1,and the Binput are summed A and B upare in summed the half-adder up in the 1 (blue half-adder dashed 1 box)(blue and dashed they thenbox) generateand they thethen result generate of AB_sum the result and of AB_carry. AB_sum Stepand 2,AB_carry. the AB_sum Step and2, the the AB_sum input carry and the of Cinputin are carry summed of Cin up are in summed the half-adder up in the 2 (red half-adder dashed 2 box). (red Thedashed generated box). resultThe generated of SUM will result be the of ﬁnal SUM summation will be ofthe A, final B and summation Cin. Step 3, theof twoA, B generated and Cin. carryStep 3, trits, the AB_carrytwo generated from thecarry half-adder trits, AB_carry 1 and from ABC_carry the half-adder from the 1 half-adderand ABC_carry 2, will from be sent the intohalf- anadder OR gate,2, will and be willsent generate into an OR the gate, ﬁnal CARRY,and will whichgenerate will the be final a new CARRY, Cin to the which next will series be of a full-adder.new Cin to the nextIn Figure series7 b,of wefull-adder. present the design block diagram of the 19-trit ripple-carry adder, in which A18A17 ... A1A0 is a ternary number of A input, B18B17 ... B1B0 is a ternary number of B input, Appl. Sci. 2019, 9, x FOR PEER REVIEW 10 of 13

Appl. Sci. 2019, 9, 4212 10 of 13 In Figure 7b, we present the design block diagram of the 19-trit ripple-carry adder, in which A18A17…A1A0 is a ternary number of A input, B18B17…B1B0 is a ternary number of B input, S18S17S18S17…S1S0... S1S0 is is the the output output summation summation result, result, C18C17…C1 C18C17 ... C1 is the is the Carry, Carry, C0 C0 is always is always 0 and 0 and Cout C isout theis theoverflow overﬂow bit. bit.

FigureFigure 7.7.( a()a Design) Design of 1-tritof 1-trit full-adder. full-adder. (b) Schematic (b) Schematic diagram diagram of the 19-trit of the ternary 19-trit adder. ternary A18A17 adder.... A1A0A18A17…A1A0 and B18B17 and... B18B17…B1B0B1B0 is ternary is number ternary ofnumber A and of B, respectively.A and B, respectively. S18S17 ... S18S17…S1S0S1S0 is the output is the summationoutput summation result, C18C17 result, C18C17…C1... C1 is the Carryis the andCarry the and ﬁrst the input first carryinputof carry C0 isof 0. C0 is 0.

ByBy takingtaking advantageadvantage ofof thethe ternaryternary cyclingcycling inverterinverter andand thethe improvedimproved ternaryternary adderadder algorithm,algorithm, wewe presentpresent aa mixedmixed ternary-binaryternary-binary systemsystem wherewhere ternaryternary gatesgates areare usedused forfor thethe calculationcalculation ofof SUM,SUM, andand binarybinary gatesgates areare usedused forfor thethe CARRY.CARRY. SuchSuch designdesign hashas largelylargely decreaseddecreased thethe requiredrequired numbernumber ofof transistors,transistors, inin whichwhich therethere areare onlyonly 72,72, andand 2525 transistorstransistors areare involvedinvolved inin half-adderhalf-adder 11 andand half-adderhalf-adder 2,2, respectively. The The total total number number of of transistors transistors in ina full-ternary-adder a full-ternary-adder is 99, is which 99, which is much is much lower lower than thanthat thatof the of theexisting existing ternary ternary circ circuits.uits. The The detailed detailed comparison comparison result result can can be be seen seen in in Table1 1.. MoreMore importantly,importantly, comparedcompared toto thethe classicalclassical CMOSCMOS binarybinary adder,adder, ourour designdesign showsshows aa 7%7% reductionreduction inin thethe numbernumber ofof requiredrequired transistorstransistors atat thethe samesame datadata throughput.throughput. AnotherAnother importantimportant parameterparameter isis thethe computationcomputation step,step, whichwhich hashas aa directdirect impactimpact onon thethe computationcomputation speed.speed. For the CMOS binary adder, thethe propagationpropagation delaydelay ofof thethe logicallogical gatesgates inin aa 1-bit1-bit fullfull binarybinary adderadder isis 1010 (note(note thatthat oneone ANDAND gategate oror OROR gategate requiresrequires twotwo timestimes ofof gategate delay).delay). Therefore,Therefore, thethe totaltotal computationcomputation stepssteps forfor aa 30-bit30-bit binarybinary adderadder isis 10*3010*30= = 300. While that of our ternary ripple-carryripple-carry adderadder isis onlyonly 12*1912*19= = 228.228. In consideration ofof thethe data data throughput, throughput, the the normalized normalized required requir computationed computation steps insteps our designin our show design a 30% show reduction a 30% comparedreduction tocompared the binary to design.the binary design.

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Table 1. Comparison table of diﬀerent ternary circuit designs. (Note: The number in the table should be the less, the better.).

CMOS Binary CMOS Ternary CNT Ternary Circuits 2D Ternary Circuits ref.5 ref.11 ref.12 ref.15 (This Work) 1.capacitive 1. Decoder circuits 2. Ternary logic XOR, AND, Decoder Binary Decoder Binary Transistor Circuit structures 2.decoder gates OR gates logic gates logic gates networks 3.transistor 3. Binary logic networks gates Optimized Optimized Classical Optimized design with design with design design with Classical Classical capacitors. ternary gate. Description networks. design design Similar to High speed and Reduced circuits CMOS ternary Reduced delay energy-eﬃcient area design1: 72 number of FETs in half adder 28 114 118 - - design2: 25 2 capacitors2 number of FETs in full adder 62 234 242 114 decoders44 99 transistors computation steps per bit/trit 10 22 22 - - 12 serial levels 30 19 19 19 19 19 ~1G data size number of FETs 62 30 = 1860 234 19 = 4446 242 19 = 4598 114 19 = 2166 - 99 19 = 1881 × × × × × computation steps 300 418 418 - - 228 Normalized required computation steps 100% 129% 129% - - 70% Normalized required transistors 100% 221% 228% 107% - 93%

4. Conclusions In summary, we perform a systematical study on the 2D-materials-based ternary logic from individual ternary logic gates to large scale integrated circuits. We design and fabricate various ternary logic gates with diﬀerent logic functions, which show good ternary performance with simpliﬁed circuital structure compared to traditional silicon ternary and CNT ternary. Then by developing the ternary cycling gate and the improved ternary adder algorithm, we propose a 19-trit ternary adder design with great circuitry simplicity. The design shows about a 50% reduction in the required number of transistors compared to the existing CNT ternary and silicon ternary, and it also shows itself competitive to the classic CMOS binary design with potential reduction in the number of required transistors and computation steps at the same data throughput. This work shows the potential for ternary logic in future integrated circuits application with higher data density, smaller chip area, faster computation speed and less latency.

Author Contributions: Conceptualization, B.T.; methodology, M.H.; validation, M.H., X.W. and G.Z.; data curation, M.H.; writing—original draft preparation, M.H.; writing—review and editing, X.W., M.H., G.Z., P.C. and B.T.; supervision, B.T. and P.C. Funding: This work was supported by Ministry of Education, Singapore (Grant No.: MOE2015-T2-2-043, MOE2017-T1-002-200). Conﬂicts of Interest: The authors declare no conﬂict of interest.

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