University of Cincinnati

UNIVERSITY OF CINCINNATI

Date:______

I, ______, hereby submit this work as part of the requirements for the degree of: in:

It is entitled:

This work and its defense approved by:

Chair: ______

Automated Layout-Inclusive Synthesis of Analog Circuits using Symbolic Performance Models

A dissertation submitted to the

Division of Research and Advanced Studies of the University of Cincinnati

in partial fulﬁllment of the requirements for the degree of

DOCTOR OF PHILOSOPHY

in the Department of Electrical and Computer Engineering and Computer Science of the College of Engineering

2005

MUKESH RANJAN

B.E. Electrical Engineering S.V. National Institute of Technology, Surat, India, 2000

Thesis Advisor and Committee Chair: Dr. Ranga Vemuri Abstract

A key task in the automated design of analog/RF circuits is circuit sizing, a process that involves assigning numerical values to unknown circuit parameters of a fixed topology, while being subjected to a set of performance constraints. Over the years, the terms sizing and synthesis have been used interchangeably, and have become synonymous in the analog domain. Mature tools for the synthesis of digital circuits are abundant, but the market for analog synthesis tools is still growing and very few commercial products exist. Several techniques have been developed in the past for analog synthesis, ranging from knowledge-based methods to techniques using numerical simulation. A frequently used technique involves an iterative stochastic search, which uses numerical simulations at every probable design point, in order to obtain the performance metrics. Expensive computations and parasitics unawareness of this traditional method necessitates a scheme which can produce fast layout aware designs. In this dissertation a new synthesis methodology, which uses parameterized layout generators and symbolic performance models (SPMs) inside the synthesis loop, has been developed to overcome the deficiencies of the previous circuit sizing method. This layout-inclusive (layout- in-loop) approach uses efficient parameterized procedural layout generators, obtained using the module-specification language (MSL) system, for speedy layout instantiation. Fast performance estimation is achieved by using pre-compiled SPMs, which are symbolic representation of circuit performances, obtained using symbolic analysis. The transfer functions of SPMs are stored as efficient symbolic graphs called element-coefficient diagrams (ECDs). Techniques to include layout geometry effects in the SPMs have also been developed. This method is used for the synthesis of opamps and filters. The method proposed above for analog circuits is then applied to the synthesis of an RF low-noise amplifier (LNA). This method also uses symbolic performance models (SPMs), and parameterized layout generator along with high-frequency extraction techniques in the synthesis loop. SPMs for noise figure and distortion parameters are developed using repetitive and weakly nonlinear symbolic analysis and are stored as pre-compiled ECDs. Full parasitic extraction is done by using multiple extractors. Quasi-static extraction is used to obtain the critical parasitic effects of interconnects and on-chip inductors. Further in the dissertation, efforts are made to overcome the shortcomings of the proposed method. The first limitation is the size of circuits that can be synthesized. It arises because of the limit on the size of ECD-code that can be compiled by a standard GNU C++ compiler. To overcome this bottleneck, a new comprehensive method and framework for exact symbolic analysis of large analog circuits is developed. The method is based on the concepts of hierarchical circuit decomposition, subcircuit symbolic analysis and transfer function synthesis. Node tearing methods have been used for decomposition and element-coefficient diagrams (ECD) based method is used for symbolic analysis of subcircuits. One of the key contributions of this work is a generalized methodology for transfer function synthesis, encompassing all interconnection templates for any two subcircuits. The method leads to the development of an easily automatable and efficient algorithm for generation of symbolic transfer function of large circuits. The hierarchical technique, developed in this work, is then used for layout-inclusive synthesis of large analog circuits. Techniques have been developed to generate the list and interconnection of subcircuits which undergo hierarchical symbolic analysis. A circuit is decomposed into common building blocks of analog circuits, for which netlists are obtained by an extraction of corresponding layout modules. The interconnection parasitics may or may not exist in the module netlists and therefore they may form subcircuits of their own. The other shortcoming of this work is that of time during performance estimation is spent on operating point analysis using SPICE, a numerical simulator. To remove this dependence on numerical simulation and further speedup synthesis, we have developed a modified gm/ID method and used it for synthesis of analog circuits. EKV MOSFET model equations for all small-signal parameters, have been extracted, and the conditions for a transistor to be in saturation, have been derived.

To My Parents Asha & Sureshwar Pandey Acknowledgements

I would like to express my deepest gratitude and sincerest thanks to Dr.Ranga Vemuri for his guidance and support throughout my PhD work. I would like to thank Dr. Hal Carter, Dr. Wen-Ben Jone, Dr. Carla Purdy and Dr. Adrian Nunez-Aldana for being a part of my dissertation committee and offering me valuable suggestions. This work was supported in part by the Defense Advanced Research Projects Agency and the Sensors Directorate of the Air Force Research Laboratory, U.S. Air Force, Wright- Patterson AFB, OH, under Contract F33615-01-C-1977, and the National Science Foundation under award number CCF-0429717. I would like to acknowledge their support. I would like to thank Dr Georges Gielen and Wim Verhaegen, Katholieke Universiteit, Leuven, Belgium, for their permission to use the DDKUL software. Their guidance also has been very important in my research. I thank Dr. Andrea Pacelli for the VPEC software suite. I also thank my colleagues Anuradha and Amitava for letting me use their software. My life has been shaped by ideals of my parents, and I thank them for setting such a good example for me to follow. I thank them for all their sacriﬁces, their unwavering support and constant encouragement. I thank all my family members for all the love and care they have showered on me. My life in Cincinnati has been made special by the presence of Varsha. She has been a wonderful companion and my best friend. It is difﬁcult to imagine the completion of my PhD without her support. Finally, I thank all my friends, who have made this stay wonderful - Andy and Bharath, my roommates; Anuradha, Raoul, Hemanth, and Veena, my closest friends and colleagues; Beth, Heather and Matt, for teaching me the ropes of the american culture; DDELites - Mad- hubanti, Jawad, Vijay, Glenn, Amitava, Vipul, Manish, Ritochit, Shubhankar, Huiying, Meng- meng, Xin, Bala, Akhil, Prasun, Harish, Renqui, Vikas, Shyam, Jayanthi, Siva, Sairavi, Sunder, Srinivas, Rajesh, Elena, Iyad, Sree; AIDers - DC, Senthil, Mahesh, Sri; SACUBers - Rishi and Jim, and 310-ers - Nitin, Arjun, Jill, Alex, Joshi, Nawab, Shagun, Ashima, Anurag, Dilip, Aditi, Anand, Dhananjay, Avinash, Rama, Manish, Anshul. Thank you all. Contents

List of Figures v

List of Tables vii

1 Introduction 1 1.1 Analog/Mixed-Signal Design ...... 2 1.2 Analog Circuit Synthesis: An Overview ...... 3 1.3 Issues with Analog Synthesis and Related Work ...... 6 1.3.1 Performance Evaluation ...... 6 1.3.2 Parasitic Closure ...... 6 1.4 Research Overview ...... 8 1.4.1 Symbolic Performance Modeling ...... 8 1.4.2 Parasitic-Inclusive Topology Generation ...... 9 1.4.3 Layout-Inclusive Synthesis using Symbolic Performance Models . . . . 10 1.4.4 Hierarchical Symbolic Analysis and Performance Modeling ...... 10 1.4.5 Solution to the Operating Point and Use in Synthesis ...... 11 1.5 Dissertation Outline ...... 12

2 Layout-Aware Analog Circuit Synthesis 14 2.1 Introduction ...... 14 2.1.1 Parasitic-Aware Circuit Synthesis ...... 14 2.1.2 Layout-Inclusive Circuit Synthesis ...... 15 2.2 Related Work ...... 16 2.3 Layout-Inclusive Synthesis using Numerical Simulations ...... 17 2.4 Circuit Sizer ...... 18 2.4.1 Optimization Engine ...... 20 2.5 Layout Generation and Instantiation ...... 20 2.5.1 MSL Program Structure ...... 21 2.6 Layout Extraction ...... 24

i 2.7 Summary ...... 26

3 Symbolic Analysis based Performance Modeling 27 3.1 Introduction ...... 27 3.1.1 Symbolic Analysis ...... 27 3.1.2 Symbolic Analyzers vs. Numerical Analyzers ...... 28 3.2 Symbolic Analysis Techniques ...... 29 3.3 Hierarchical Symbolic Analysis ...... 32 3.3.1 Circuit-level hierarchy ...... 32 3.3.2 Expression-level hierarchy ...... 32 3.4 Symbolic Performance Model Generation ...... 32 3.4.1 Determinant Decision Diagrams ...... 35 3.4.2 Element-based Coefﬁcient Diagrams ...... 35 3.4.3 Compilation and Evaluation of ECDs ...... 37 3.4.4 Accuracy of Symbolic Performance Models ...... 39 3.5 Summary ...... 39

4 Layout-Inclusive Analog Synthesis using Symbolic Performance Models 40 4.1 Proposed Circuit Synthesis Approach ...... 40 4.1.1 Layout Generation and Instantiation ...... 41 4.1.2 Symbolic Performance Modeling ...... 41 4.2 Inclusion of Layout Effects in Symbolic performance Models ...... 42 4.2.1 Inclusion of Layout Parasitic Elements ...... 43 4.2.2 General Inclusion of Fingered Transistor Effects ...... 50 4.3 Experimental Results ...... 51 4.4 Conclusions ...... 52

5 RF Low Noise Ampliﬁer Synthesis 54 5.1 Proposed RF Circuit Synthesis Method ...... 55 5.1.1 Layout Generation and Instantiation ...... 55 5.1.2 Multi-way Layout Extraction ...... 56 5.1.3 Post Processing of Extracted Netlists ...... 57 5.1.4 High-Frequency Symbolic Performance Models ...... 58 5.2 Inclusion of Layout Effects in SPMs ...... 60 5.3 Experimental Results ...... 62 5.3.1 Setup ...... 62 5.3.2 Results and Discussion ...... 63 5.4 Conclusions ...... 64

ii 6 Exact Hierarchical Symbolic Analysis of Large Analog Circuits 65 6.1 Introduction & Related Work ...... 65 6.2 General Interconnection Template (GIT) ...... 67 6.2.1 Subcircuit Characterization ...... 67 6.2.2 GIT Transfer Function Synthesis ...... 69 6.3 Proposed Hierarchical Symbolic Analysis Method ...... 75 6.3.1 Subcircuit TF-Matrix Extraction ...... 75 6.3.2 TF-Synthesis ...... 77 6.3.3 Subcircuit Symbolic Analysis ...... 78 6.3.4 Implementation Framework ...... 78 6.3.5 Illustrative Example: Differential Ampliﬁer ...... 80 6.4 Experimental Results ...... 82 6.5 Conclusion ...... 89

7 Synthesis using Hierarchical Performance Models 91 7.1 Parasitic-Inclusive Generation: Analysis of the Layout-Template ...... 91 7.2 Hierarchical Symbolic Analysis ...... 96 7.2.1 Module-Based Partitioning ...... 96 7.2.2 Partitioning Algorithm Based/ Manual Approach ...... 97 7.3 Symbolic Performance Modeling ...... 98 7.4 Layout-Inclusive Synthesis ...... 98 7.5 Experimental Results ...... 99 7.6 Conclusions ...... 102

8 Solution for the DC Operating Point 103 8.1 Related Work ...... 104 8.1.1 DC Operating Point Analysis in SPICE ...... 104 8.1.2 Operating Point Driven Method ...... 105 8.1.3 Relaxed DC Formulation Approach ...... 106

8.1.4 The gm/ID Method and Inversion Coefﬁcient Approach ...... 107 8.1.5 Discussion ...... 107 8.2 The State of MOSFET Modeling for Analog CAD ...... 108 8.3 The Enz-Krummenacher-Vittoz (EKV) MOSFET Model [27, 13] ...... 109 8.3.1 Salient Features ...... 109 8.3.2 Drain Current and MOS Inversion Coefﬁcient ...... 110 8.3.3 Large-Signal Interpolation Function and Intrinsic Voltages ...... 111 8.3.4 Small-Signal Parameters ...... 112

iii 8.4 The Universal gm/ID vs IN Curve ...... 114 8.5 Conditions for Forward Saturation ...... 115

8.6 Synthesis Approach based on Modified gm/ID Method ...... 116 8.7 Experimental Setup and Results ...... 119 8.7.1 Twostage Operational Amplifier ...... 119 8.7.2 Miller-Compensated Operational Transconductance Amplifier . . . . . 121 8.7.3 Results and Discussion ...... 122 8.8 Discussion on Possible Improvements ...... 125 8.9 Future Application to Layout-Inclusive Synthesis ...... 126 8.10 Conclusions ...... 127

9 Conclusions and Future Work 129 9.1 Contributions ...... 130 9.2 Directions for Future Work ...... 132

Bibliography 135

iv List of Figures

1.1 Optimization-based Circuit Sizing Approach using a Simulator ...... 4 1.2 Circuit Sizing using Symbolic Performance Models ...... 9

2.1 Parasitic-Aware Analog Circuit Synthesis ...... 15 2.2 Layout-Inclusive Analog Circuit Synthesis ...... 16 2.3 Layout-Inclusive Analog Circuit Synthesis ...... 18 2.4 Layout Generation and Instantiation Method ...... 21 2.5 Transistor Module with Fingers ...... 22 2.6 Capacitance Extraction in Magic ...... 25 2.7 Resistance Extraction in Magic ...... 25

3.1 Symbolic Performance Model Generation ...... 33 3.2 Common-Source Stage with Passive Load ...... 35 3.3 Determinant Decision Diagram for CS Stage ...... 36 3.4 Element-based Coefﬁcient Diagram for CS Stage ...... 37 3.5 Comparison of Symbolic and Numeric Gain Responses ...... 38 3.6 Comparison of Symbolic and Numeric Phase Responses ...... 39

4.1 Proposed Approach ...... 41 4.2 Transistor Modules ...... 44 4.3 Twostage OpAmp I ...... 47 4.4 Single-ended OpAmp ...... 48 4.5 Low Pass Filter ...... 49

4.6 Accuracy of the Hierarchical Approach (A) Gain of TF u41(B) Phase of TF u41 49 4.7 An Example of Inclusion of Parasitic Resistances ...... 50 4.8 General Inclusion of Parasitic Resistances ...... 51

5.1 Proposed RF Synthesis Approach ...... 56 5.2 PEEC Model ...... 60 5.3 Illustration of parasitic extraction ...... 60

v 5.4 Illustration of parasitic inclusion in SPMs ...... 61 5.5 Larger example of a parasitic model ...... 62 5.6 Low Noise Ampliﬁer Topology ...... 62 5.7 Layout of the Single-ended LNA ...... 63

6.1 (a) Subcircuit (b) Compact Representation ...... 68 6.2 Internal External Variables ...... 69 6.3 General Interconnection Template ...... 70 6.4 Hierarchical Analysis ...... 76 6.5 Circuit Function Synthesis of an RC Ladder ...... 76 6.6 Implementation Framework ...... 79 6.7 Differential Ampliﬁer and Module Subcircuits ...... 80 6.8 Block Diagram of DiffAmp & Hierarchy Tree Traversal ...... 81

6.9 Accuracy of the Hierarchical Approach (A) Gain of TF u41(B) Phase of TF u41 82

6.10 Accuracy of the Hierarchical Approach (A) Gain of TF z44(B) Phase of TF z44 82 6.11 GIT Analysis Results ...... 83 6.12 Memory Usage Trend ...... 84 6.13 Time Results ...... 85 6.14 (A) Rail to rail operational ampliﬁer (B) Hierarchy ...... 87 6.15 Differential Operational Ampliﬁer ...... 88

7.1 Differential Pair with Active Current Mirror and Realistic Current Source . . . 92 7.2 Circuit Layout Template ...... 94 7.3 Block Diagram for Parasitic Capacitance-Inclusive Circuit ...... 95 7.4 Block Diagram for Parasitic Resistance and Capacitance-Inclusive Circuit . . . 96 7.5 Module-based Analysis of Parasitic Capacitance-Inclusive Circuit ...... 97 7.6 Partitioning-based Analysis of Parasitic Capacitance-Inclusive Circuit . . . . . 98 7.7 Differential Operational Ampliﬁer ...... 99

8.1 Stages of Circuit Analysis ...... 103 8.2 Transconductance Efficiency vs Normalized Current (NMOS) ...... 114 8.3 Transconductance Efficiency vs Normalized Current (PMOS) ...... 115 8.4 Synthesis Methodology ...... 117 8.5 Twostage Op Amp ...... 120 8.6 Miller Compensated OTA ...... 122 8.7 Saturation/Non-Saturation Iteration Counts ...... 127 8.8 Transconductance Efficiency vs Inversion Coefficient (NMOS) ...... 128 8.9 Transconductance Efficiency vs Inversion Coefficient (PMOS) ...... 128

vi List of Tables

2.1 An Example of a Performance Speciﬁcation File for the Sizer ...... 19 2.2 An Example of a Search Range Speciﬁcation File for the Sizer ...... 19

4.1 Comparison of Parasitic Capacitances Inclusion Techniques: Part I ...... 46 4.2 Comparison of Parasitic Capacitances Inclusion Techniques: Part II ...... 46 4.3 Time Comparisons for Parasitic Capacitances Inclusion Techniques ...... 46 4.4 Layout-Inclusive Circuit Synthesis Results ...... 52 4.5 Time Results of Layout-Inclusive Circuit Synthesis ...... 53

5.1 Synthesis Results for Low-Noise Ampliﬁer ...... 63

6.1 Results of Flat Symbolic Analysis of Large Networks ...... 85 6.2 Results of Hierarchical Symbolic Analysis of Large Networks: Part I ...... 86 6.3 Results of Hierarchical Symbolic Analysis of Large Networks: Part II . . . . . 86 6.4 Results of Flat Symbolic Analysis of Large Practical Analog Circuits: Part I . . 87 6.5 Results of Flat Symbolic Analysis of Large Practical Analog Circuits: Part II . 89 6.6 Results of Hierarchical Symb. Analysis of Large Practical Analog Circuits: Part I 89 6.7 Results of Hierarchical Symb. Analysis of Large Practical Analog Circuits: Part II 89

7.1 Results of Flat Symbolic Analysis of FDO: Part I ...... 100 7.2 Results of Flat Symbolic Analysis of FDO: Part II ...... 100 7.3 Results of Hierarchical Symbolic Analysis of FDO: Part I ...... 100 7.4 Results of Hierarchical Symbolic Analysis of FDO: Part II ...... 101 7.5 Layout-Inclusive Synthesis Results: FDO PAR - Run #2 ...... 101 7.6 Time Results of Layout-Inclusive Synthesis for FDO PAR ...... 102

8.1 Search Ranges for Primary Design Variables of TSO ...... 119 8.2 Secondary Variables in Terms of the Primary Design Variables for TSO . . . . 120 8.3 Saturation conditions for the Transistors of TSO ...... 121 8.4 Search Ranges for Primary Design Variables of MC-OTA ...... 121

vii 8.5 Secondary Variables in Terms of the Primary Design Variables for MC-OTA . . 122 8.6 Saturation conditions for the Transistors of MC-OTA ...... 123

8.7 Modiﬁed gm/ID Synthesis Results for Twostage Opamp ...... 123 8.8 Synthesis Results for Primary Design Variables of Twostage Op Amp . . . . . 124

8.9 Modiﬁed gm/ID Synthesis Results for MC-OTA ...... 124 8.10 Synthesis Results for Primary Design Variables of MC-OTA ...... 125 8.11 Time Results of Synthesis for TSO & MC-OTA ...... 126

viii Chapter 1

Introduction

Today’s world of extremely high performance electronics, ever-evolving technologies and a customer’s unquenchable thirst, has fostered a spirit of ﬁerce competition in the semicon- ductor industry. As companies try to outdo each other and churn out new products everyday, the pressure is on designers to handle increasingly complex designs in a short period of time. Analog and RF circuits are poised to play a pivotal role in the technological advancement of everyday-use electronic goods. The rise in demand for high performance analog/RF circuits can be attributed to the following factors. In several mixed-signal systems the DSP and digital blocks communicate with outside world through analog circuit as the interface. The real world signals like light, sound, pressure, speed, temperature, humidity etc can only be detected by using Analog/RF circuits. Another application of analog chips is that they are designed to handle higher voltage and currents and are therefore associated with managing power from batteries. Even though analog technology is not featured as prominently as digital, it is as important for the future of cutting- edge electronics. In fact in mixed-signal systems a dollar’s worth of digital components is surrounded by about $1.70 in analog components [1]. On one hand, the design of analog circuits remains a very challenging task, relying heav- ily on the intuitive skills and experience of a designer; on the other, the industry faces a shortage of experienced designers. The arduous task of analog design has been complicated further by increasing design complexity, rising cost of manufacturing and shrinking time-to-market. In mixed-signal systems, very often, the design of analog components takes up signiﬁcantly more time than their digital counterparts, even though they occupy much less area. The aforementioned reasons have created a huge market for analog design automation tools.

1 1.1 Analog/Mixed-Signal Design

This section describes the steps followed in a complex analog/mixed-signal system design from conception to fabrication. Gielen and Rutenbar have divided this process into six distinct stages [42]. These stages are described below. Kundert et al. also provide a detailed survey of the mixed-signal design process and tools in [61].

• Conceptual Design: In this stage a design is conceived along with the specifications. The design is refined and the specifications are verified by talking to customers. A thorough planning of the project is done while considering parameters like time, cost and personnel.

• System Design: The conceptualized system is partitioned into hardware and software parts along with specifications for each part. Each partition is refined into a functional description or an algorithm, which is then elucidated in a suitable description language. Verification is done by using hardware-software co-simulation techniques. Tools like Matlab [59] or SPW (Signal-Processing Worksystem) can also be used at this stage, as they allow a system designer to test various functionalities, algorithms and trade-offs quickly. These tools represent the partitions as block diagrams and have a library of pre- defined blocks for interactive use by the designer. Decisions about fabrication technology and test strategy are also made at this stage.

• Architectural Design: Once the system has been partitioned into various blocks, where each block represents a certain function/algorithm, each block is then mapped to a spe- ciﬁc architecture. Each architecture has functional blocks which realize the behavioral description or the block functionality. In this stage, the blocks and their interfaces are carefully modeled using mixed-signal hardware description languages (MS-HDLs) like, VHDL-AMS or Verilog-AMS. These languages also support mixed-mode simulations.

• Cell Design: Each architectural block may consist of one or more cell-level blocks, each of which are described by a device-level circuit topology. This stage involves distributing the constraints of a block between its different cells, selecting a circuit topology for each cell and ﬁnally sizing each circuit parameter to meet the desired speciﬁcations. In the analog design automation community, assigning numerical values to circuit parameters is referred to as circuit sizing or synthesis.

• Cell Layout: In this stage a cell-level sized circuit schematic is converted to a physical layout, while taking care of area and other constraints. This process is also called phys-

2 ical synthesis. After layout generation, each cell is individually subjected to a parasitics extractor. The result is a circuit schematic which includes all parasitics. The performance of the resulting circuit is verified again by a circuit-level simulator to ensure that all performance specifications met. If the circuit fails on verification, it is re-sized.

• System Layout: This stage involves system-level floor-planning, placement, and routing of all cell-level blocks. Here, routing of power-grids is also done. Shielding and guarding are introduced to prevent cross-talk and substrate coupling. Test circuitry is also added to the system level layout. Once the final layout is obtained, a system-level verification is done.

After the system level layout has been veriﬁed, the chip is fabricated and tested. If at any stage the veriﬁcation step fails, then back-track and redesign strategy is used. From the steps outlined above it is clear that analog/mixed-signal design is very time consum- ing. Hence, the need for tools which automate the process is needed urgently in order to beat the time-to-market pressure. The research presented in this dissertation focusses on automating the stages of cell-design and cell-layout.

1.2 Analog Circuit Synthesis: An Overview

Circuit synthesis is the process of determining the circuit-level implementation of a block from abstract high-level specifications. In the case of digital circuits several commercial tools are available. Digital design is two-dimensional; it makes complex logic sequences out of similar identical transistors that just turn on and off. Whereas, analog design is multi-dimensional because, it uses transistors and other components over the full working range of their physical characteristics, and modifies signals in various ways. This implies that designer has to learn to use the analog process. Therefore automating the design of analog circuits is a much more difficult task. Analog circuit synthesis has made significant strides in the last decade but is still limited by generality of topologies it can handle. The CPU time required to synthesize new circuits is also very high. Traditionally analog circuit synthesis refers to these two steps: Topology selection and circuit sizing. Topology selection is the process of selecting a device-level circuit schematic which is most fit for a meeting a set of performance constraints with minimal implementation cost [42]. The early efforts in this area, selected topologies heuristically from a library of schematics [39, 26, 17]. Later on numerical techniques were developed where each

3 topology was first characterized by feasible performance specifications, and then selection was made by a comparison with the actual specifications [34, 48]. Some attempts were also made to combine the topology selection and the circuit sizing steps by using mixed-integer nonlinear programming [67] or nested simulated annealing [36]. Most of the early works in circuit synthesis focussed on topology selection along with circuit sizing, but the focus now is mostly on circuit sizing, and often the term circuit synthesis implies circuit sizing. Circuit sizing is the process of determining numerical values for unsized circuit elements of a fixed circuit topology, while satisfying a set of performance constraints [42]. The two most prevalent techniques for circuit sizing are: Knowledge-Based Circuit Sizing: In these approaches, design equations and strategies are hard-coded for each circuit that has to be synthesized. This results in extremely fast synthesis but the drawback is that, for each circuit, expert knowledge is required to formulate the design plan. This large setup time ultimately limits the use of such an approach. Some early systems based on this approach are IDAC [32] and OASYS [39]. Optimization-Based Circuit Sizing: Due to limited flexibility of knowledge-based techniques, optimization-based techniques came into being. These techniques use numerical optimization techniques to obtain the numerical values of unsized circuit parameters, while optimizing the performance of the circuit under a given set of constraints. Figure 1.1 illustrates this technique. It can be seen in the figure that each iteration of the sizing loop requires a performance evaluation step. Performance evaluation of any analog circuit can be done using two approaches:

Figure 1.1: Optimization-based Circuit Sizing Approach using a Simulator

4 • Simulation-Based Techniques: In most circuit sizing approaches, a numerical simulator like SPICE is used. This approach is already shown in Figure 1.1. Circuit synthesis systems like DELIGHT.SPICE [72] and FRIDGE [29] use SPICE in the synthesis loop for performance verification. Both of the aforementioned techniques are limited in the number of parameters optimized and have large run times. A mixed equation-simulation approach is used in ASTRX/OBLX [73], along with simulated annealing for optimization. The linear characteristics are obtained quickly by asymptotic waveform evaluation (AWE), and other parameters are obtained by using SPICE. More efficient optimization algorithms like parallel processing, and full SPICE simulations, form the backbone of systems like ANACONDA [76] and MAELSTROM [60]. One of the challenges of using a simulation based approach is the large performance evaluation time in each iteration. A cumulative effect of this is the large run time for the entire synthesis process. However, the use of simulators offer the flexibility of synthesizing any kind of topology for any kind of performance specification.

• Equation/Model-Based Techniques: This circuit sizing technique does not use any numerical simulator for performance estimation. The performance characteristics are obtained either by analytic equations, or macromodels, or symbolic performance models. Some of the earlier works use simple design equations which are derived by hand [17, 49]. The problem with such techniques is that, for each circuit, equations have to be derived by the designer. This implies signiﬁcant setup time, as well as, considerable analog design expertise. To circumvent these problems, tools for automatic generation of characteristic equations were developed, which in turn led to the development of symbolic performance models [43, 86]. The core of symbolic performance modeling is a technique known as symbolic analysis [43]. With symbolic models as the core, several synthesis environ- ments have been developed over the course of years [41, 31, 71]. The advantage of equation/models based approach is that they offer extremely fast evaluation of performances, and as a result faster synthesis.

Neural networks have also been used to model performance characteristics [97]. Neu- ral nets are accurate and fast to evaluate but, the data generation time is signiﬁcant. In [55] it has been shown that, global optimization of opamps can be achieved by convex geometric programming, where the performance equations are modeled as posynomials. The drawback of this technique is that the performance equations are derived by hand and often simpliﬁed. Automatic generation of the posynomial performance models, by using

5 data points generated by SPICE, was done in [21].

1.3 Issues with Analog Synthesis and Related Work

The traditional simulation-based circuit synthesis method suffers from two signiﬁcant shortcomings. The performance of an analog circuit is sensitive to the parasitic effects introduced during the subsequent layout phase. This may lead to the failure of the circuit which is optimized without taking layout effects into account. So, it is imperative to adopt a layout-aware approach so that effective parasitic closure can be achieved. The other drawback is the computationally expensive performance estimation due to the use of numerical simulators inside the synthesis loop. A detailed discussion of these two issues follows.

1.3.1 Performance Evaluation

The issue of performance evaluation can be alleviated by using any of the equation/ model-based circuit sizing techniques mentioned in the previous section. Each of the techniques have pros and cons. Using macromodel based techniques ensures extremely fast performance estimation in the synthesis loop but, the setup time of generating the macromodels is immense. Moreover, most of the macromodels are not accurate over the entire design space. To build globally accurate models the number of data-points required is large, and therefore involves thousands of SPICE simulations. Even though this is a one-time effort, the same process has to be repeated for every new topology/circuit. Another shortcoming of the macromodeling approach is the limit on number of independent circuit parameters that can be handled, often referred to as the curse of dimensionality [97]. The alternative to macromodels is performance modeling based on symbolic equations. It is discussed later in the chapter.

1.3.2 Parasitic Closure

The problem of performance degradation, due to layout parasitics, can be alleviated by either layout-aware or layout-inclusive circuit synthesis. A combination of template-based parasitic estimation and table lookup technique is used for layout-aware circuit synthesis in [28]. The technique works well for intra-module capacitances but, is not reliable for inter-module parasitic capacitances. Moreover, this technique is limited to medium sized circuits since an interpolation technique is used for estimating interconnect parasitics.

6 Onodera et al. [37] propose a layout-aware sizing technique based on procedural layout generators. In this approach, the estimation of parasitic is based on simple formulas, and is limited to wire and diffusion capacitances. A similar parasitic estimation technique is proposed by Dessouky et al. in [23], where a layout language(CAIRO) is used to describe the placement and routing of a circuit. This layout description is used during a synthesis iteration to directly calculate parasitics, without actually generating a physical layout. The technique, even though good for fast layout-aware circuit synthesis, requires that the placement and the whole routing be written in the layout language. Moreover, since the layout-template is fixed, it does not yield optimized layouts. The parasitic estimation is done using the routing information, and therefore requires extraction rules to be specified. The sizing methodology employed in this paper is knowledge-based. Choi et al. [16] proposed a parasitic-aware technique for synthesis of RF Mixers. Only the inductor parasitics were modeled and therefore this technique is very limited; it does not account for other device parasitic as well as interconnect parasitics. From the above methods it is evident that, while layout-aware techniques offer fast timing closure, the parasitics are difficult, and often impossible, to estimate accurately. At this stage layout-inclusive synthesis becomes an intriguing option. In layout-inclusive synthesis, layout generation and extraction are done within the synthesis loop. This method captures the parasitic effects accurately, since layout generation is followed by a full layout extraction. In [33] Vancorenland et al. propose a layout-inclusive RF synthesis approach. The method uses a template-based layout generator, and parasitic capacitance formulae, for parasitic estimation. Performance estimation is done using analytic equations. The template evaluation time is extremely small, which results in very small layout generation and extraction time. So, to summarize, layout-inclusive methods can employ two types of layout generation techniques inside the synthesis loop: optimization-based or template-based. Generation of optimized layouts is computationally expensive, and therefore practically infeasible when repeated in every iteration. Template-based (procedural) layout generators are suitable for the layout-in- loop approach but fail to produce and optimized layout. It is possible to obtain a good quality layout by using constraints on the placement of modules.

7 1.4 Research Overview

The focus of my work is on the development of efficient layout-inclusive analog circuit synthesis techniques using pre-compiled symbolic performance models. Conventional analog circuit sizing is an iterative stochastic search based technique which uses numerical simulations at every probable design point in order to obtain the performance metrics. Expensive computations and parasitics unawareness of these traditional methods necessitates a scheme which can produce fast layout aware designs. Our methodology uses speedy layout-in-loop (i.e., layout-inclusive) techniques and pre-compiled symbolic performance models to remove the aforementioned deficiencies. A number of techniques have been developed to include the layout geometry effects into the symbolic performance models. To generate symbolic performance models for large circuits, a novel hierarchical symbolic analysis has been developed. Techniques also have been also developed for reducing the significant operating analysis time in every iteration. In the following sections, contributions of this dissertation are discussed in details.

1.4.1 Symbolic Performance Modeling

Symbolic performance models (SPMs) are symbolic equations in terms of circuit parameters, which represent the performance characteristics of an analog circuit. In circuit synthesis, SPMs are used for repetitive performance estimation during the optimization iterations. In the initial approach, only a DC operating point analysis and a very quick evaluation of SPMs are done in each iteration. This results in a significant speedup of the performance estimation time compared to a numerical simulator based approach. The SPMs are built using symbolic transfer functions which are obtained by symbolic circuit analysis. The transfer functions are stored as efficient graphs called Element Coefficient Diagrams (ECDs). The ECDs are converted to C++ code and compiled, resulting in an average speedup of the evaluation time by a factor of 32, with respect to ECDs stored in memory. Figure 1.2 shows a circuit sizing approach using symbolic performance models. A symbolic performance modeling framework has been developed, which includes modules like nodes information generator, circuit expander, symbolic analyzer etc. A technique to model noise figure using symbolic analysis has been researched and developed. The technique is extension of a previously used method for spectral noise density. Compiled ECDs have been used to capture the effect of several noise sources ta the output. Symbolic performance models

8 Figure 1.2: Circuit Sizing using Symbolic Performance Models for distortion parameters, based on weakly-nonlinear symbolic analysis, have been used in this work. These models have been integrated to the SPM framework mentioned above and have been modiﬁed to use compiled ECDs. In comparison to numerical circuit simulators (like SPICE), symbolic performance models have a few distinct advantages, which facilitate their use during synthesis of analog circuits. The symbolic performance models remain valid for different values of parameters,i.e.,the entire design space, while the outcome of numerical analysis quantiﬁes this behavior at an isolated point of this space [43]. Hence the evaluation time of performance models is small compared to numerical simulators, since the same performance models are evaluated several time during the search process, instead of doing circuit analysis and numerical simulation in every iteration.

1.4.2 Parasitic-Inclusive Topology Generation

As component sizes vary during synthesis, the layout geometry also varies between iterations. These variation may generate varying sets of parasitic elements (resistances and capacitances) for different iterations. Variation in the width of a transistor module causes the number of ﬁngers to change between iterations, which consequently produce different set of parasitics. All possible parasitics which would ever appear in a synthesis run, have to be original circuit topology used to generate the SPMs. We have developed methods to include these variations in the original circuit topology. Three techniques that have been developed for the inclusion of parasitic capacitances in the

9 SPMs are: complete-set, layout-sampling, and analysis -based. A method for inclusion of parasitic resistances has also been developed. A method has also been proposed to model a transistor as one lumped small-signal model even if it is ﬁngered. For the synthesis of an RF LNA, using SPMs, parasitic-inclusion techniques for interconnects represented by the PEEC Model [6] have been developed. These techniques enable the use of symbolic performance models for circuit synthesis.

1.4.3 Layout-Inclusive Synthesis using Symbolic Performance Models

A novel layout-inclusive synthesis for analog circuits, like opamps and filters, has been developed in this work. The approach uses module-specification language (MSL) system for layout generation and instantiation; MAGIC extractor for layout extraction and symbolic performance models for performance estimation. The optimization engine uses simulated annealing. This synthesis methodology is the first attempt to use symbolic performance models in conjunction with layout-inclusive techniques. This layout-inclusive circuit synthesis method has also been extended to parasitic-inclusive large analog circuits which use hierarchical symbolic performance models, for performance estimation. A synthesis methodology, similar to the one proposed for analog circuits, is developed for low noise amplifier synthesis. The method uses a quasi-static extraction tool, VPEC [8], for interconnect parasitic inductances and resistances. Parasitic capacitances are extracted using a rule-based extractor (MAGIC). This method also uses simulated annealing as the optimization algorithm.

1.4.4 Hierarchical Symbolic Analysis and Performance Modeling

With the inclusion of layout in the sizing loop, the size of circuits which are to be analyzed explode [71]. Even DDD-based methods like element-coefﬁcient diagrams (ECD) [93] cannot handle even moderately large circuits which include parasitics. To overcome this shortcoming hierarchical approaches have to be used. The main hierarchical approach one comes across in literature are DDD-based approach [87], a structural regularity based approach [25] and a network formulation approach [50]. All of these approaches are not conducive for the application mentioned above as they do not utilize the modular property of layouts and hence the parasitic-inclusive circuits. A method where subciruits are combined to yield results for a higher level circuit would be preferable. In [25], a decomposition-based

10 approach is proposed. It breaks down the circuit to the smallest element, which is not desirable for parasitic-inclusive circuit sizing using symbolic performance models. The hierarchical analysis approach presented in this thesis is a generalization of the technique proposed in [24]. The method has three significant steps: circuit decomposition, symbolic analysis of subcircuits and circuit (transfer) function synthesis. The method in [24], fails to develop a concrete mathematical formulation for circuit function synthesis. The core of our algorithm is a novel idea where transfer functions (TF) are synthesized for a general interconnection template (GIT) of two subcircuits. Extremely efficient element-coefficient diagrams (ECD) are used for symbolic analysis of subcircuits. The results of TF-synthesis of a GIT, lead to the development of an easily automatable symbolic analysis method. The efficiency and scope of this method is then demonstrated on few common large analog networks. The method is then used to symbolically analyze large practical analog circuits, with and without parasitics introduced at the layout stage. Another significant contribution of this chapter is the use of pre-generated and pre-compiled subcircuit transfer functions to analyze larger circuits. This paves the way for reusable TF-library based techniques for symbolic analysis.

1.4.5 Solution to the Operating Point and Use in Synthesis

The estimation of any performance metric is done in two stages. The first stage is the operating point analysis; the second is either AC, transient or some other analysis. In the numerical simulator based approach, SPICE, or it’s variant, is used for all types of analysis, including DC operating point (OP) and AC analysis, for estimating performances like DC gain, UGF, phase margin etc. A breakdown of the analysis time shows thats OP analysis takes up 40-70% of the total analyses time, and AC analysis about 30-60%. Therefore, performance evaluation using symbolic performance models can be significantly sped up by replacing the numerical operating point analysis. Approaches like operating point driven technique [64], relaxed DC formulation [74], and the gm/ID method [85, 38](and it’s variants [11, 80, 18]) have been explored. We believe that the gm/ID design technique for analog circuits, is the most suited for application in a synthesis methodology. The existing form of the technique yields solutions (device sizes), which lie off the grid. Since the final goal is to obtain device sizes, which can be used for layouts, a variation of the technique has been developed.

11 The gm/ID method for analog design was modiﬁed, to start with known values of ID and

W/L, instead of gm/ID. Since, W/L is an input parameter, the values of W and L can be chosen in a such a way that they always lie on the layout grid. This modiﬁed method has also been used in the synthesis of analog circuits. EKV MOSFET model equations for all small-signal parameters, which include transconductances and intrinsic capacitances, have been extracted from the model equations presented in [12], [27] and [13]. Conditions which force a transistor in to saturation, have been also derived. These conditions are enforced during synthesis. The resulting designs are robust, since they satisfy the sizing rules presented in [44].

1.5 Dissertation Outline

This dissertation is organized as follows. The concept of layout-inclusive analog circuit synthesis is introduced in Chapter 2. Various layout-aware and layout-in-loop approaches have also been discussed. In this work module specification language (MSL) has been used for layout generation and instantiation. Examples of MSL for layout generation are presented in this chapter. Chapter 3 presents the concepts of symbolic analysis, along with various techniques for analyzing a circuit symbolically. It also introduces the concept of determinant decision diagrams (DDDs) and element-coefficient diagrams (ECDs) which have been used for symbolic performance modeling in this thesis. The technique for symbolic performance modeling using ECDs has also been presented. In Chapter 4, a new methodology for fast analog circuit synthesis, based on the use of parameterized layout generators and symbolic performance models (SPMs) in the synthesis loop is presented. Fast layout generation is achieved by using efficient parameterized procedural layout generators described in Chapter 2. Fast performance estimation is achieved by using pre- compiled SPMs, stored as efficient DDD-like structures called element-coefficient diagrams. Techniques have been developed to include layout geometry effects in the SPMs. The accuracy and efficiency of the parasitic inclusion technique as well as the proposed methodology have been demonstrated by comparisons to traditional synthesis methods. The proposed methodology is used for the synthesis of opamps and filters and is demonstrated to achieve effective performance closure. A layout-in-loop synthesis method for radio-frequency LNAs is presented in Chapter 5. This method uses symbolic performance models, parameterized layout generator and high-

12 frequency extraction techniques in the synthesis loop. SPMs for noise figure and distortion parameters are obtained using repetitive and weakly nonlinear symbolic analysis; these SPMs are stored as pre-compiled element coefficient diagrams. Speedy layout generation is achieved by using parameterized procedural layout generators and full parasitic extraction is done by using multiple extractors. Quasi-static extraction is used to obtain the critical parasitic effects of interconnects and on-chip inductors. Techniques to include parasitics, generated by quasi- static and rule-based extraction, are also developed. The proposed methodology is used for the synthesis of a low noise amplifier. In Chapter 6, a new comprehensive method, and framework, for exact symbolic analysis of large analog circuits is proposed. The method is based on the concepts of hierarchical circuit decomposition, subcircuit symbolic analysis and transfer function synthesis. Node tearing methods have been used for decomposition and element-coefficient diagrams (ECD) based method is used for symbolic analysis of subcircuits. One of the key contributions of this work is a generalized methodology for transfer function synthesis, encompassing all interconnection templates for any two subcircuits. An easily automatable and efficient algorithm for generation of symbolic transfer function of large circuits is also presented. The efficiency and scope of this algorithm has been demonstrated on large circuits. The method has also been used to symbolically analyze analog circuits extracted from layouts. The focus of Chapter 7 is on the generation of layout-aware symbolic performance models (SPMs), for parasitic-inclusive large analog circuits, by using exact hierarchical symbolic analysis presented in the previous chapter. The generation and partitioning of circuit topologies, which includes all parasitics generated in a synthesis run, is shown. We propose efficient techniques for parasitic-inclusive topology generation and partitioning. In this chapter we also use the hierarchical SPMs in layout-inclusive synthesis of a large analog circuit, to overcome important deficiencies in traditional analog synthesis. The accuracy and effectiveness of these SPMs has also been demonstrated.

In Chapter 8, a modiﬁed gm/ID method is presented, and it is used in a synthesis approach along with symbolic performance models. The small-signal parameters like transconductances and intrinsic capacitances are obtained from gm/ID vs IN characteristics, as well as equations extracted from EKV MOSFET model papers and manual. Conditions to force transistors in saturation have been derived from EKV MOSFET model equations. Finally, Chapter 9 dis- cusses the contributions of the dissertation in details, and points to research directions that can be pursued in the future.

13 Chapter 2

Layout-Aware Analog Circuit Synthesis

2.1 Introduction

Established analog circuit synthesis methods fail to account for the parasitics, which are introduced during the layout stage. Therefore, a sized circuit, obtained from such a process, may fail to meet the desired performance specifications, during post-layout verification. This severe shortcoming of customary techniques has raised the demand for layout-aware analog circuit synthesis methods. The main feature of a layout-aware synthesis approach is that the parasitics are extracted or estimated in each synthesis iteration. After the optimization engine proposes a new set of values for circuit parameters, and before performances are estimated, it is imperative to analyze the correlation between the circuit parameter values and the effects due to their physical implementation. The main questions that need to be answered are: Which parasitics will be introduced by the layout? What will the numerical values of these parasitic components? The aforementioned analysis be done in two distinct ways which has lead to two different approaches for layout-aware circuit synthesis process. The first approach is that of parasitic estimation during each iteration and therefore the method is known as parasitic-aware circuit synthesis. The other technique involves generating a complete physical layout in each iteration and it is termed as layout-inclusive circuit synthesis. This approach is also referred to as the the layout-in loop approach.

2.1.1 Parasitic-Aware Circuit Synthesis

The parasitic-aware method is shown in Figure 2.1. The process starts with optimization engine proposing a set of sizes for the circuit to synthesized. Using these set of values

14 the layout-parasitics are estimated. These estimates, along with the parasitic elements, are used to generate netlists that are used for performance evaluation. One way to estimate the para-

Circuit Search Range Topology of Parameters

Optimization Performance Engine Estimates

Sizes for Circuit Parameters Sized Topology Parasitic with Parasitic Performance Estimation Evaluation Components

Figure 2.1: Parasitic-Aware Analog Circuit Synthesis sitics is to use mathematical expressions, which correlate the size of a module, with various parasitics associated with that particular module. The expressions can be obtained by a simple analysis of the layout-template of the module. The other popular technique is a table look-up method, where by using interpolation techniques, the parasitic values are guessed from pre- generated data. Both these method serve the purpose well for intra-module parasitics. The problem arises while estimating the interconnect parasitics. Due to the varying structure of interconnects, it is difﬁcult, and often impossible, to accurately estimate the parasitics. Therefore, for a high-performance circuit, the performance of which is extremely sensitive to interconnect parasitics, the parasitic-estimation technique is inadequate, due to which the parasitic-aware synthesis method can not be used.

2.1.2 Layout-Inclusive Circuit Synthesis

The layout-inclusive synthesis method is shown in Figure 2.2. The inputs to the optimization engine are the circuit topology and the search range for each independent circuit parameter. The output is a set of values for each parameter in each iteration. Using this set of parameter values, either a layout is generated completely or it is just instantiated. The result is a physical layout, which is then extracted and veriﬁed. Analog physical synthesis is the process of creating layouts from give set of parameter values. In literature we ﬁnd two popular approaches for analog physical synthesis. First is an optimization-based layout generation. This method produces optimized layouts. However,

15 Circuit Search Range Topology of Parameters

Optimization Performance Performance Engine Evaluation Estimates

Sizes for Sized Topology Circuit with Parasitic Parameters Components

Layout Physical Layout Generation/ Layout Extraction Instantiation

Figure 2.2: Layout-Inclusive Analog Circuit Synthesis since the process is based on optimization, several options are examined for optimality and therefore such an approach is computationally expensive. The limitation imposed by time taken to generate the layouts, makes this approach undesirable in layout-inclusive circuit synthesis. The alternative approach is a template-based method, often referred to as procedural layout generation. The advantage of this method is that layouts are not completely generated in every iteration, but by using a ﬁxed template, they are just instantiated. Layout instantiation time is very fast and thus this method can be used in every synthesis iteration. The shortcoming of this approach is that layouts are not optimal since the layout-template remains the same for the entire design space. We believe that it is possible to obtain a good quality layouts by using constraints on the placement of modules.

2.2 Related Work

A combination of template-based parasitic estimation and table lookup technique is proposed for layout-aware circuit synthesis in [28]. The technique works well for intra-module capacitances, but is not reliable for inter-module parasitic capacitances. Moreover, this technique is limited to medium sized circuits because of the interpolation technique used for estimating interconnect parasitics. Onodera et. al. [37] propose a layout-aware sizing technique based on procedural layout generators. The estimation of parasitics is based on simple formulae, and is limited to wire and diffusion capacitances. A similar parasitic estimation technique is proposed by Dessouky et al. [23], where a layout language(CAIRO) is used to describe the placement and routing of a circuit. This layout description is used during synthesis iteration to directly calculate parasitics

16 without actually generating a physical layout. The technique even though good for fast layout- aware circuit synthesis requires that the placement and the whole routing be written in the layout language. Moreover since the layout-template is fixed it will not yield optimized layouts. The parasitic estimation is done using the routing information and therefore requires extraction rules to be specified. The sizing methodology employed is knowledge-based. Choi et.al [16] propose a parasitic-aware technique for synthesis of RF Mixers. Only the inductor parasitics are modeled and therefore this technique is very limited, as it does take into account other device and interconnect parasitics. From the methods mentioned above it can be concluded that, while layout-aware techniques offer fast timing closure, the parasitics are difficult, and often impossible, to estimate accurately. The other option is layout-inclusive synthesis, where layout generation and extraction is done within the synthesis loop. This method captures the parasitic effects accurately as the layout generation is followed by a full layout extraction. In [33], Vancorenland et al. propose a layout-inclusive RF synthesis flow. The method uses a template-based layout generator and parasitic capacitance formulae for parasitic estimation. Performance estimation is done using analytic equations. The template evaluation time is extremely small and therefore layout generation and extraction in loop is very fast. Layout-inclusive approaches can not use synthesis-based layout generation system inside a synthesis loop because of the large run time to produce a layout. Template based (procedural) layout generators are suitable for the layout- in-loop approach.

2.3 Layout-Inclusive Synthesis using Numerical Simulations

In our work we have used a template-based layout generator for fast instantiations of physical layout inside the synthesis loop. As has been mentioned earlier, our work focuses on use of layout-inclusive techniques in conjunction with symbolic performance models, to speed up the time taken to go through one iteration of synthesis, which in turn, speeds up the entire synthesis run. To compare the efficiency of our work, a synthesis method, using template-based layout instantiations and numerical simulations, has been developed. This method, which is shown in Figure 2.3, uses the module specification language (MSL) based layout environment for generation and instantiations of layouts. The placement of a circuit is written in MSL by either using a library of modules (common group of devices) or by writing the MSL file from scratch. This

17 Circuit Search Range Cost Function Topology of Parameters

Simulated CIRCUIT Performance Cost Cost Function SIZER Annealing Evaluation Constraints Optimization

Sizes for Circuit Performance Parameter Parameters PEFORMANCE Parameterized ANALYSIS Layout SYSTEM (PAS) Performance Performance Layout Instantiation Estimation Models Generator

Physical Simulation Layout Results Sized Topology MAGIC with Parasitic SPICE Extraction Components Simulation

Figure 2.3: Layout-Inclusive Analog Circuit Synthesis description of the layout-template is then compiled and produces a C++-based parameterized layout-generator. When the optimization engine proposes a new set of sizes, the compiled layout generator, uses these values and immediately generates a physical layout. The layout is then extracted using the circuit extractor built in the Magic Tool [96]. The circuit thus extracted is passed on to the performance analysis system (PAS) [98]. PAS uses SPICE, a numerical simulator, to carry out the various kinds of analyses speciﬁed through a control block. PAS uses a common interface for different simulators and the user can choose the numerical simulator. Performance models use the simulation results to generate performance estimates. The performance estimates are then used by the optimization engine for further analysis and to generate a new set of sizes. The process reaches a conclusion when all the performance constraints have been satisﬁed.

2.4 Circuit Sizer

A circuit sizer is the heart of any analog circuit synthesis method. The task of a sizer is to allocate a set of sizes for all the unknown (independent) parameters of a circuit. Analog circuit sizing often employs heuristic search algorithms like simulated annealing, tabu search, genetic algorithm, multi-objective optimization etc, to obtain the values for the set of unsized elements. The sizer starts from an arbitrary point in the design space and moves throughout the

18 space, selecting solutions, based on the feedback it gets from the performance estimator. The ﬁnal result is a solution which satisﬁes all the performance constraints, i.e., yield a cost value of zero. PERFORMANCE ASSIGNED MINIMUM MAXIMUM PARAMETER WEIGHT VALUE VALUE DC GAIN 30 35 - THREE DB 45 2e+6 - UNITY GAIN 5 1.5e+7 - PHASE MARGIN 20 60 -

Table 2.1: An Example of a Performance Speciﬁcation File for the Sizer

Inputs to the sizer are: performance constraints, search range of each unsized parameter, and circuit netlist. Table 2.1 shows an example of a ﬁle provided to the sizer with the constraints on various performance parameters. Along with the name of the performance parameter, the maximum and minimum value expected is also given. A weight is assigned to every parameter which signiﬁes it’s importance in the search process. The weights of all the characteristics should add up to 100. A dash (-) in a maximum or minimum value, implies that no limit has been set. MINIMUM MAXIMUM SCALING DEVICE VALUE VALUE FACTOR M w 0 3 20 2000 0.1e-6 M w 1 2 40 1000 0.11e-6 M w 4 20 1500 1e-6 M w 5 20 1500 1e-6 V b1 5 18 0.1 C 0 1 1000 1e-15 I b2 1 1000 1e-5 I b3 b4 1 1000 1e-5

Table 2.2: An Example of a Search Range Speciﬁcation File for the Sizer

The way to specify the search range of each unsized parameter is shown in Table 2.2. The name of the parameter, along with the minimum and maximum range of values, is provided. Matching information is also provided in this ﬁle. For example, M w 0 3 implies that the width of transistors M0 and M3 should be matched. A scaling factor is also speciﬁed, by which all the values within the search range are multiplied to give the actual value of each parameter. The

19 scaling factor also serves as the step size for varying the values. For example, the scaling factor −15 −15 for C0 is 10 , which implies that the actual minimum value of capacitance C0 is 1 X 10 , −15 and the upper limit is 1000 X 10 . This also means that the value of C0 can be varied only in increments of 10−15 by the sizing algorithm.

2.4.1 Optimization Engine

The circuit sizing problem is formulated as a constrained optimization problem as expressed in [2.1]. Here x is the set of independent variables which can be widths and length of transistors or capacitance, resistance and inductance values or voltage and current values. We intend to ﬁnd values of these variables which optimize the set of k performance functions represented by f(x) while satisfying the set of n constraints represented by g(x).

k ∑ wi · fi(x) s.t g1 ≤ gi(x) ≤ g2 (2.1) i=1 The constrained optimization problem is mapped to an unconstrained optimization problem as shown in 2.2 below. The weights indicate the relative priority of the performance functions and are speciﬁed by the user.

k n C = ∑ wi · fi(x) + ∑ w j · g j(x) (2.2) i=1 j=1

In this work simulated annealing has been used to solve the unconstrained optimization problem formulated above since it has been proven to solve for a globally optimal solution in the presence of many local minima. Several circuit synthesis tools ([41, 74]) have used simulated annealing successfully for automatically synthesizing analog circuits in the absence of a good starting point.

2.5 Layout Generation and Instantiation

In this work, an MSL-based environment has been used to generate parameterized layouts. The proposed environment is shown in Figure 2.4 (taken from [79]). Modules are devices or group of devices and they are speciﬁed in MSL. Examples of modules are ﬁngered transistors, differential pairs, serpentine resistors etc. A higher level module is built using smaller level modules written in MSL. This ensures reusability of previously written modules and their hierarchical use. If a new module is required and it does not exist in the module library, then

20 it is written in MSL, either entirely or by using smaller modules already present in the module library. Complete circuits or systems are built hierarchically in a similar manner. The leaf level module is just a rectangle with three properties: height, width and layer-type. Matching of circuit elements is done inside the module.

New Module Definition (written in MSL) Parameterized Module Library (written in MSL) MSL Compilation New Parameterized and Layout Generator Code Generation (editable C++ code)

Layout Editor and Technology Routing Adaptation

Layer Map Layout Parameter Values Instantiation (Elaboration)

Physical Layout

Figure 2.4: Layout Generation and Instantiation Method

The MSL program for the module/circuit/system is then compiled using the MSL compiler. This produces parameterized layout as editable C++ code. This code is integrated either with place and route systems (if the placement has not already been speciﬁed in the MSL program) or just with routers. In this paper, the placement of modules has been speciﬁed in the MSL program and the code produced by compilation and code generation, is integrated with a channel router. Layout instantiation is done by providing the parameterized layout with values of layout parameters.

2.5.1 MSL Program Structure

The main features of MSL which have been mentioned already are: ability to produce parameterized modules/circuits/systems, hierarchical reusability, modules-placement capability and easy integration with place-route/route systems. A closer look at the MSL program structure will help highlight the segments which help achieve these features. Shown below is a Fingered-Transistor Module in Figure 2.5, and the the corresponding MSL program along with

21 explanation of the various sections of the program.

Figure 2.5: Transistor Module with Fingers

An MSL Program has two main sections - the header and the module definition. Module definition has five sections (some of which are optional) - attributes, types, variables, terminals and rules. The header section includes the lower level modules which are used to build the new module. It also includes the external functions like the router functions, functions to calculate number of fingers, etc. The header section for a fingered transistor is shown below:

#include "mosDevice.msl" #include "terminal.msl" header functionsMSL.hpp; functionsMSL.cpp; end header

The attribute section deﬁnes the properties of a module. These properties are the elements that make an MSL module parameterizable. Shown below are the attributes of a ﬁngered transistor. module fingeredDevice attributes tranLength,totalWidth: int; diffusionLayer,conLayer,selLayer: layer; numFingers: int; individualWidths: int[numFingers];

fingerLimit: int:=50*lambda; spacing: int:=0;

polyOh: int:=2*lambda; diffOh: int:=13*lambda;

22 selEnc: int:=0;

maxHeight: int:=18*lambda; end attributes

The types section contains the instances of lower-level modules which are used to build the new module hierarchically. In case of the ﬁngered transistor, MOS-devices and terminals have been used. types devices: mosDevice[numFingers];

innerconnectors: terminal[2*numFingers]; outerconnectors: terminal[2*numFingers]; gateconnectors: terminal[numFingers]; inner,outer,gate : rect; end types

The variable section is optional and is used to deﬁne variable local to the module deﬁni- tion. It is used to declare variables which help in placement of the lower-level module. variables arrIndex : int; innerIndex,outerIndex : int:=0; ySpacing : int:=0; outerSpace : int:=0; innerSpace : int:=0; gateSpace : int:=0; deviceSpace : int:=0; end variables

The modules are parametrically sized and placed relative to each other in a third section called the rules section. External functions written in C++ are linked and used in the rules section to perform calculations that are not possible by using the constructs of MSL alone. MSL also allows the use of array objects, or more precisely a variable number of objects of the same type which makes ﬁngering of modules an easy task to achieve. rules numFingers = fingerCalc(totalWidth, fingerLimit);

23 fingerWidthCalc(totalWidth, individualWidths, fingerLimit); maxHeight = individualWidths[numFingers - 1]; if(numFingers > 1)

{

outerSpace = 28*lambda; innerSpace = 20*lambda; gateSpace = 12*lambda; } for(arrIndex = 0; arrIndex < numFingers; arrIndex = arrIndex+1)

{ devices[arrIndex].trLength = trLength; devices[arrIndex].trWwidth = individualWidths[arrIndex]; devices[arrIndex].polyOh = polyOh; devices[arrIndex].diffOh = diffOh; devices[arrIndex].selEnc = selEnc; devices[arrIndex].diffusionLayer = diffusionLayer; devices[arrIndex].conLayer = conLayer; devices[arrIndex].selLayer = selLayer; ...... end rules

2.6 Layout Extraction

The circuit extractor used in this work is the in-built extractor in Magic [96]. It has the ability to extract both resistances and capacitances. Parasitic capacitances extracted are of two types: area capacitances and internodal capacitances. The area capacitance occurs in two ways. There exists a capacitance-to-substrate for each type of material, along with a capacitance-to-substrate per unit length, for each type of edge. Since both these capacitances are with respect to the substrate, they are also referred to as substrate capacitances. The internodal capacitances are of three types. A cross-section of a set of masks is shown in Figure 2.6, which shows the three sources for these capacitances. The ﬁrst is the overlap capacitance, which occurs when two different layers cross each other. This falls under the category of parallel plate capacitances. Another capacitance, also a parallel plate capacitance,

24 Layer_A Layer_A sidewall

overall sidewall overlap

Layer_B

Figure 2.6: Capacitance Extraction in Magic occurs between the sidewalls of two same type of layers. Therefore it is referred to as the sidewall capacitance. The last capacitance is the sidewall overlap, which is an orthogonal-plate capacitance, occurring between the vertical edge of a mask and the horizontal surface of another, when the vertical edge is present over the horizontal surface. k

R_k

R_N R_1 N 1 M

C_M

Figure 2.7: Resistance Extraction in Magic

Magic extracts the resistance and capacitance of each interconnecting net in the layout, based on the geometry of the net. The extraction of a net with N terminal, originating from one single point, is shown in Figure 2.6. Each branch of the net is extracted as a resistance Rk and a capacitance is extracted CM. If there exist several points of intersection, then a capacitance is extracted for each such point, and a resistance is extracted for every segment in the net.

25 2.7 Summary

In this chapter we have discussed in detail the layout-aware analog circuit synthesis method. The two main approaches of parasitic-aware and layout-inclusive methods have been presented. A thorough overview of the existing layout-aware techniques is then addressed. We have developed a simulation-based layout-inclusive technique for comparison purposes. A detailed overview along along with an overall description of each individual module is presented. Module speciﬁcation language (MSL) environment is used for generating parameterized layouts, MAGIC extractor is used for circuit extraction from these layouts and the performance analysis system (PAS) is used for analysis of the extracted circuit. A simulation annealing based optimization algorithm has been used in the circuit sizer.

26 Chapter 3

Symbolic Analysis based Performance Modeling

3.1 Introduction

Computationally intensive numerical simulations in traditional circuit synthesis methods can be avoided by using circuit models for performance estimates. Accurate posynomial models are difﬁcult to generate automatically [20] and are often created by expert designers [65]. Gen- eration of neural network models is time intensive and is limited to a few circuit variables [97]. The generation and evaluation of accurate symbolic performance models (SPMs) is fast [83] and therefore is the method of our choice. In our work, symbolic analysis is used for the generation of symbolic performance models. Symbolic performance models are a combination of transfer functions and they yield a performance parameter, when the values of small signal parameters and frequency are fed into it.

3.1.1 Symbolic Analysis

Symbolic analysis is a formal technique to obtain circuit characteristic equations in terms of symbolic circuit parameters and independent variables like time and frequency. It is a type of circuit analysis method which can explicitly tell which circuit parameters have a signiﬁcant inﬂuence on circuit behavior. Linear symbolic analysis involves obtaining expressions for linear network and transfer functions in terms of both the frequency and small-signal elements, which are retained as symbols. Other than use in circuit synthesis for generation of symbolic performance models, sym-

27 bolic equations also give a direct insight into the qualitative inﬂuence of each circuit component on circuit behavior. They can also show what effect adding a component can have, on the behavior of the circuit - a result very useful for analog designers. Symbolic equations also reveal the relationships between different behaviors of the circuit. This helps in the design process as it makes easier for the designer to determine which parameters are important for different performance parameters. Symbolic analysis can also be used for behavioral model generation. Another use is in testing and fault diagnosis of analog circuits. Symbolic analysis techniques can also be used for pole-zero extraction and sensitivity analysis.

3.1.2 Symbolic Analyzers vs. Numerical Analyzers

In comparison to numerical analyzers (like SPICE), symbolic analyzers have a few distinct advantages. The equations generated by symbolic analysis provide an insight into the circuit behavior. It is possible to tell by looking at the equations which are the dominant parameters, whereas, in numerical analysis the results which are just numbers, offer no insight. These equations remain valid for different values of parameters, whereas in numerical analysis simulation has to be repeated if the parameters change. In other words, the outcome of symbolic analysis, an analytic formula, is valid for large regions of design space, while the outcome of numerical analysis quantifies this behavior at an isolated point in this space. In spite of these advantages the use of symbolic analyzers is not very prevalent for circuit simulation. This can be attributed to the fact that today only linear or weakly nonlinear AC analysis is possible using them. The numerical simulators can handle strongly nonlinear behavior and time-domain analysis. Some work has been done in the field of nonlinear and transient analysis using symbolic techniques, but stable and mature algorithms are still scarce in this field. The numerical analyzers are also capable of handling larger circuits than symbolic analyzers. Symbolic analyzers use complex hierarchical analysis techniques on circuits of large complexity. Thus it can be concluded that symbolic analysis and numerical analysis are complemen- tary techniques. Symbolic analysis has not yet reached a level where it can completely replace numerical techniques as a means of circuit analysis, but it definitely does offer benefits which make it a better choice in some applications.

28 3.2 Symbolic Analysis Techniques

This section describes various symbolic analysis methods. These methods fall under one of the following categories:

1. Matrix-based methods

2. Flowgraph (topological) methods

3. Tree-enumeration methods

Matrix-based Methods

The methods that fall under this category, generate symbolic circuit equations and trans- form them into a system of linear equations of the form:

Ax = b

where A is the symbolic circuit matrix and both x and b are symbolic vectors. Several methods exist for the formulation of A. Most notable are the sparse-tableau analysis, modiﬁed nodal analysis (MNA) and its variations like reduced MNA (RMNA), compact MNA (CMNA) and super-node analysis (SNA). MNA is described in detail below. Modiﬁed Nodal Analysis The nodal admittance matrix Y is formulated from the circuit and then the variable vector V is setup which contains all the node voltages. The vector J represents all the independent current sources in the circuit. The nodal linear system is represented by;

YV = J

The nodal matrix Y is constructed by writing KCL for all the nodes, except the datum node. Row i of Y represents the KCL equation at node i. This matrix can also be constructed by an automatic method called the stamp method. In this method, each branch of the circuit is visited and its contribution is added to the nodal admittance matrix at appropriate positions. The MNA method expands on the method described above to incorporate independent voltage source and controlled sources (VCVS, CCCS and CCVS). This is done by introducing some branch currents as variables into the system of equations. Each extra current variable will need an extra equation for it to be solved. This equation is obtained from branch relationship (BR)

29 equations for branches whose currents are chosen as extra variables. The new matrix Yn is referred to as the MNA matrix. The new system of equations is of the form:

     Yn B V J    =   CD I E

where I is the vector of extra branch variables introduced, E is the independent voltage sources vector, and C and D correspond to BR equations for the branches whose currents are in I. Cramer’s Rule The system of symbolic equations Ax = b can be solved by using Cramer’s rule. Solving the system of linear equations implies deriving the closed-form expression of a circuit unknown in terms of symbolic parameters in A and symbolic excitations in w. According to the Cramer’s

rule, the kth component xk of the unknown vector x is obtained as follows:

¡ ¢ n i+k ∑ bi (−1) det Aa x = i=1 i,k k det (A)

i+k ¡ ¢ Note that (−1) det Aai,k is a co-factor of det(A) with respect to the element ai,k of matrix A at the row i and column k. Therefore, the main issue in a matrix-based symbolic analysis is how to ﬁnd symbolic expressions of det(A) and its co-factors. Two such methods are introduced in the next two sections. Laplace Expansion of Determinants This is a technique to obtain the symbolic expression of the determinant of a matrix. The expansion is done along most sparse row or column. The formulae for expansion of A, a nXn matrix, along row r and column c are as follows:

n r+c ¡ ¢ det (A) = ∑ ar,c (−1) det Aar,c r=1 n r+c ¡ ¢ det (A) = ∑ ar,c (−1) det Aar,c c=1 The setup time of equations as well as their evaluation time is very large, therefore Laplace expansion is not a preferred choice for generating the symbolic determinant of a matrix.

30 Flowgraph (Topological) Methods

Two types of flowgraphs are used in the field of symbolic analysis. They are the signal- flow graph and Coates graph. Only the signal-flow graph is described in the following section. Signal-flow graph and Mason’s rule The process of symbolic analysis using signal-flow graphs involves two steps. The first step is to construct the signal-flow graph from the given circuit. Second step is to do analysis on the graph and apply Mason’s rule to obtain the symbolic expressions. The major challenge in applying Mason’s rule is listing all paths from input to output node, in the SFG, in addition to finding loops of all orders. The other problem is the selection of optimum tree while the formation of SFG from the given circuit. Also the term cancelation problem exist in this method.

Tree-enumeration Methods

Tree-enumeration method is the oldest symbolic analysis process and is the basis for old and new symbolic analysis programs. Direct implementation of these programs can handle only small circuits because of the exponential growth in the number of terms. This method can handle only one type of controlled source; namely voltage-controlled current source. Also the method does not produce any symbolic term cancelation. Directed tree-enumeration First a modiﬁed version of the original circuit is constructed along with it’s directed graph, then all the directed trees of the graph are enumerated. The product of admittances of these trees, gives nodal admittance matrix’s symbolic determinant and co-factors. These are used to generate the symbolic-transfer functions. Undirected tree-enumeration The undirected tree-enumeration method is also called the two-graph tree-enumeration method. First the two graphs,i.e., the voltage graph and the current graph, are constructed from the circuit, then the trees and appropriate 2-trees common to both the graphs are enumerated. The product of admittances of these trees gives the nodal admittance matrixes symbolic determinant and co-factors. These are used to generate the symbolic-transfer functions.

31 3.3 Hierarchical Symbolic Analysis

Issues such as huge memory requirements for storing the symbolic expressions, and the time required to generate the expressions, limit the scope of classical symbolic analysis methods to small circuits. For large circuits, or even moderately large circuits, hierarchical symbolic analysis techniques have to be used. These techniques use classical divide-and-conquer method and nested expressions. Hierarchical symbolic analysis can be performed at two levels - circuit and output-expression levels. These two levels are independent from each other.

3.3.1 Circuit-level hierarchy

The key idea in this approach is to partition the circuit into smaller sub-circuits, and then do a symbolic analysis on the sub-circuits, and then combine the symbolic solutions obtained from the sub-circuit to produce symbolic expressions for the entire circuit. The circuit can be split into several levels of hierarchy and then the symbolic analysis starts from the sub-circuits at the lowest level (terminal block analysis). It proceeds to the sub-circuits at the intermediate levels (middle-block analysis) and this process continues till the transfer function for the entire circuit has been produced.

3.3.2 Expression-level hierarchy

The problem of exponential growth in the number of symbolic terms with the size of the circuit, can be solved by using a sequence of expressions procedure, rather than using a single expression procedure for generating transfer functions. The idea is to produce a succession of small expressions with a backward hierarchical dependency on each other. The growth of expressions in the worst case is quadratic.

3.4 Symbolic Performance Model Generation

This section describes in detail the use of symbolic analysis techniques in analog circuit synthesis. Symbolic analysis is used for generation of symbolic performance models. What are symbolic performance models? Symbolic performance models are a set of characteristic equations in terms of symbolic circuit parameters, which represent the performance parameters of an analog circuit. Performance parameters are circuit characteristics such as gain, common-

32 Parasitic−Inclusive Input,Output & Circuit Topology Small−Signal Power Nodes Models

Node Expansion Information Module Generator

Combination Expanded of nodes Circuit

List of Symbolic Symbolic Performance Model Analysis Parameters Builder Engine

Performance Symbolic Models Transfer Functions Compilation

Compiled Symbolic Performance Models

Figure 3.1: Symbolic Performance Model Generation mode rejection ratio, slew-rate and power-supply rejection ratio. A symbolic transfer function, which is obtained by symbolic analysis, or a combination of such functions is used to obtain a performance model. In automated circuit synthesis, performance models are used for repetitive numerical evaluation. The values of the symbolic parameters are furnished by the search engine, which employs heuristic techniques like simulated annealing to come up with new sizes. Two conditions for using performance models in circuit synthesis are speed and accuracy. The evaluation time of performance models should be small, because these performance models are evaluated thousands of time during the search process. If they cannot be evaluated fast, then their use for simulation purposes is a waste. The second issue is that the performance models on evaluation should yield accurate results. We do not consider the time required to set up these expressions, because that is a one- time process and it does not effect the simulation time. The size of the expressions in a performance model inhibits the fast evaluation of circuit characteristics. There exist techniques for obtaining reduced symbolic expressions [30], but due to approximation there is a loss of accuracy. This inaccuracy can mislead the circuit sizing process and the design ﬁnally obtained may not satisfy the performance speciﬁcations. Hence the goal of symbolic analysis in circuit

33 synthesis is to obtain complete transfer functions and thus exact performance models which can be evaluated fast. The process of generation of symbolic performance models has been explained in Figure 3.1. The ﬁrst step is the generation of node information. A combination of nodes is produced at this stage which is used to generate the performance models and transfer functions. The symbolic model builder uses the node information to generate expression which combine two or more symbolic transfer function and generate a performance parameter. The symbolic analysis engine uses the nodes information, to generate the desired transfer functions. At the same all the active devices in a circuit are replaced by their small signal models, respectively. This step is named as the expansion module because generally one element is replaced by several elements as small-signal model. Then comes the stage of building of performance models.The input to this module is the list of performance parameters and the combination of nodes generated required for this list of parameters. This module generates equations which represent performance models. They do not have the transfer function expressions in these expressions, just a reference to the transfer function to be used.

• For the single-ended opamp, the DC Gain model would be like,

h i Gain = 20log T (x,s) DC 10 x=Xi,s=0

where, T(x,s) is the transfer function generated by the symbolic analysis engine. Xi is the numerical value of x, the vector of circuit parameters, furnished by the optimization engine in the ith iteration. Thus we see that the performance models along with transfer functions form the symbolic performance models.

• Some performance models are form of equations like the Unity Gain Frequency.

UGF = Solve for s, 20log {T (x,s) } = 0 10 x=Xi

Such equations have been solved using Bisection Method.

Transfer functions are obtained by doing the symbolic analysis of the linearized circuit. The process of symbolic analysis is described below.

34 3.4.1 Determinant Decision Diagrams

This is graphical technique to represent a symbolic determinant. Special data structures called ZBDD’s, which represent sparse subset systems, were adapted to represent sparse matrix systems. This led to the formulation of graph representation of symbolic determinants,i.e., determinant decision diagram (DDD). This representation is compact for a large class of analog circuits. It is also canonical, i.e., every determinant has a unique DDD representation. The canonicity of representation facilitates efﬁcient symbolic analysis. Finally, derivation, manipulation and evaluation of DDD representations of symbolic determinants have time complexity proportional to DDD sizes.

3.4.2 Element-based Coefﬁcient Diagrams

Figure 3.2: Common-Source Stage with Passive Load

In circuit synthesis it is essential that the expressions which make up the symbolic performance models are complete, compact, fast to evaluate and easy to manipulate. The compactness of expressions implies symbolic expressions and hence symbolic performance models, which exploit sharing of sub-expressions and expressions free of term-cancellation. The completeness implies, no approximation of the symbolic expressions, so that the same models are valid for the entire design space. The generation of complete compact expressions is very important for minimization of memory requirements and accuracy of results of performance parameters. Compact representations can also lead to fast evaluation of expressions [54] [51] [88] [82] [83].Fast evaluation of expressions is a critical step since thesemodels are used for repetitive numerical analysis, and is the fundamental reason for the use of symbolic performance models. Efﬁcient manipulation of

35 denom numer

1 -__input__

v3 v8

-1 1

v4 v9

-s*cgd_m1 -s*cbd_m1 -g_rds_m1 -g_rd s*cgd_m1 -gm_m1

v5 v10

-1 1

-1

Figure 3.3: Determinant Decision Diagram for CS Stage the expressions into the s-polynomial format [93] [83] is also significant because it allows fast evaluation of models for different frequencies, at the same design point. This helps describe the entire ac behavior accurately. Keeping the above mentioned factors in mind we selected Element-Coefficient Diagrams (ECDs), a graphical technique, to represent a symbolic determinant [93]. According to the Cramer’s rule each network transfer function is ratio of two determinants. To represent these two determinants, two ECDs are constructed. One of them represents the numerator of the transfer function and the other, denominator. The first step in obtaining an ECD from a determinant, is the construction of a Determi- nant Decision Diagram (DDD). This is done by using Laplace expansion on the determinant along a row or a column. The result at each intermediate level, which are minors of the original matrix, are also expanded similarly and represented graphically. In the graph each vertex represents a minor and each edge represents an element in the circuit matrix. The top vertex represents the symbolic determinant of the circuit matrix. Recursive application of Laplace expansion rule on the circuit matrix finally results in only 1x1 minors, which evaluate to the element they contain. In the graph representation the 1x1 minor is represented as an edge ter- minating in a 1-vertex symbolizing value of 1. The ordering of columns can be done using either of two approaches: static column selection scheme, in which the columns are ordered according to sparsity prior to the first column

36 denom_0 denom_1 numer_0 numer_1

1 1 -__input__ -__input__

v3_0 v3_1 v8_0 v8_1

-1 -1 1 1

v4_0 v4_1 v9_0 v9_1

-g_rds_m1 -g_rd -cgd_m1 -cbd_m1 -gm_m1 cgd_m1

v5_0 v10_0

-1 1

v6_0

-1

Figure 3.4: Element-based Coefficient Diagram for CS Stage expansion, or the greedy column selection scheme, where the most sparse column is selected prior to each column expansion. Additional zero-suppression and splitting into parallel edges steps have to be carried out to obtain the final DDD. Figure 3.3 shows the DDD of a Common- Source Stage with a passive load shown in Figure 3.2. The DDD’s are then manipulated to obtain ECDs so that individual numerator and denominator coefficients can be obtained. The coefficient graphs are subvertices of the top vertex of the original DDD and they are derived by applying subvertex construction rule described in [93]. The ECD for common-source stage circuit is shown in Figure 3.4. As can be seen the coefficient graphs are overlapping, resulting in a relatively low number of subvertices. The time and space complexity of the ECD’s is linear with the size of the original DDD. Note here that numer 0 represents the coefficient of the numerator corresponding to s0.

3.4.3 Compilation and Evaluation of ECDs

During the synthesis process compiled ECDs are used for evaluation. This reduces the performance model evaluation time considerably. The ECD shown is Figure 3.4, is ﬁrst dumped as a C++ code and is compiled. The example below shows the way the ECD is evaluated. The compiled C++ code takes in as input, a map of small signal parameters and their values, SSV. The evaluation takes a bottom up approach starting from the 1-vertex v1, which has the value 1, and proceeds upwards to ﬁnally obtain the value of numerator and denominator coeffcients

37 Symbolic/Numeric Gain vs. Frequency 40 Sym Num 20

−20 Gain (dB)

−40

−60

−80 0 5 10 15 10 10 10 10 Frequency (Hz)

Figure 3.5: Comparison of Symbolic and Numeric Gain Responses of the transfer function represented by the ECD. The evaluation function of ECD in Figure 3.4 is shown below.

Evaluate ECD (SSV) v1 = 1

v6 0 = -1 * v1 v10 0 = 1 * v6 0 v9 0 = -SSV.gm m1 * v10 0 v8 0 = 1 * v9 0 v9 1 = SSV.cgd m1 * v10 0 v8 1 = 1 * v9 1 v5 0 = 1 * v6 0 v4 0 = -SSV.g rds m1 * v5 0 + -SSV.g rd * v5 0 v3 0 = -1 * v4 0 v4 1 = -SSV.cgd m1 * v5 0 + -SSV.cbd m1 * v5 0 v3 1 = -1 * v4 1 numer 0 = - input * v8 0 numer 1 = - input * v8 1 denom 0 = 1 * v3 0 denom 1 = 1* v3 1 end Evaluate ECD

38 Symbolic/Numeric Phase vs. Frequency 4 Sym Num 3

0 Phase (rad) −1

−2

−3

−4 0 5 10 15 10 10 10 10 Frequency (Hz)

Figure 3.6: Comparison of Symbolic and Numeric Phase Responses

3.4.4 Accuracy of Symbolic Performance Models

The AC response of symbolic performance models was compared to the the response obtained by numerical simulation using SPICE. The circuit under test was a single-ended opamp shown in Figure 4.4. In Figure 3.5, it can be seen that the gain-response for both cases, overlap each other, up to very high frequencies. Deviation in the two responses, at very high frequency, occurs because SPICE uses different a different small-signal transistor model at high frequencies. In case of SPMs, if we switched the small-signal model at high freqency, the two responses would overlap each other again. A similar trend can be seen for the phase-response in Figure 3.6.

3.5 Summary

The chapter presents in detail, the advantages of using symbolic analysis based performance modeling, over numerical simulator based methods. A variety of symbolic analysis techniques have been presented and the merits of each have been discussed. The determinant decision diagrams have been presented in details. A variation of DDD’s, element-coefﬁcient diagram has been used in our work for the purposes of performance modeling. A detailed symbolic performance modeling framework has also been presented.

39 Chapter 4

Layout-Inclusive Analog Synthesis using Symbolic Performance Models

In this chapter we present new synthesis method which combines a combines parameterized layout generators with SPMs for fast performance closure during analog circuit sizing. To combine the two aspects, algorithms for inclusion of layout effects into the SPMs have been presented and their efﬁciency and accuracy demonstrated. The paper is organized as follows. The new synthesis method is described in Section 4.1 followed by techniques to include layout effects in the SPMs in Section 4.2. Experimental results are presented in Section 4.3 followed by conclusions in Section 4.4.

4.1 Proposed Circuit Synthesis Approach

The proposed circuit synthesis environment is shown in Figure 4.1. Layouts are generated by using the Module Specification Language(MSL) system [46], which produces parameterized layouts. A parameterized layout is a fixed template layout, which when provided with the values of the circuit parameters by the optimization engine, produces a physical layout. In our case simulated annealing is used for optimization. A standard circuit extractor is used to extract the devices and parasitics from the layout. The extracted parasitic values along with the passive component values are passed to the pre-compiled SPMs. The SPMs also take in the small-signal parameter values for all active devices obtained by performing an operating point analysis using SPICE. The performance estimates obtained from SPMs are compared to the specified constraints. If necessary, the optimization engine proposes a new set of design

40 Search range Circuit for each circuit Topology parameter Cost Function

Optimization Cost Cost Function Modified Circuit MSL Program Engine Evaluator Topology for the Circuit Pre−Compiled Sizes Performance Parameter Parameters Symbolic −ized Performance Symbolic MSL Layout Layout Symbolic Models Performance Performance Compiler Generator Instantiation Evaluator Model Generator Physical Parasitic Small−Signal Layout Values Values

Extraction Operating Point Analysis Parasitics Inclusive Netlist

Figure 4.1: Proposed Approach parameter and this process continues till convergence.

4.1.1 Layout Generation and Instantiation

The MSL system is used to generate parameterized layouts. MSL contains constructs for hierarchical instantiation and relative placement of modules and for deﬁning parameterized nets for routing. When compiled an MSL program yields an executable layout generator which can be quickly elaborated into a concrete layout, when concrete size information is available from the optimization engine. A library of parameterized module generators, including ﬁngered transistors, differential pairs, current mirrors, resistors, capacitors,inductors etc, has been developed in MSL.

4.1.2 Symbolic Performance Modeling

Symbolic performance models (SPMs) are symbolic equations in terms of circuit parameters [40]. They represent the characteristics of an analog circuit. SPMs are built using symbolic transfer functions which are obtained by symbolic circuit analysis. In circuit synthesis, SPMs are used for repetitive performance estimation during the optimization iterations. Unlike nu-

41 merical simulators, analysis is not done in every iteration and only evaluation of the SPMs is needed. This results in a significant speedup of the performance estimation time. The framework for the generation of SPMs is presented in Figure 3.1. The first step is to generate combinations of nodes that appear in a performance characteristic formula. All the active devices in a circuit are expanded to their small-signal models. The symbolic analysis engine uses the node information to generate the required transfer functions as Element Coeffi- cient Diagrams (ECDs). The symbolic model builder uses the node information to generate the formulae for the desired performance characteristics. The combination of the symbolic formulae and transfer functions are called SPMs. In our methodology, the SPMs are generated using a modified parasitic-inclusive circuit topology. Techniques to include the relevant set of parasitic elements and various layout effects in the SPMs are described in Section 4.2.

The core of this SPM generation process is symbolic analysis. Symbolic analysis is a formal technique used to obtain network transfer functions in terms of symbolic circuit parameters and independent variables like frequency [43]. In circuit synthesis it is essential that the SPMs are not approximate, require minimum space, are fast to evaluate and are stored in the s-polynomial format [83]. In this chapter we use ECDs to represent a symbolic determinant. The process of ECD-based symbolic analysis is described in [93]. The ECDs are converted to C++ code and then compiled. The use of pre-compiled ECDs reduces the SPM evaluation time considerably. An average speedup by a factor of 32, with respect to evaluation of ECDs stored in memory, was observed for for the ﬁve benchmark circuits discussed in this chapter.

4.2 Inclusion of Layout Effects in Symbolic performance Models

As component sizes vary during synthesis, the layout geometry varies between iterations. This variation may generate varying sets of parasitic elements (resistances and capacitances) in each iteration. The variation of width of a transistor module also causes the number of ﬁngers to change between iterations. For example, Figure 4.2 shows two instances of a transistor module with and without ﬁngers. In this section we talk about techniques to model these variations in the original circuit topology, which in turn generates parasitic-aware SPMs.

42 4.2.1 Inclusion of Layout Parasitic Elements

Let C(R) be the set of all parasitic capacitances (resistances) ever appearing in an extracted circuit. Some elements of C(R) might be missing (set to zero) in some instances of the extracted circuits. However, an SPM including all potential parasitic capacitances (C) and resistances (R), must be pre-generated. Techniques to do so are described next.

Inclusion of Parasitic Capacitances

We describe three techniques for determining and including parasitic capacitances, C, in the SPMs.

1. Complete Set Technique This method assumes that there is a potential symbolic capacitance between every two nodes of the circuit. Therefore,

C = {Cab = Cba | a,b ∈ N, a 6= b}

|N| |N|(|N|−1) where N = set of all nodes. Hence |C| = C2 = 2 The advantage of using this technique is that no parasitic element will be missed out and hence the results obtained by evaluation of the models will be accurate. However, their is an explosion in the number of circuit elements due to the inclusion of symbolic parasitic elements some of which may never be extracted from any layout. The result is an increase in the time required to generate and compile the ECDs.

2. Layout Sampling Technique In layout sampling technique, we generate a number of sample layouts of the entire circuit, examine which area and coupling capacitances are extracted from these layouts and symbolically include only those capacitances in the SPM generation process. The advantage of using this method is that only relevant parasitics, i.e., those which have appeared due to extraction of layouts, are taken into account. This method may not generate all possible parasitic elements and this may cause inaccuracy if a new physical capacitor is extracted. There is an additional overhead of generating the layout samples. The sampling methodology used in our experiments is random sampling.

3. Analysis-based Technique

43 This method uses information about the layout-template and routing technique and determines the symbolic parasitic capacitances. During layout extraction, the two signiﬁcant groups of capacitances extracted are area and internodal coupling capacitances [81]. The internodal coupling capacitances include overlap, sidewall overlap and sidewall capacitances. In any layout the two main parts are modules and interconnects. Each module and interconnect has both area and coupling capacitances. Hence, the four categories of capacitances that are generated after extraction are: CMA, the set of area capacitances of all modules; CMC, the set of coupling capacitances of all modules; CIA, the set of interconnect area capacitances; CIC, the set of interconnect coupling capacitances. The complete set of parasitic capacitances is:

C = CMA ∪ CMC ∪ CIA ∪ CIC

(a) Module Capacitances Analysis

This involves determining CMA and CMC. In an MSL system a module has fixed templates. A fixed template always generates the same set of capacitances for any size. The set of these potential capacitances can be determined either by applying the knowledge of extraction rules or producing the layout of any one instance of the module. Figure 4.2 shows two templates of a transistor module, one with fingers and the other without. For the case of non-fingered transistor module (module x) the set of capacitances obtained are:

CMAx = {Cn1 GND,Cn2 GND,Cn3 GND,Cn4 GND}

CMCx = {Cn1 n2,Cn1 n3,Cn1 n4}

Figure 4.2: Transistor Modules

For the ﬁngered module the set of all possible capacitances is different from previous example because a few extra capacitances have been introduced due to internodal interconnect

44 coupling. All possible symbolic capacitances in this case are:

CMAy = {Cn1 GND,Cn2 GND,Cn3 GND,Cn4 GND}

CMCy = {Cn1 n2,Cn1 n3,Cn1 n4,Cn2 n3,Cn2 n4,Cn3 n4}

Since the template information for all modules is available, the set of all possible capacitances can be determined for the entire layout. Finally we have

[m [m CMA = CMAi & CMC = CMCi i=1 i=1 where, m is the number of modules. Eventually |CMA| = |N| − 1 , since each node has an area capacitance to the substrate.

(b) Interconnect Capacitances Analysis The MSL system uses a channel routing style to route the nets and the technique described below is specific only to that style. Similar to the case of modules, the set of area capacitances and internodal coupling capacitances for the interconnects have to be found. The set of area capacitances for interconnects is the same as that of the modules CIA = CMA, since all interconnect nodes are present inside the modules too. Therefore, one symbolic capacitance at a node can model multiple physical capacitances at that node, one due to the node layer and others due to the interconnect. At the SPM evaluation time all the parallel physical capacitor values are added up to yield one value for the symbolic capacitance. For the internodal coupling capacitances of interconnects, we focus only on the sidewall coupling capacitances because they are the only significant ones. The coupling capacitances are obtained as described below. Let, h be the number of channels and CICi the set of internodal Sh coupling capacitances in channel i. Then, CIC = i=1 CICi . The capacitances in each channel are very difficult to estimate, since based on the modules sizes the routing varies and hence also the coupling between interconnects. Therefore for each channel we include a complete set of all-possible capacitances. For each channel this set is known, as we are familiar with the layout template. Let, ni is the set of nodes in channel i. Then |n |(|n | − 1) C = {C = C | x,y ∈ n , x 6= y} & |C | = i i ICi xy yx i ICi 2

The advantages of using this method are that all the relevant capacitances are obtained without generating sample layouts. Some unnecessary capacitances are generated because of

45 Table 4.1: Comparison of Parasitic Capacitances Inclusion Techniques: Part I Circuit # # # Parasitic Caps ECD Name Devices Nodes CS LS AB Depth SEO1 9 10 55 32 37 10 TSO1 5 11 55 31 31 11 TSO2 9 11 55 30 32 11 SEO2 16 17 136 56 65 17 LPF 22 22 231 48 61 22

Table 4.2: Comparison of Parasitic Capacitances Inclusion Techniques: Part II Circuit # ECD-Vertices # ECD-Edges Name CS LS AB CS LS AB SEO1 705 503 580 8,694 3,972 5,565 TSO1 1,236 668 668 14,352 4,234 4,234 TSO2 1,550 1,024 1,288 25,953 8,479 11,996 SEO2 264,254 1,661 23,450 5,109,736 13,522 222,789 LPF 3,734,349 11,583 80,326 24,294,879 71,563 613,667

the exhaustive technique used for interconnect coupling capacitances. The limitation of this method is that it is valid for a fixed layout template methodology. Table 4.1, Table 4.2 and Table 4.3 compare the complete-set (CS), layout sampling (LS) and analysis-based (AB) techniques of layout parasitic capacitances. The comparison is done on five benchmarks. Single-Ended Op-amp1(SEO1) is the device model of CMOS Operational Amplifier in [57]. Twostage Op-amp2(TSO2) is borrowed from page 308 of [78]. Low Pass Filter (LPF), has been borrowed from page 410 of [7] and is shown in Figure 4.5. LPF is a fourth-order Butterworth filter of Sallen-Key implementation. SEO2 is also a single-ended op-

Table 4.3: Time Comparisons for Parasitic Capacitances Inclusion Techniques Circuit ECD Generation ECD Compilation ECD Evaluation Name CS LS AB CS LS AB CS LS AB SEO1 9.4s 8.8s 9.3s 17.0s 10.0s 12.8s 1.6ms 1.0ms 1.2ms TSO1 9.6s 8.9s 8.9s 22.2s 10.3s 10.3s 2.5ms 1.4ms 1.4ms TSO2 10.3s 9.2s 9.3s 37.9s 15.2s 19.3s 3.1ms 2.1ms 1.5ms SEO2 252.3s 10.7s 19.1s C/F 30.6s 53m18.1s C/F 3.2ms 19.3ms LPF 8323.3s 13.8s 43.1s C/F 212.8s C/F C/F 17.7ms C/F

46 vdd

IB1

IB1 Vinp Vinn MP0 MP1

IB2 IB3

Voutp Voutn C0 C1

vbias MN3 MN2 MN1 MN0

+ VBIAS Gnd

Vss

Figure 4.3: Twostage OpAmp I amp which is shown in Figure 4.4 and TSO1 is yet another twostage op-amp shown in Figure 4.3. SEO1 is used to implement the LPF. Table 4.1 and Table 4.2 gives an account of the number of capacitances added to the original topology for each inclusion technique. It also demonstrates the effect of number of extra capacitances on the size of the ECDs. Table 4.3 shows the generation, compilation and evaluation times of ECDs (and hence the SPMs). For SEO2’s CS technique and LPF’s CS and AB techniques the compiler crashed (C/F = Compiler Failure) while compiling the ECDs due to the large size of circuits. This implies that for large circuits the LS technique is the most suitable technique. As the size of circuits increase further, hierarchical techniques of symbolic analysis will have to be used for generation of SPMs. Figure 4.6 presents the accuracy-results of the three capacitance inclusion techniques for the op-amp TSO1 (Figure 4.3). The comparison is done with respect to numerical analysis. Approximately 2000 samples were used for comparison. The comparison was done by using all the set of circuit parameters proposed by the optimization engine during a synthesis run. The performance parameters - gain, three-dB frequency, unity gain frequency - were selected only when the values of gain for a particular set of sizes was greater than 1dB. The ﬁgure shows results for gain and unity-gain frequency. Similar results were obtained for phase margin and three-dB frequency. The results show that even when layout-sampling strategy is used for parasitic-capacitance inclusion, the accuracy is almost the same as in the case of analysis-

47 Figure 4.4: Single-ended OpAmp based or complete set technique. This gives us the conﬁdence to use the LS technique for our experiments.

Inclusion of Parasitic Resistances

In this section we describe a technique to include parasitic resistances in the SPMs. Re- sistance extraction is done only for the interconnects of the layout. The analysis-based parasitic capacitance inclusion technique is not valid for interconnects when resistance extraction is done. Hence a two stage extraction strategy is employed. First only the modules are extracted to obtain the symbolic parasitic capacitances. Then the interconnects are extracted to obtain both symbolic parasitic resistances and capacitances. The parasitic resistances can be modeled as described below. The interconnect parasitic capacitances are modeled as a capacitance to ground for each node extracted during symbolic resistance extraction. For multi-terminal nets the number of resistances extracted in different iterations may not be the same. This is because the pin positions change and this causes the nets geometry to change. Figure 4.7 shows a multi- terminal net with one terminal on the top row and three terminals on the bottom row. Based on the relative x-coordinate of node a, a(x) with respect to c(x), the number and position of resistances extracted vary. To model these variations a complete model, which is a superset of all possible combinations, is used to generate the SPMs. The actual evaluation of the SPMs is done by determining the relative coordinates of the critical nodes (a and c, in the above example) and

48 C2 C4

R1 R2 SEO1 + R5 SEO1 + − Vin − Vout R4 C1 C3 R8 R3 R7

Figure 4.5: Low Pass Filter

Figure 4.6: Accuracy of the Hierarchical Approach (A) Gain of TF u41(B) Phase of TF u41 setting the value of some resistances and conductances to zero. Extending the above example to the general case where a multi-terminal net has m terminals in the top row and n terminals in the bottom row, Figure 4.8 shows the complete resistance network used in the circuit topology for the generation of SPMs. In this network there is a set of resistances between each intermediate node of the top terminals and intermediate node of the bottom terminals called RINT .

RINT = {Rab = Rba | a ∈ TN b ∈ BN} where, TN is the set of all intermediate nodes corresponding to the top row and BN is the set of all intermediate nodes corresponding to the bottom row.

Another set of resistances RADJ exist between each pair of adjacent nodes of TN and each pair of adjacent nodes of BN. There is also a set of resistances between each intermediate node of TN and BN, and the corresponding terminal nodes in TT and BT . This set of resistances is

49 a a

b c d b c d General = 0 Case1 : a(x) = c(x) G1=G3=R6=R8 Resistance a a Model of the net a

R1 R2 R3 R4

b c d R5 b c d R6 R7 R8 G2 = G3 = R8 = 0 Case2 : a(x) < c(x) b c d a a

b c d b c d Case3: a(x) > c(x) G1 = G2 = R6 = 0

Figure 4.7: An Example of Inclusion of Parasitic Resistances

referred to as RTER. Thus,

R = RINT ∪ RADJ ∪ RTER

During evaluation based on the pin position of top terminals with respect to the bottom terminals, most of the resistances are eliminated by setting their conductances to zero.

4.2.2 General Inclusion of Fingered Transistor Effects

A transistor module is expanded to a small signal model before symbolic analysis. De- pending on the width of the transistor it may or may not be fingered during an iteration. When a transistor is fingered, it appears as more than one transistor in the extracted file. This variation in the number of fingers needs to be captured in the SPMs. A transistor module is modeled by only one lumped small-signal model, even if is fingered. The parameters of the lumped small-signal is just a summation of small-signal values of ∑ f each finger. Hence, Cgs = i=0 Cgsi and other lumped small-signal parameters can be expressed similarly. Here f is the number of fingers. The small-signal values of each finger are obtained

50 Tt0 Tt1 Tt2 Tt3 Tt4 Ttm

Tn0 Tn1 Tn2 Tn3 Tn4 Tnm

Bn0 Bn1 Bn2 Bn3 Bn4 Bnn

Bt0 Bt1 Bt2 Bt3 Bt4 Btn

Figure 4.8: General Inclusion of Parasitic Resistances by doing a numerical simulation using SPICE. To eliminate the need to dig up the small signal parameter value of each finger from the simulation results, only the values of the first, second and the last finger(in case the last finger is a of different size than others) are obtained. If the number of fingers is even and all fingers are of the same size then (other cases can be expressed similarly), then the lumped values are: Cgb = f ×Cgb1 ,Gm = f × Gm1 ,Gmb = f × Gmb1 ,Gds = f × Gds1 and, Cgs = f /2 ×Cgs1 + f /2 ×Cgd2 , Cgd = f /2 ×Cgd1 + f /2 ×Cgs2

4.3 Experimental Results

Table 4.4 presents the results for two approaches of circuit synthesis.The ﬁrst approach (Flow1) uses the MSL environment and NG-Spice for layout-inclusive synthesis. The second approach (Flow2) uses MSL with SPMs. The layout sampling technique is used for the inclusion of parasitic capacitances. The layout editor used in both approaches is Magic 7.1 and the numerical simulator is NGSpice. Parasitic resistances have not been modeled in these experiments. The obtained performance estimates for Flow2 are veriﬁed using NG-Spice. All the results are within 5% error. This error can be attributed in part to the LS parasitic inclusion technique as it fails to include all parasitic capacitances and in part to the bisection method of solving for roots of the transfer function, to obtain the values of unity gain and -3dB frequencies. Table 4.5 presents the time results for both methodologies. The performance convergence in both cases is fast due to the use of a language-based layout generator. Flow2 is 15%-30% faster than Flow1, per iteration. The Numeric analysis time of Flow2 (for operating point anal-

51 Table 4.4: Layout-Inclusive Circuit Synthesis Results

Circuit Attribute Constraints Flow1 Flow2 Flow2 Veriﬁed % Error DC Gain ≥50 dB 50.133 dB 54.185 dB 54.182 dB +0.006% SEO1 F−3dB ≥1.0e+05 1.761e+05 1.318e+05 1.308e+05 +0.759% UGF ≥1.0e+07 5.601e+07 6.348e+07 6.459e+07 -1.749% PM ≥ 60◦ 68.401◦ 64.273◦ 63.888◦ +0.599% DC Gain ≥40 dB 40.568 dB 43.921 dB 43.42 dB +1.141% TSO1 F−3dB ≥5.0e+06 5.034e+06 5.033e+06 5.037e+06 -0.079% UGF ≥5.0e+07 5.430e+08 6.908e+08 6.659e+08 +3.605% PM ≥ 50◦ 61.389◦ 54.961◦ 54.042◦ +1.672% DC Gain ≥23 dB 23.918 dB 25.721 dB 25.948 dB -0.883% TSO2 F−3dB ≥5.0e+06 8.998e+06 5.015e+06 5.238e+06 -4.447% UGF ≥5.0e+07 1.257e+08 1.049e+08 1.022e+08 +2.574% PM ≥ 50◦ 50.434◦ 74.956◦ 77.899◦ -3.926% DC Gain ≥35 dB 42.665 dB 40.037 dB 39.774 dB +0.657% SEO2 F−3dB ≥1.0e+06 1.021e+06 1.142e+06 1.181e+06 -3.415% UGF ≥1.0e+07 1.196e+08 8.451e+07 8.722e+07 -3.207% PM ≥ 60◦ 64.39◦ 75.308◦ 76.73◦ -1.888% LPF DC Gain ≥10 dB 10.119 dB 10.201 dB 10.201 dB 0.00% F−3dB 950-1050 1042.85 1025.04 1024.8 +0.023% ysis) is 65%-75% faster than Flow1. Model evaluation time of Flow2 (SPM evaluation time) is 13-88 times faster than model evaluation (the process of obtaining desired performance attributes from the analysis results) time for Flow1. Overall, SPM-based performance estimation time is 1.25-1.5 times faster than NG-Spice-based method. The total synthesis time for both approaches is not compared because the number of iterations to converge to a solution is different in both cases (N/A is Not Applicable). All experiments have been conducted on SunBlade 1000 with Solaris(SunOS), 2048MB RAM and 2-750MHz Processors.

4.4 Conclusions

The chapter has proposed a new methodology for layout-inclusive circuit synthesis. The use of SPMs speeds up the simulation process considerably and the overall synthesis speed is faster by 15%-30%. The evaluation of pre-compiled SPMs is signiﬁcantly faster than those in memory. Techniques have been developed to accurately and efﬁciently model the layout effects in the SPMs. There are two main areas where the proposed methodology can be improved.

52 Table 4.5: Time Results of Layout-Inclusive Circuit Synthesis

Synthesis Total Time per Iteration Circuit Approach System # Layout Performance Estimation Total Name & Time for Iter. Gen. Numer. Model Total Iter. Speedup Synthesis & Ext. Analysis Eval. Time Flow1 520.2s 286 1.039s 0.441s 0.158s 0.603s 1.642s SEO1 Flow2 125.7s 96 1.042s 0.254s 0.0018s 0.263s 1.309s Speedup N/A N/A -0.3% 73.6% 8683% 129.3% 25.4% Flow1 893.3s 432 1.296s 0.447s 0.171s 0.624s 1.919s TSO1 Flow2 361.1s 230 1.292s 0.264s 0.0026s 0.273s 1.570s Speedup N/A N/A 0.03% 69.9% 6547% 128.6% 22.2% Flow1 1865.2s 902 1.311s 0.425s 0.187s 0.621s 1.932s TSO2 Flow2 932.1s 585 1.311s 0.248s 0.0023s 0.257s 1.593s Speedup N/A N/A 0.00% 71.4% 8042% 141.6% 21.3% Flow1 1476.6s 446 1.703s 0.461s 0.171s 0.643s 2.346s SEO2 Flow2 1010.0s 369 1.704s 0.273s 0.0041s 0.285s 1.989s Speedup N/A N/A - 0.06% 68.9% 4081% 125.6% 18.0% Flow1 524.3s 253 1.095s 0.417s 0.248s 0.671s 1.766s LPF Flow2 692.2s 503 1.093s 0.241s 0.019s 0.271s 1.374s Speedup N/A N/A 0.1% 73.0% 1210% 147.6% 28.5%

First, the size of circuits this method can handle are not very large. This limitation can be remedied by using hierarchical symbolic analysis techniques. Second, the SPMs in this chapter are limited to modeling AC behavior of benchmark circuits. With recent progress in symbolic analysis of circuits exhibiting hard non-linearity, this technique can be extended to non-linear circuits and models and ultimately to the automatic synthesis of RF circuits.

53 Chapter 5

RF Low Noise Ampliﬁer Synthesis

The traditional circuit synthesis process when applied to radio-frequency (RF) circuits, suffers from the same two shortcomings which have been mentioned for analog circuits. How- ever, the layout parasitics effects are much more pronounced in RF circuits. As mentioned earlier, the problem of performance degradation due to layout parasitics can be alleviated by either layout-aware or layout-in-loop circuit synthesis. While layout-aware techniques offer fast timing closure, the parasitics are difﬁcult, and often impossible, to estimate accurately. In layout-in-loop synthesis, layout generation and extraction is done within the synthesis loop with the hope of capturing the parasitic effects accurately. Several attempts have been made to synthesize RF circuits using layout-aware and layout-in-loop techniques, but none of them consider the full extraction of circuits including the metallic interconnects [14, 22, 75, 77]. The problem of computationally intensive numerical simulations can be avoided to an extent by using circuit performance models for estimating the behavior of a particular design. A similar approach was presented in Chapter 4, but it is limited to linear analog circuit synthesis and the parasitic-inclusion techniques are relevant only to rule-based extractors. This chapter presents a synthesis methodology for nonlinear RF LNA circuits along with techniques for the inclusion of high-frequency quasi-static layout effects into the SPMs. The rest of the chapter is organized as follows. The proposed method is described in Section 5.1 and techniques to include layout effects in the SPMs in Section 5.2. Experimental results are presented in Section 5.3 and conclusions in Section 5.4.

54 5.1 Proposed RF Circuit Synthesis Method

The proposed RF circuit synthesis environment is shown in Figure 5.1. The Module Specification Language(MSL) system [47] is used for layout generation. This is a language- based layout generation system, which produces a parameterized layout generator from the placement and/or routing description of any circuit under consideration. The layout generator thus obtained is instantiated in every synthesis iteration using the devices sizes furnished by the optimization engine. Since only an instantiation step is involved the layouts are generated very fast. The core of the optimization engine is the simulated annealing algorithm. The layout instantiation step is followed a multi-way extraction. In order to extract the high-frequency parasitics associated with the interconnects as well as on-chip inductors, relevant components of the layout are passed onto a quasi-static extractor. In a parallel step, the parasitic capacitances associated with interconnects, on-chip inductors and on-chip capacitors are extracted using rule-based extractors. Transistors and their parasitics are also extracted using rule-based extractor albeit separately. This extraction step is followed by a netlist postprocessing step where the netlist of extracted parasitics is sorted and compacted. A map of parasitic values which is eventually used in the evaluation of symbolic performance models is also generated in this step. In our method symbolic performance models (SPMs) are used to judge if the devices sizes proposed by the optimization engine meets the desired specifications. These models are generated only once before the start of synthesis (similar to the parameterized layout generator) and are repetitively evaluated during synthesis. During the evaluation step, SPMs use small- signal values for active devices and a set of non-linearity coefficients. These are generated during the numerical analysis step shown in the figure. Once the performance estimates have been obtained the optimization engine (if required) proposes a new set of circuit parameter values (device sizes). These values are again fed to the layout generator to instantiate a physical layout. The process continues till the optimization algorithm converges to a design which is near optimum and satisfies all the performance constraints. The detailed description of each step follows.

5.1.1 Layout Generation and Instantiation

The MSL system [47] is used to generate parameterized layouts. MSL contains construct for hierarchical instantiation and relative placement of modules and for deﬁning parameterized

55 Optimization SPM Engine Evaluation

Layout Numerical Instantiation Analysis

Multi−Way Post− Extraction Processing

MSL SPM System Generator

Figure 5.1: Proposed RF Synthesis Approach nets for routing. When compiled an MSL program yields an executable layout generator which can be quickly elaborated into a concrete layout, when concrete size information is available from the optimization engine. A library of parameterized module generators, including ﬁn- gered transistors, differential pairs, current mirrors, resistors, capacitors,inductors etc, has been developed in MSL.

5.1.2 Multi-way Layout Extraction

A multi-way layout extraction, for LNA circuits is done by strategically avoiding replica- tion or aliasing of node and by preserving the continuity of the resultant netlist [5]. The final netlist is obtained by merging all the netlists generated by rule-based and quasi-static extractors. Rule-based Extraction: The rule-based extractor is used to extract the parasitics of active devices and the capacitances of on-chip inductors, capacitors and interconnects. First the active devices (transistors) are extracted by using a rule-based methodology. The result is a netlist file which contains the diffusion capacitances of the fingered transistors and the parasitic capacitances of the intra-modular interconnects. Then the intrinsic capacitance of the on-chip MiM capacitors are extracted by the rule-based method along with the parasitic capacitances of on-chip inductors, interconnects skeleton and poly-resistors. This produces another netlist file where the extracted capacitances are lumped at each node. The rule-based extractor used in our experimentation is the standard MAGIC extractor.

56 Quasi-Static Extraction: The layout devoid of active devices, MiM capacitors and poly- resistors is passed through a quasi-static extractor. This tool extracts the resistances and inductances of the metallic interconnects and on-chip inductors and outputs another netlist. The extractor used here is part of the VPEC software suite [8] for inductance extraction and sparsifi- cation. An efficient inductance calculator, based on the quasi-static limit which usually matches FastHenry results within a few percent accuracy is used . In this work we did not account for skin effect in the wires, because the cross section of the wires is smaller than the skin depth at the frequencies under consideration. VPEC does not extract the capacitance of the interconnects or the on-chip inductors, but this deficiency is obviated by merging the extracted netlist with the result of the rule-based extraction described above.

5.1.3 Post Processing of Extracted Netlists

In order to be amenable to symbolic methods, the extracted netlists have to be compacted, especially after VPEC extraction. Internally VPEC uses a program called xray to extract the wireframe representation of the layout from its flat version. The wireframes in essence represent the geometry of a layout and are eventually used by the VPEC extractor to obtain the parasitic netlist. Each segment in the wireframe is extracted as an Voltage-Resistance-Inductance (VRL) segment. Since, xray supports three-dimensional (multilevel) interconnect, each level is extracted separately but is connected through vertical wires (representing vias and contacts) to other segments. The vias and contacts are also extracted and appear in the final netlist. Due to the thorough extraction technique used by VPEC, the number of parasitic elements extracted explode in number. Conceptually it becomes difficult to capture the complete set of parasitics generated in all iterations, before the generation of SPMs. Moreover, symbolic analysis, the cornerstone of symbolic performance modeling, is incapable of handling such huge circuits. In case of the Low Noise Amplifier shown in figure 5.6, the five interconnects are extracted as 96 VRL segments. Such a scenario makes it necessary to post process the extracted parasitic netlist. The first step, is sorting the netlist. In the netlist generated by VPEC, the different segments of a net are spread all over and are not bunched together. For proper extraction of parasitic values it is essential that the segments be sorted. The net segments are therefore sorted according to their net affiliations. This is done by scanning the terminal nodes of each net segment and linking it with an earlier segment. Each net is thus stored as an acyclic graph, with vertices representing the nodes and the edges the impedance of a segment. This graphical representa-

57 tion of a net is then compacted by merging circuit parasitics which are in series with each other. This entails removal of a vertex with only one edge originating from it and connecting its child vertex to its parent vertex, while lumping the vertex’s impedance with that of the child vertex. Due to this representation it becomes easy to generate the map of parasitic values used by SPMs and also to generate the complete compacted netlist for later simulations.

5.1.4 High-Frequency Symbolic Performance Models

Symbolic performance models (SPMs) are symbolic equations in terms of circuit parameters that represent the performance metrics of an analog circuit. An SPM is built using one or more symbolic transfer functions and a symbolic mathematical formula (performance model) which represents the relationship between a performance characteristic and the transfer functions. In circuit synthesis, SPMs are used for repetitive performance estimation during the optimization iterations. Unlike numerical simulators, analysis is not done in every iteration and only evaluation of the SPMs is needed. This results in a significant speedup of the performance estimation time. At radio-frequencies the circuit is very susceptible to noise and distortion, therefore the following performance characteristics are optimized: gain, noise figure and the distortion parameters (HD2 & HD3). The following subsections describe the process of obtaining noise figure and distortion SPMs and process of symbolic analysis.

Noise Figure

The generation of Noise Figure SPM is similar to the one attempted in [89], but our approach extends this technique to the modeling of noise ﬁgure rather than just spectral noise density. Moreover, instead of using a DDD approach with evaluation in memory we have used pre-compiled ECDs to represent the transfer functions.

Distortion Parameters

The symbolic formulae for distortion and intermodulation products of RF circuits are obtained through a Volterra-series based method [95]. In short, the behavior of the nonlinear circuit elements is described using a multi-dimensional Taylor series, which is truncated after the 3rd order terms. While in general this truncation is not necessarily sufﬁciently accurate, for the application towards RF circuits this poses no problems. Using the further assumption that higher order terms are negligible in the computation of lower order ones - which is also

58 fair to assume for RF circuits - the circuit can effectively be composed in a number of circuits, each of which models the behavior at a frequency which is a linear combination of the input frequencies. The construction of this models using the simplifying assumptions does not need to be repeated for each new circuit. An analysis of these effects using the general Kirchhoff laws allows us to derive a number of stamps that model the behavior of (trans)conductances and capacitances for an effect of a given order. An incremental substitution of the circuit elements by these stamps leads to a set of models in which only the linear interactions between the terminals of the nonlinear elements still need to be computed. These linear transfer functions are obtained as described above, and modeled as ECDs. The SPM resulting from the Volterra based analysis consists of a postprocessing function combining the components at appropriate frequencies of a number of in- and output voltages and/or currents, which themselves are modeled using a hierarchy of expressions containing linear transfer functions (modeled using ECDs) and nonlinearity coefﬁcients only. Just as is the case with the evaluation of the ECDs these SPMs depend on the topology only and need to be constructed only once. The evaluation of the SPMs additionally requires numerical values for the nonlinearity coefﬁcients, which can be obtained using either numerical postprocessing of a operating point simulation, or through models. Since no accurate model equations are available to us, we have opted for the numerical nonlinearity calculation.

Symbolic Analysis and Pre-Compiled ECDs

The core of this SPM generation process is symbolic analysis. Symbolic analysis is a formal technique used to obtain network transfer functions in terms of symbolic circuit parameters and independent variables like frequency [43]. In circuit synthesis it is essential that the SPMs are not approximate, require minimum space, are fast to evaluate and are stored in the s-polynomial format [83]. In this chapter we use Element-Coefﬁcient Diagrams (ECDs) to represent a symbolic transfer function. The process of ECD-based symbolic analysis is described in [93]. In our work the ECDs are converted to C++ code and then compiled. The use of pre- compiled ECDs reduces the SPM evaluation time considerably. An signiﬁcant average speedup (by a factor of 30), with respect to evaluation of ECDs stored in memory, is observed for for the transfer functions of the benchmark circuit.

59 5.2 Inclusion of Layout Effects in SPMs

R L Vs

Ic1 Ic2

C1 I1 C2 I2

Figure 5.2: PEEC Model

The perturbation of component sizes during synthesis causes variations in the layout geometry between iterations. These variations may generate varying sets of parasitic elements (resistances, capacitances and inductances) in each iteration. The variation of width of a transistor module also causes the number of ﬁngers to change between iterations. In this section we talk about techniques to model these variations in the original circuit topology, which in turn generates parasitic-inclusive SPMs. a a

b c b c

Figure 5.3: Illustration of parasitic extraction

The inclusion of parasitic capacitances for active components obtained by rule based extraction can be done using analysis-based inclusion technique proposed by us in [71]. The set of parasitics generated for every segment of an interconnect is in the form of the PEEC Model [6] shown in Figure 5.2. The extracted circuit for a three terminal net is shown in Figure 5.3. Note that the voltage and current sources of the PEEC Model are not included in the circuit as

60 the evaluation of SPMs is independent of the process of biasing a circuit. a

Z1 = Z3 = Z4 = Z7 = Inf.

a b c Z1 = Z2 = Z4 = Inf. a CaseA Z5 = Z7 = 0 a Z1 Z3 Z2 Z6 = 0; Z2 = Z3 = Z7 = Inf. b c Z4 Z5 Z6 Z7 Case D c a b Z8 Z9 Case B Z4 = Z6 = 0 b c Z2 = Z3 = Z7 = Inf. b c Z5 = 0; Z1 = Z2 = Z4 = Inf. Case E b c Case C

Figure 5.4: Illustration of parasitic inclusion in SPMs

For multi-terminal nets the number of parasitic elements extracted in different iterations may not be the same. This is because the pin positions change and this causes the nets geometry to change. Figure 5.4 shows a multi-terminal net with one terminal on the top row and two terminals on the bottom row and the ﬁve possible net geometries. Based on the relative x- coordinate of node a, a(x) with respect to b(x) and c(x), the number and position of parasitics extracted vary. To model these variations a complete parasitic model, which is a superset of all possible combinations (shown in the center of Figure 5.4), is included in the original circuit description which is eventually used to generate the SPMs. The actual evaluation of the SPMs is done by determining the relative coordinates of the critical nodes (a,b,c in this example) and setting the value of some resistances and conductances to zero. Figure 5.5 shows another example of a parasitic model for a net with two upper terminals and three lower terminals. This parasitic modeling technique can easily be extended to nets with m terminals on the top row and n terminals at the bottom row.

61 a b

Z1 Z3 Z2

Z4 Z6 Z9 Z11

Z5 Z10 Z7 Z8

Z12 Z13 Z14 Z15 Z16 Z17 Z18 Z19 Z20 Z21

Z22 Z23 Z24 c d e

Figure 5.5: Larger example of a parasitic model

vdd

R1 L2 Vdd

vdd! V0 M2 + M0 C0 r=50 − Vdc=3.3V gnd PORT1

R0 M1 c=10pF L1 C1 .

r=50

PORT0

Figure 5.6: Low Noise Ampliﬁer Topology 5.3 Experimental Results

5.3.1 Setup

The LNA in Figure 5.6 is chosen to demonstrate the proposed RF circuit synthesis method. In this circuit the input & outputs are matched at 50Ω and the width of transistors M0 & M1 are equal. The equal widths enable the merging of the drain of M0 with the source of M1, which in turn reduces the internal noise of the cascode transistor M1 and facilitates input matching [63]. The width of transistor M2 (which forms a current mirror with M1) is chosen to be one-tenth of the width of M1. This minimizes the power consumption in the bias circuit [63]. The large input blocking capacitance is off-chip and its value is ﬁxed at 10pF. The SA-based optimizer

62 Table 5.1: Synthesis Results for Low-Noise Ampliﬁer Performance Performance Synthesis HSpice Percentage Attribute Constraints Results Verﬁcation Error Gain ≥ 15 dB 16.565 dB 16.548 0.102 % NF ≤ 3 dB 2.754 dB 2.90 5.03 % HD2 ≤ -25 dB -26.239 dB - - HD3 ≤ -20 dB -20.782 dB - - explores the search space for these seven design variables: M1.W, L0, L1, L2, R0, R1 and C0. The TSMC 0.18µ technology is used and all simulations are run on SunBlade1000 with 2GB RAM.

5.3.2 Results and Discussion

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Figure 5.7: Layout of the Single-ended LNA

The SPM generation process for the circuit described above took around 45 minutes, out of which the ECD generation time was 16 minutes 34 seconds and ECD compilation time was 26 minutes 23 seconds. The number of ECDs required for H2 are 9; for H3 are 31 and for noise figure are 8. So a total of 49 ECDs were generated and compiled (including 1 ECD for gain). The single-ended LNA was synthesized for gain, H2, H3 and noise figure at a frequency of 2.1 GHz. The results are presented in table 5.1. When compared to a numerical simulator the accuracy for gain was within 0.1%, for noise figure within 5%. The slight inaccuracy in noise

63 figure arises because we do not consider all sources of noise but only the important ones, the thermal noise due to the transistors’ channel resistances and circuit resistances. The accuracy of H2 & H3 is discussed in details in [95]. The inaccuracy in H2 & H3 arises from two sources. First, is due to the fundamental assumptions associated with weakly non-linear symbolic analysis. The other source of inaccuracy is due to the use of non-linearity coefficients which are obtained by interpolation the operating point results. The accuracy can be improved by using a tighter grid but of course that would slow down the process significantly. The total synthesis time was 13 hours. Each iteration time is 26.04s, out of which layout generation time is 1.1s, layout extraction time is 8.67s and performance estimation time is 16.23s. Figure 5.7 shows a layout obtained after synthesis.

5.4 Conclusions

The chapter has presented a new method for RF LNA synthesis using quasi-static extraction and symbolic performance models. The novelty of the approach is the use of ECD-based symbolic performance models for RF layout-in-loop synthesis. The synthesis method can be improved signiﬁcantly in terms of speed by calculating non-linearity coefﬁcients using biasing voltages and model parameters of active components instead of numerical interpolations.

64 Chapter 6

Exact Hierarchical Symbolic Analysis of Large Analog Circuits

6.1 Introduction & Related Work

The process of determining numerical values for the unsized elements of an analog circuit, while satisfying a set of performance constraints, is called circuit synthesis. Traditional analog synthesis methods [42] suffer from two important shortcomings - a) unawareness to the layout parasitics and b) computationally expensive numerical analysis for performance estimation. Not estimating layout-effects during optimization can lead to the failure of the synthesized circuit in the post-layout verification stage. Numerical simulation inside the synthesis loop results in large per-iteration time, as well as, large synthesis time. These deficiencies can be alleviated by using layout-inclusive techniques along with symbolic analysis based performance models. In layout-inclusive synthesis a complete layout is either generated or instantiated inside the synthesis loop. This technique is also called the layout-in-loop approach. Symbolic performance models (SPMs) are symbolic equations in terms of circuit parameters, which represent the characteristics of an analog circuit [43, 30, 71]. SPMs are built using symbolic transfer functions obtained by symbolic circuit analysis. When SPMs are used in a layout-inclusive flow, they have an inherent advantage over other performance modeling methods because, they can be generated extremely fast and can also model each parasitic element as variables [71]. In [71] a synthesis method combining the concepts of layout-inclusion and SPMs is presented. Layout generation is included in the synthesis loop by using a parameterized layout generator. SPMs are generated using the symbolic analysis method based on element-coefficient

65 diagrams (ECDs). ECD’s are graph-based data structures which store exact (no approxima- tions) transfer functions expressions compactly and were first presented in [84, 92]. For use in synthesis the ECDs are converted into C++ code and compiled for extremely fast evaluation. In such a synthesis method parasitic-inclusive topologies have to be used for ECD generation, in order to capture the layout effects. Even for medium sized analog circuits, due to inclusion of parasitic elements, topologies becomes very complex. The synthesis methodology in works well for small and medium sized analog circuits, but as the size of circuits increase it is difficult to compile and eventually to generate the ECD code. For even larger circuits symbolic technique fails to generate the ECDs. To overcome the limitation on the size of circuits, a hierarchical symbolic analysis approach has to be used. Techniques involving approximation/simplification cannot be used because in synthesis the accuracy of performance models is of paramount importance - SPMs have to be valid for the entire design space and therefore cannot be approximated. Other important criteria for SPMs used in circuit synthesis are: easy conversion of transfer functions in the s-expanded form [84, 92]; conversion of the s-expanded form into efficient C++ code; and the fast compilation of the C++ code. The s-expanded form ensures that the same design point can be evaluated over multiple frequencies without evaluating the coefficients of the transfer function several times. The transfer function have to be converted to C++ code and compiled to ensure fast evaluation during synthesis iterations. In addition to the features mentioned above, it is very advantageous to develop a reusable library-based method which can use pre-compiled transfer functions of common analog modules. Several hierarchical methods were examined and none of them satisfy all criteria for generation of SPMs to be use in circuit synthesis. Two relevant and promising hierarchical methods are: DDD-based [87, 35] and network approach (based on sequence of expressions and reduced MNA) [50]. These methods are not suitable because, it is difficult to convert the resulting transfer functions to the s-expanded format. Moreover the size of circuits with the inclusion of parasitics is very large, which is outside the scope of these approaches. A method, where subcircuits transfer functions (TFs) are combined to yield the TFs for a higher level circuit, is preferable. Only then can the modular properties of topologies obtained from layouts be exploited. In [25] a regularity-based approach is proposed, but it breaks down the circuit to the smallest, most basic, elements. This approach also does not correspond directly to the layout, which uses the common analog modules. A technique based on decomposition and circuit function generation is presented [24], but is limited to small circuits because it does not present a formal method

66 which can be used for large circuits. Moreover none of these methods can be easily manipulated to obtain the s-expanded format. It remains unclear if the methods mentioned above can be converted to C++ code and compiled. In addition, none of the methods can support a transfer function based library approach. In this chapter we present a new hierarchical symbolic analysis method based on the use of a general interconnection template (GIT). The GIT represents all possible ways to connect two subcircuits. A complete analysis of the GIT is done using the principles of transfer function synthesis. The transfer functions which completely characterize the GIT are thus obtained from the transfer functions of the two general subcircuits. The complete analysis of the GIT is presented in the chapter. These results can directly be used by a person who intends to use the method. This hierarchical analysis method takes as input a partitioned circuit. The rest of the chapter is organized as follows. In Section 6.2 the GIT is introduced and completely analyzed. The hierarchical symbolic analysis method, with GIT results as its core, is described in Section 6.3. Also presented in this section is the complete implementation framework. Experimental results are presented in Section 6.4 and conclusions in Section 6.5.

6.2 General Interconnection Template (GIT)

This section introduces the concept of the general interconnection template (GIT). The ﬁrst part describes the way to characterize circuits in terms of circuit functions (transfer functions). In the second part, the GIT is introduced and then thoroughly analyzed. Transfer functions are synthesized for the larger subcircuit of the GIT, which is formed by merging the smaller subcircuits. The two main results which are derived are: the circuit function matrices, and the formulae for transfer function synthesis of a GIT. It is very important to derive these results because, they form the backbone of the hierarchical analysis method to be proposed in Section 3. These results are used directly and eliminate the need to go through a similar analysis at every level of hierarchy.

6.2.1 Subcircuit Characterization

Each subcircuit can be characterized by its circuit functions [24]. Circuit functions are equations that represent the relationship between a pair of port variables (voltages/currents). In this work, the terms circuit functions and transfer function refer to the same thing and are used interchangeably. In each subcircuit some ports are described by voltages and some by currents.

67 i j v 1 1 1 V 1 v i j SUBCKT_ SUBCKT_ V v V x i j y x y Figure 6.1: (a) Subcircuit (b) Compact Representation

Figure 6.1.a shows an example subcircuit with x + y number of ports, with x ports described by current equations and y ports described by voltage equations. The following equations are the equations characterizing each port variable.

x y im = ∑ ym,rvr + ∑ βm,s js ; m = 1,.....,x r=1 s=1

x y Vn = ∑ µn,rvr + ∑ zn,s js ; n = 1,...... ,y r=1 s=1

The parameters ym,r, βm,s, µn,r, zn,s, are circuit functions (or transfer functions) and in this work are symbolic.

im ym,r = |vr=1; vu=0 (u6=r; u=1,...,x); jv=0 (v=1,...,y); m = 1,...,x; r = 1,...,x vr β im m,s = | js=1; jv=0 (v6=s; v=1,...,y); vu=0 (u=1,...,x); m = 1,...,x; s = 1,...,y js Vn µn,r = |vr=1; vu=0 (u6=r; u=1,...,x); jv=0 (v=1,...,y); n = 1,...,y; r = 1,...,x vr Vn zn,s = | js=1; jv=0 (v6=s; v=1,...,y); vu=0 (u=1,...,x); n = 1,...,y; s = 1,...,y js Figure 6.1.b is the compact representation of a subcircuit, where all primary current and voltage variables are represented as vectors i and v. The compact matrix representation of circuit characteristic equations is obtained from Figure 6.1.b and is shown below:

     ix Yx Bx vx   =    Vx Ux Zx jx

Here, ix & jx are current variable matrices and vx & Vx are the voltage variable matrices. The equation above can also be presented as:

Mx = Hx × Nx

68 The matrix Mx is the set of primary variables characterizing a port and Nx is the set of secondary variables. Subscript x represents the subcircuit x which is being characterized. Hx is the circuit function matrix, members of which are obtained by symbolic analysis of the the two subcircuits being merged. i i v e i e v i j SUBCKT_ j e i V V e i

Figure 6.2: Internal External Variables

When two subcircuits are merged to form a higher-level subcircuit then the interconnection ports (ports common to both the subcircuits) are represented as internal variables and the remaining ports are classiﬁed as external. Figure 6.2 shows a subcircuit characterized by internal and external port variables. Any internal interconnection port on a subcircuit has the same voltage as its counterpart in the subcircuit to its parent subcircuit is connected to and also satis- ﬁes the KCL. The compact matrix representation with internal and external variables separated is presented below:

     ix Yx Yx Bx Bx vx  i   ii ie ii ie  i        ix  Yx Yx Bx Bx vx  e   ei ee ei ee e   =    Vx Ux Ux Zx Zx jx   i   ii ie ii ie  i  x x x x x x Ve Uei Uee Zei Zee je

6.2.2 GIT Transfer Function Synthesis

When two subcircuits are merged, the primary goal is to ﬁnd the circuit function matrix of this new subcircuit/circuit, in terms of circuit functions of the constituting blocks. Two subcircuits can be connected to each other in various connection templates, whether it be series, parallel, feedback or any combination of these. In this work, a connection template which encompasses all such connections between any two subcircuits, is proposed, and is called the general interconnection template or GIT (Figure 6.3. The GIT is then completely analyzed symbolically using KCL, KVL and matrix algebra. Several circuit functions matrices are derived, as well formulae to to obtain the transfer functions of the larger block. The results obtained from

69 this analysis is used for analyzing any type of connection, by simply eliminating the variables which do not exist. The whole process is described, in details, below.

a b b a i i i i i 2 c c i1 i 2 i1 i ie 1 a b e 3 i b i c c e a i B e i a j i e 2 i 2 i 3 b e 4 c j j c e A b e Ve a e b Ve 3 1 j i i j c i1 i 3 i 4 i c V c c V e 2 j j e 4 e 2 e 4

Figure 6.3: General Interconnection Template

From Figure 6.3 the characteristic equations for subcircuit A are:      ia Ya Ya Ya Ya Ba Ba Ba va  i1   i1i1 i1i2 i1i3 i1e i1i1 i1i2 i1e i1        ia  Ya Ya Ya Ya Ba Ba Ba va   i2   i2i1 i2i2 i2i3 i2e i2i1 i2i2 i2e i2        ia  Ya Ya Ya Ya Ba Ba Ba va   i3   i3i1 i3i2 i3i3 i3e i3i1 i3i2 i3e i3        ia  = Ya Ya Ya Ya Ba Ba Ba va   e   ei1 ei2 ei3 ee ei1 ei2 ee  e       Va  Ua Ua Ua Ua Za Za Za ja   i1   i1i1 i1i2 i1i3 i1e i1i1 i1i2 i1e i1       Va  Ua Ua Ua Ua Za Za Za ja   i2   i2i1 i2i2 i2i3 i2e i2i1 i2i2 i2e i2  Va Ua Ua Ua Ua Za Za Za ja e ei1 ei2 ei3 ee ei1 ei2 ee e

⇒ Ma = Ha × Na

All the circuit functions in the matrix Ha are obtained either by repeated symbolic analysis according to the deﬁnition of the circuit functions or have been generated by merging two subcircuits.

70 Similarly, the characteristic equations for subcircuit B are:      ib Yb Yb Yb Yb Yb Bb Bb vb  i1   i1i1 i1i2 i1i3 i1i4 i1e i1i i1e i1        ib  Yb Yb Yb Yb Yb Bb Bb vb   i2   i2i1 i2i2 i2i3 i2i4 i2e i2i i2e i2        ib  Yb Yb Yb Yb Yb Bb Bb vb   i3   i3i1 i3i2 i3i3 i3i4 i3e i3i i3e i3        ib  = Yb Yb Yb Yb Yb Bb Bb vb   i4   i4i1 i4i2 i4i3 i4i4 i4e i4i i4e i4        ib  Yb Yb Yb Yb Yb Bb Bb vb   e   ei1 ei2 ei3 ei4 ee ei ee  e       Vb  Ub Ub Ub Ub Ub Zb Zb  jb   i   ii1 ii2 ii3 ii4 ie ii ie  i  Vb Ub Ub Ub Ub Ub Zb Zb jb e ei1 ei2 ei3 ei4 ee ei ee e

⇒ Mb = Hb × Nb

Please note the differences in matrices Mb, Hb and Nb, from the matrices of subcircuit A. The key to the synthesis of circuit functions of the new subcircuit/circuit C (which is obtained by merging A and B) is to devise an efﬁcient mathematical procedure of deriving the circuit function matrix Hc . The characteristic equations of subcircuit C are represented as:

Mc = Hc × Nc

In the general interconnection template it is assumed that the subcircuit C is characterized only by external variables. Therefore the compact representation is:      ic Yc Yc Yc Yc Bc Bc Bc Bc vc  e1   e1e1 e1e2 e1e3 e1e4 e1e1 e1e2 e1e3 e1e4  e1        ic  Yc Yc Yc Yc Bc Bc Bc Bc vc   e2   e2e1 e2e2 e2e3 e2e4 e2e1 e2e2 e2e3 e2e4  e2        ic  Yc Yc Yc Yc Bc Bc Bc Bc vc   e3   e3e1 e3e2 e3e3 e3e4 e3e1 e3e2 e3e3 e3e4  e3        ic  Yc Yc Yc Yc Bc Bc Bc Bc vc   e4   e4e1 e4e2 e4e3 e4e4 e4e1 e4e2 e4e3 e4e4  e4    =    Vc  Uc Uc Uc Uc Zc Zc Zc Zc jc   e1   e1e1 e1e2 e1e3 e1e4 e1e1 e1e2 e1e3 e1e4  e1       Vc  Uc Uc Uc Uc Zc Zc Zc Zc jc   e2   e2e1 e2e2 e2e3 e2e4 e2e1 e2e2 e2e3 e2e4  e2       Vc  Uc Uc Uc Uc Zc Zc Zc Zc jc   e3   e3e1 e3e2 e3e3 e3e4 e3e1 e3e2 e3e3 e3e4  e3  Vc Uc Uc Uc Uc Zc Zc Zc Zc jc e4 e4e1 e4e2 e4e3 e4e4 e4e1 e4e2 e4e3 e4e4 e4

From Figure 6.3 based on KCL and KVL we derive the following relations: va = i1 vc ; va = vc ; va = V c ; va = vc ; ja = jc + ib ; ja = ib ; ja = jc . Also vb = vc ; vb = e1 i2 e3 i2 e4 e e2 i1 e2 i4 i2 i3 e e1 i1 e3 i2 vc ; vb = V a; vb = V c ; vb = vc ; jb = jc + ia ; jb = jc e1 i3 i2 i4 e2 e e4 i e4 i3 e e3

71 In order to obtain Hc, the primary internal variables of both subcircuits A and B have to eliminated. The ﬁrst step in that direction is the separation of the circuit functions associated with internal variables into a separate matrix Aab. The equation resulting is shown below.

   I 0 0 0 0 −Ba −Ba 0 0 0 ia  i1i2 i1i1  i1     0 I 0 0 0 −Ba −Ba 0 0 0 ia   i2i2 i2i1  i2     0 0 I 0 0 −Ba −Ba 0 0 0 ia   i3i2 i3i1  i3     0 0 −Bb I 0 0 0 0 −Yb 0 ib   i1i i1i3  i1     0 0 −Bb 0 I 0 0 0 −Yb 0 ib   i2i i2i3  i2     0 0 −Bb 0 0 I 0 0 −Yb 0 ib   i3i i3i3  i3     0 0 −Bb 0 0 0 I 0 −Yb 0 ib   i4i i4i3  i4     0 0 0 0 0 −Za −Za I 0 0Va   i1i2 i1i1  i1     0 0 0 0 0 −Za −Za 0 I 0Va   i2i2 i2i1  i2  0 0 −Zb 0 0 0 0 0 −Ub I Vb ii ii3 i   0 0 0 0 0 0 0 Ya  i1i3     0 0 0 0 0 0 0 Ya  ic  i2i3  e1     0 0 0 0 0 0 0 Ya  ic   i3i3  e2     0 0 0 0 0 Yb 0 0  ic   i1i4  e3     0 0 0 0 0 Yb 0 0  ic   i2i4  e4  =   + 0 0 0 0 0 Yb 0 0 Vc   i3i4  e1     0 0 0 0 0 Yb 0 0 Vc   i4i4  e2     0 0 0 0 0 0 0 Ua Vc   i1i3  e3    0 0 0 0 0 0 0 Ua  Vc  i2i3  e4 0 0 0 0 0 Ub 0 0 ii4

72   Ya Ya Ya 0 Ba Bb 0 0  i1i1 i1e i1i2 i1e i1i1     Ya Ya Ya 0 Ba Bb 0 0  vc  i2i1 i2e i2i2 i2e i2i1  e1     Ya Ya Ya 0 Ba Bb 0 0 vc   i3i1 i3e i3i2 i3e i3i1  e2     Yb 0 Yb Yb 0 0 Bb Bb vc   i1i2 i1i1 i1e i1e i1i e3     Yb 0 Yb Yb 0 0 Bb Bb vc   i2i2 i2i1 i2e i2e i2i e4     (6.1) Yb 0 Yb Yb 0 0 Bb Bb jc   i3i2 i3i1 i3e i3e i3i e1     Yb 0 Yb Yb 0 0 Bb Bb jc   i4i2 i4i1 i4e i4e i4i e2     Ua Ua Ua 0 Za Zb 0 0 jc   i1i1 i1e i1i2 i1e i1i1  e3    Ua Ua Ua 0 Za Zb 0 0  jc  i2i1 i2e i2i2 i2e i2i1  e4 Ub 0 Ub Ub 0 0 Zb Zb ii2 ii1 ie ie ii

⇒ Aab × Pab = Bab × Mc + Cab × Nc

-1 ⇒ Pab = Aab × (Bab × Mc + Cab × Nc) (6.2)

The characteristic equations of the new subcircuit C can be formed by substituting the primary external variables of C by internal and external variables of the constituting subcircuits based obviously on KCL and KVL. The equation resulting from this equation is shown below.

       ic ia + ib 0 0 0 0 0 Yb 0 Ya ic  e1   i1 i2   i2i4 i1i3  e1          ic   ia  0 0 0 0 0 0 0 Ya  ic   e2   e   ei3  e2          ic  ia + ib  0 0 0 0 0 Yb 0 Ya  ic   e3   i2 i1   i1i4 i2i3  e3          ic   ib  0 0 0 0 0 Yb 0 0  ic   e4   e   i1i4  e4    =   =   + Vc   Va  0 0 0 0 0 0 0 Ua Vc   e1   e   ei3  e1         Vc   Va  0 0 0 0 0 0 0 Ua Vc   e2   i1   i1i3  e2         Vc   Vb  0 0 0 0 0 Ub 0 0 Vc   e3   e   ei4  e3  Vc Vb 0 0 0 0 0 Ub 0 0 Vc e4 i ii4 e4

73    Ya + Yb Ya Ya + Yb Yb Ba Ba Bb Bb vc  i1i1 i2i2 i1e i1i2 i2i1 i2e i1e i1i1 i2e i2i e1      Ya Ya Ya 0 Ba Ba 0 0 vc   ei1 ee ei2 ee ei1  e2     Ya + Yb Ya Ya + Yb Yb Ba Ba Bb Bb vc   i2i1 i1i2 i2e i2i2 i1i1 i1e i2e i2i1 i1e i1i e3      Yb 0 Yb Yb 0 0 Bb Bb vc   ei2 ei1 ee ee ei  e4      Ua Ua Ua 0 Za Za 0 0 jc   ei1 ee ei2 ee ei1  e1      Ua Ua Ua 0 Za Za 0 0 jc   i1i1 i1e i1i2 i1e i1i1  e2      Ub 0 Ub Ub 0 0 Zb Zb jc   ei2 ei1 ee ee ei  e3  Ub 0 Ub Ub 0 0 Zb Zb jc ii2 ii1 ie ie ii e4   ia   i1    0 0 Bb 0 0 Ba Ba 0 Yb 0  ia   i2i i1i2 i1i1 i2i3  i2     0 0 0 0 0 Ba Ba 0 0 0 ia   ei2 ei1  i3     0 0 Bb 0 0 Ba Ba 0 Yb 0 ib   i1i i2i2 i2i1 i1i3  i1     0 0 Bb 0 0 0 0 0 Yb 0 ib   ei ei3  i2  +   (6.3) 0 0 0 0 0 Za Za 0 0 0 ib   ei2 ei1  i3     0 0 0 0 0 Za Za 0 0 0 ib   i1i2 i1i1  i4     0 0 Zb 0 0 0 0 0 Ub 0Va   ei ei3  i1    0 0 Zb 0 0 0 0 0 Ub 0 Va  ii ii3  i2  b Vi

⇒ Mc = Dab × Mc + Eab × Nc + Fab × Pab (6.4)

As can be seen equation 6.4 still has the internal variable matrix Pab. In order to eliminate this and get equations is terms of external variables (and hence current and voltage variables of subcircuit C), we plug in equation 6.2 in the equation 6.4. This results in the following equation:

-1 Mc = Dab × Mc + Eab × Nc + Fab × Aab × (Bab × Mc + Cab × Nc)

³ ´ ³ ´ -1 -1 ⇒ I − Dab − Fab × Aab × Bab × Mc = Eab + Fab × Aab × Cab × Nc

74 ³ ´-1 ³ ´ -1 -1 ⇒ Mc = [ I − Dab − Fab × Aab × Bab × Eab + Fab × Aab × Cab ] × Nc

³ ´-1 ³ ´ -1 -1 ∴ Hc = I − Dab − Fab × Aab × Bab × Eab + Fab × Aab × Cab (6.5)

Thus we have a formal method of obtaining the circuit function matrix of the new subcircuit/circuit based on symbolic matrix calculations. This formal method is easy to implement and forms the basis of a hierarchical symbolic analysis method. A bottom-up approach is used to combine subcircuits till the highest level of hierarchy is reached.

6.3 Proposed Hierarchical Symbolic Analysis Method

In this section we discuss the proposed hierarchical analysis method. Some important steps and transformations, carried out at ever level of hierarchy, are also discussed here. In this method, the assumption is that, the circuit to be analyzed is already decomposed into smaller subcircuits. It is also assumed that a hierarchical description linking various subcircuits is available. As is shown in Figure 6.4, the subcircuit/ top circuit obtained by merging two lower-level subcircuits is referred to as parent C. The two subcircuits being merged to form a bigger subcircuit/top circuit are referred to as child A and child B. The transfer functions of the leaf-level subcircuits is obtained by direct symbolic analysis and not by transfer function synthesis using lower level subcircuits. Middle-level subcircuits are obtained by merging either two other middle-level subcircuits, one middle-level and one leaf-level subcircuit or two leaf- level subcircuits. Described next are the various important steps in the proposed method.

6.3.1 Subcircuit TF-Matrix Extraction

From the general circuit-function matrices, like Aab, etc., the subcircuit TF-function matrices are obtained by eliminating the absent variables. These subcircuit-functions matrices are then expanded by replacing the compact node variables, with actual physical nodes and their variables. Thus, each node in the hierarchy tree is completely characterized with type and expanded circuit function matrices.

75 Top−Level Parent C N_y Circuit

Leaf−Level SubCircuit N_x

Child A Child B N_3 Middle−Level SubCircuit Parent C

N_1 Leaf−Level N_2 Leaf−Level SubCircuit SubCircuit

Child A Child B

Figure 6.4: Hierarchical Analysis Simple Ladder Circuit

The procedure of subcircuit TF-matrix extraction is shown on a simple 3-stage RC circuit. The intent is to synthesize the circuit functions for the three stages based on the circuit functions of one 2-stage RC ladder and one 1-stage circuit.

i 1 R1 R2 j i R3 j 1 2 3 3 3 4 4 C1 C2 C3

c i c i a j a i b j b j e 2 e i i e e 3 A B c c V v e3 e2

Figure 6.5: Circuit Function Synthesis of an RC Ladder

From the generic interconnection template, by eliminating the undesired variables, the connection template shown in Figure 6.5 is obtained. The equation necessary to completely describe the process of combining subcircuits A & B are directly obtained from equations derived in the Section 6.2.2, by eliminating the unwanted variables. The resulting equations and

76 analysis is presented. The characteristic equations of subcircuit A are:           ia Ya Ba va ia ya βa va  e  =  ee ei2  e ⇒  1  =  11 13 1 Va Ua Za ja V a µa za ja i2 i2e i2i2 i2 3 31 33 3 The characteristic equations of subcircuit B are:           ib Yb Bb vb ib yb βb vb  i3  =  i3i3 i3e i3  ⇒  3  =  33 34 3 Vb Ub Zb jb V b µb zb jb e ei3 ee e 4 43 44 4 The new circuit C, formed by merging subcircuits A & B has the following characteristic equations:

          ic Yc Bc vc ic yc βc vc  e2  =  e2e2 e2e3  e2  ⇒  1  =  11 14 1 c c c c c c c c Ve3 Ue3e2 Ze3e3 je3 V4 µ41 z44 j4 The subcircuit TF-matrices are directly obtained, from the matrices derived in Section 6.2.2, as is shown below.     I −Yb 1 −yb i3i3 33 Aab =   =   −Za I −za 1 i2i2 33         0 Bb 0 βb Ya 0 ya 0 i3e 34 ee 11 Cab =   =  ;Eab =   =   Ua 0 µa 1 0 Zb 0 zb i2e 31 ee 44       Ba 0 βa 0 0 0 ei2 13 Fab =   =  ; Bab = Dab =   0 Ub 0 µb 0 0 ei3 43

6.3.2 TF-Synthesis

After the subcircuit TF-matrices are obtained, the transfer functions are synthesized, using

Equation 6.5. In the case of the RC-ladder example, since Bab = Dab = 0, Equation 6.5 is reduced to: -1 Hc = Eab + Fab × Aab × Cab

Using the two equation for Hc we obtain the circuit functions of the new subcircuit c βc c c (y11, 14, µ41, z44) in terms of circuit functions of A & B. In this case we are presenting the c equation of just the voltage gain µ41.

77 a b c µ31 × µ43 µ41 = a b (6.6) 1 − z33 × y33

6.3.3 Subcircuit Symbolic Analysis

The method used for the formulation of symbolic analysis problem, in our work, is a matrix-based method which uses element-coefficient diagrams (ECDs), a graphical technique, to represent a symbolic determinant [92]. According to the Cramer’s rule each network transfer function is ratio of two determinants. To represent these two determinants, two ECDs are constructed. One of them represents the numerator of the transfer function and the other, denominator. The first step in obtaining an ECD from a determinant, is the construction of a determinant decision diagram (DDD) [84]. The DDD’s are then manipulated to obtain ECDs so that individual numerator and denominator coefficients can be obtained. The coefficient graphs are subvertices of the top vertex of the original DDD. The coefficient graphs are overlapping, resulting in a relatively low number of subvertices. The time and space complexity of the ECD’s is c linear with the size of the original DDD. For the RC-ladder example, if µ41 is synthesized, then a b a b the TFs µ31, µ43, z33 and y33 (Equation 6.6) would be generated by ECD-based flat symbolic analysis.

6.3.4 Implementation Framework

The proposed hierarchical symbolic analysis method, is very amenable to software implementation. As can be seen from the expressions derived earlier, this involves symbolic matrix multiplications along with matrix inversions. We have used the method described in Section 6.2.2 to develop a framework for hierarchical analysis of large analog networks and practical circuits. The concept, as described earlier, is to merge two sub-circuits at a time, till all the subcircuits have been merged to obtain the circuit (transfer) function matrix Hc of the target netlist, in terms of the transfer functions of the leaf-level subcircuits. Figure 6.6 presents the implementation framework of the proposed approach. The process of hierarchical symbolic analysis takes in as input a hierarchy description ﬁle along with the circuit function matrices of the general interconnection template. The hierarchy description ﬁle is the breakdown of the circuit being analyzed, in terms of it’s modular components. These components, in case of analog circuits, can be standard modules like current mirror, differential pair etc, or they can be simply the target circuit partitioned using an algorithm.

78 Hierarchy General Compiled Description Circuit Top_Level Function TF Matrices Create Hierarchy Compilation Tree

Characterized TF ECDs Hierarchy List of (C++) Tree Leaf−Level Sub− Sub− Generate Circuits circuits Leaf−Level MATLAB Symbolic & ECD Files Analysis Library

Matrix List of Calculation Leaf−Level Top− Files Symbolic TFs Level Top−Level TF (C++) MATLAB TF Matrix Post− Simulation Processing

Figure 6.6: Implementation Framework

This file also has the information about the sequence in which two subcircuits are combined at a time, as well as the information about nodes and variables, in a format corresponding to the general interconnection template. The general circuit function matrices are matrices like Aab, etc., obtained by rigorous mathematical derivation from the general interconnection template in Section 6.2.2. The first step is the generation of a hierarchy tree from the hierarchy-description file. The structure of this hierarchy tree is shown in Figure 6.4. Each node in this tree represents a subcircuit, and stores information about the subcircuit-type and the external nodes. From the general circuit-function matrices, the subcircuit TF-function matrices are extracted as described in the previous section. The next step is to read the hierarchy tree and generate Matlab code for matrix manipulations. For symbolic matrix multiplication and inversion, the Symbolic Math Toolbox of Matlab is used. In the results section, the effectiveness of Matlab is discussed, in details. The hierarchy tree is read top-down using the recursive-left edge traversal algorithm. If a node on the tree is a leaf-level node then the expanded circuit functions matrices are written to the Matlab file. If the node is a middle or a top node then the circuit function matrix Hc is generated using the matrices of its child nodes, using Equation 6.5. Once the Hc matrix is obtained, if the node is a middle-level subcircuit, then Hc is transformed to Ha or Hb, based on whether it is child a or childb for the next stage. If more that one new subcircuit generation is required then the Matlab code is a hierarchical code, starting from the lowest level of hierarchy, going to the topmost level.

79 Matlab is then invoked to perform the symbolic matrix manipulations. The output is a text

ﬁle with the Hc of the top-level circuit or a part of it, depending on the desired transfer function. This output, which is a list of symbolic expressions in terms of leaf-level transfer functions, is then processed to convert it to C++ code. This C++ code becomes the top level function, which combines the transfer functions of leaf level circuits (ECDs converted to C++ code), to give the top-level transfer function. The output ﬁles from Matlab are also parsed to obtain the list of leaf-level transfer functions required by the top-level transfer function(s). The list of transfer functions and subcircuits are passed onto a symbolic analyzer. It may not be necessary to generate all or any of the ECDs, if the circuit is partitioned into common-analog modules. Most of the common modules are analyzed completely and stored as a library of pre-compiled ECDs. The top-level compiled C++ functions, along with compiled leaf-level C++ ECDs, form the symbolic performance models (SPMs).

6.3.5 Illustrative Example: Differential Ampliﬁer

W S (Vdd) 3 G D 4 CM_2_P G D (C) (out) 4 3 D2 D1 (in_1) 1 1 G1 D1 3 W (in_2) G2 2 2 DP_N D2 4 G2 S G1 (A) S 5

D (Vb) W G D 5 G ST_N S S (B)

(Gnd)

Figure 6.7: Differential Ampliﬁer and Module Subcircuits

Figure 6.7 shows a differential ampliﬁer and it’s hierarchical partitioning. A module based partitioning approach is used in this case. The differential ampliﬁer is decomposed into three components: differential pair (DP N), current mirror (CM 2 P) and current source (ST N). This example illustrates, how the proposed hierarchical symbolic analysis method is

80 E 1 C 4 A 3 (CM_2_P) (DP_N) D C

2 5 B (ST_N) D A B E

Figure 6.8: Block Diagram of DiffAmp & Hierarchy Tree Traversal applied to a practical circuit, for the generation of transfer functions of the top-level circuit.

Hierarchal Analysis of Differential Ampliﬁer

In this example two levels of transfer function synthesis take place as shown in Figure 6.8. The steps for hierarchically analyzing the circuit are:

1. Sub-circuits A (leaf) and B (leaf) form sub-circuit D

The ﬁrst step in the generation of circuit functions for the differential ampliﬁer is combing two leaf-level sub-circuit A and B. A leaf-level sub-circuit is one whose circuit functions are obtained by direct symbolic analysis rather than circuit function synthesis. The following variables are retained in the generic interconnection template of Figure 6.3 and the rest are removed: T T Child A : ia = [iA iA iA] ; Va = [V A]; Va = [V A] ; Child B: ib = [iB]; Parent D: e 1 2 4 i2 5 e 3 i3 5 c = [ D D D]T c = [ D]T ie2 i1 i2 i4 ; Ve1 V3 A B D D The matrices Ma , Mb , Mc and Pab are obtained directly by retaining only the relevant

variables from Ma, Mb, Mc and Pab. Using the information above all the circuit matrices A B D D D D D D D Ha , Hb , Hc ,Aab, Bab, Cab, Dab, Eab and Fab can be created from equations for Ma, Mb

and Mc, along with equations 6.1 and 6.3, by simply substituting Ma, Mb, Mc and Pab A B D D by Ma , Mb , Mc and Pab. From the information about nodes associated with each variable matrix, the expanded D circuit function matrices can be generated. Using the equation for generating Mc, Mc D D D D D D D can be generated from Aab, Bab, Cab, Dab, Eab and Fab . This Hc after transformation D becomes becomes Ha for the next stage.

2. Sub-circuits D and C (leaf) form top circuit E

81 T Child D : ia = [iD iD]T; ia = [iD]; Va = [V D]T; Child C: ib = [iC] ; Vb = [VC]; Parent e 1 2 i3 4 i2 3 i3 3 i 4 c = [ E E]T c = [ E] E: ie2 i1 i2 ; Ve4 V4 E The output of this stage is Hc which is the desired circuit functions matrix for the differential ampliﬁer. From this circuit functions matrix we can obtain 9 transfer functions.

6.4 Experimental Results

Gain for Design Point # 1 Phase for Design Point # 1 80 0 Gain (db) u_4_1_fZ Phase (deg) u_4_1_fZ Gain (db) u_4_1_Z Phase (deg) u_4_1_Z

60 -20

40 -40

20 -60 Gain (dB) Phase (deg)

0 -80

-20 -100

-40 -120 0.01 1 100 10000 1e+06 1e+08 1e+10 1e+12 1e+14 1e+16 0.01 1 100 10000 1e+06 1e+08 1e+10 1e+12 1e+14 1e+16 Frequency (Hz) Frequency (Hz)

Figure 6.9: Accuracy of the Hierarchical Approach (A) Gain of TF u41(B) Phase of TF u41

Gain for Design Point # 1 Phase for Design Point # 1 140 180 Gain (db) z_4_4_fZ Phase (deg) z_4_4_fZ Gain (db) z_4_4_Z Phase (deg) z_4_4_Z 120 170

100 160

80 150 60 140 40

Gain (dB) 130 20 Phase (deg) 120 0

110 -20

-40 100

-60 90 0.01 1 100 10000 1e+06 1e+08 1e+10 1e+12 1e+14 1e+16 0.01 1 100 10000 1e+06 1e+08 1e+10 1e+12 1e+14 1e+16 Frequency (Hz) Frequency (Hz)

Figure 6.10: Accuracy of the Hierarchical Approach (A) Gain of TF z44(B) Phase of TF z44

In the section we present results and discuss the issues of accuracy, capability and limitations of the proposed hierarchical analysis approach. We also present the results for the analysis of some common (large) electrical networks. Finally, results for large practical analog circuits, with and without parasitics, are presented. The first result presented is for the accuracy of the method when compared to flat symbolic analysis. The accuracy of flat symbolic analysis using

ECDs has already been presented in [71, 92]. In Figure 6.9, the transfer function µ41 of the differential ampliﬁer was generated by both direct (i.e. ﬂat) symbolic analysis and the proposed

82 hierarchical method. When evaluated for a set of transistor sizes, i.e. one design point, both yield exactly the same results, therefore both curves overlap in Figure 6.9 and appear as one.

The same observations can be made from Figure 6.10, for the transfer function z44. There is no loss of accuracy by using our method to synthesize transfer functions. The proposed method is also correct by construction and therefore accurate.

GIT Analysis (m,n vs Matlab Time)

4 10

3 10

2 10

Matlab Time (s) 10

0 10 8 10 6 9 8 7 6 4 5 4 3 2 2 Internal Variables (m) External Variables (n)

Figure 6.11: GIT Analysis Results

It is important to evaluate the efficiency and limitation posed by Matlab, when it is used for symbolic matrix manipulations. The size of the matrices passed onto Matlab, depends on the number of internal and external variables at any stage of analysis. The key factor, is not he number of analysis stages (as will be seen next), but the number of variables at any stage. In Figure 6.11 the GIT is analyzed for the time spent by Matlab when the number of internal and external variables vary. It is observed that limiting factor is the number of internal variables, and therefore the number of interconnections between the two subcircuits being analyzed at any stage. For number of internal variables ≤8 Matlab can generate the results in reasonable time. The Matlab time does not increase significantly with an increase in the number of external variables. Therefore if the number of internal variables is greater than 8, then some of the internal variables can be assumed to external variables for that stage and an extra stage of analysis can be added to the process, without limiting the efficiency. These results show that Matlab can be used efficiently for tightly coupled circuits because, if the limit is reached for internal variables, then they can be assumed to be external variables for that stage, for which

83 the limit in terms of time is high.

RCLadder−600 (Memory vs # of Partitions) 4 10

3 10 Memory (MB) 2 10

1 10 1 2 3 4 6 8 10 12 15 # of Partitions

Figure 6.12: Memory Usage Trend

To examine the memory and time behavior trends of the proposed technique, a RC-ladder circuit with 600 stages (ladder600) has been analyzed hierarchically. The results are presented in Figure 6.12 and 6.13. Here, the x-axis, in both plots, represents the number of equal partitions of ladder600. If the number of partitions is 2, it implies that ladder600 has been partitioned into two ladder300 circuits. Similarly, ﬁfteen ladder40 circuits can be merged to obtain ladder600. Since all partitions are of equal size, the transfer functions, generated or selected from the library, for one partition are valid for all partitions. Therefore the results of subcircuit analysis (by ECD-generation), focusses on the generation of only one ECD - with a fairly accurate assumption that all ECDs of RC ladder circuits have similar memory and time requirements. It can be seen in Figure 6.12 that as the number of partitions increase, memory requirements for the generation of one ECD (i.e., the maximum memory required at any point of time) decreases exponentially. Therefore to decrease memory requirements during subcircuit analysis, it is beneﬁcial to partition the circuit into smaller segments. But as the number of partitions increase, the transfer functions synthesis time and the overall analysis time increase. The results for time requirements, as the number of partitions vary, is presented in Figure 6.13. The plot shows the time to generate one ECD decrease exponentially. At the same time, total time for transfer functions synthesis increases linearly with number of partitions. Other curves represent the split of the total symbolic analysis time into: time for Matlab simulation, and time to generate and

84 RCLadder−600 (Time vs # of Partitions) 70 ECD Gen Total Symbolic 60 Top Level Compile Top Level Gen Matlab 50

Time (s) 30

0 2 4 6 8 10 12 14 16 # of Partitions

Figure 6.13: Time Results compile the top-level transfer function synthesis C++ ﬁle. From these results we can conclude that, as long as the GIT limitations are not reached, the circuit can be partitioned into several small partitions as the total symbolic time increases linearly with number of partitions. This result is very useful and becomes more evident when large analog circuits will be partitioned into several small modules. ECD Statistics Circuit # Nodes Time Memory Depth # Vertices # Edges ladder600 601 17m 3.1G 604 363,610 903,308 ladder700 701 G/F G/F G/F G/F G/F ladder1000 1001 G/F G/F G/F G/F G/F p5 20 2 100 14m 58.6s 3.3GM 108 506,598 1,350,055 p5 20 3 100 G/F G/F G/F G/F G/F p5 20 4 100 G/F G/F G/F G/F G/F Table 6.1: Results of Flat Symbolic Analysis of Large Networks

Our proposed approach was then applied to analysis of large analog networks. Using flat analysis we were able to generate element-coefficient diagrams for up to 630 RC stages. We used both flat and hierarchical approaches for ladder600 network. The hierarchical approach took almost one fourth of the time taken by the flat approach, when ladder600 was

85 Circuit Subciruits Total Time # of TF Maximum Time ladder600 2 ladder300 4m 56.5s 4 2m 26.5 ladder700 2 ladder350 8m 3.9s 4 4m 5.5s ladder1000 2 ladder500 36m 44.6s 4 19m 49.6s p5X20X2 5 ladder20 & 2 IR 6m 45.2s 50 8.3s p5X20X3 5 ladder20 & 3 IR 16m 4.6s 108 8.4s p5X20X4 5 ladder20 & 4 IR 25m 53.2s 188 8.4s Table 6.2: Results of Hierarchical Symbolic Analysis of Large Networks: Part I

ECD Maximum Statistics Circuit Max. Memory ECD Depth # of Vertices # of Edges ladder600 874M 304 91810 226,658 ladder700 1.1G 352 245709 610,417 ladder1000 2.9G 502 501,009 1,246,020 p5X20X2 13M 24 891 1922 p5X20X3 13M 25 3708 7463 p5X20X4 13M 26 4017 8064 Table 6.3: Results of Hierarchical Symbolic Analysis of Large Networks: Part II partitioned into 2-ladder300. The other class of networks which we used for our analysis are the mesh-structured circuits. The circuit p5 20 y implies 5 rows of 20 ladder stages with y interconnections between rows at equal spacing [35]. Tables 6.1, 6.2 and 6.3 present the results for flat and hierarchical analysis on these two classes of circuits. The term G/F implies the failure of the analysis technique to generate. All experiments were run on Sunblade 1000 with two 750 Mz processors, 2GB RAM and 11GB swap space. In Table 6.2 the term TF represents the number of subcircuit transfer functions required to characterize the desired circuit functions of the top level circuit. Maximum time and maximum memory indicate the largest value of time and memory consumed by any one of the transfer functions. ECD maximum statistics represents the largest transfer function(s) of the constituting subcircuits. From the results, we can conclude that our hierarchical approach is capable of handling large and tightly connected circuits and can generate expressions in reasonable time. We have also used our approach to analyze one moderately large and one large analog circuit. R2R is a rail-to-rail operational amplifier, with 24 transistors, which has been broken down into 12 very common analog circuits modules [62]. FDO is a differential amplifier, which

86 X

H C F W K

V A J K VIN_1 J U I VIN_2 VOUT I T

B I L R S G H N Q

D F G E D M P

C E A B

Figure 6.14: (A) Rail to rail operational ampliﬁer (B) Hierarchy

ECD Generation ECD Statistics Circuit Time Memory Depth # Vertices # Edges R2RO 14.7s 21M 18 18,021 107,574 R2RO MODPAR 25.9s 39M 18 36,336 326,403 FDO 3m 36s 210M 27 516,905 3,888,252 FDO MODPAR 7m 5.2s 663M 27 683,839 7,707,532 Table 6.4: Results of Flat Symbolic Analysis of Large Practical Analog Circuits: Part I has been decomposed into 22 common analog modules (Figure 6.15) [97]. In R2R MODPAR the parasitic capacitances of each module is added to the original R2R topology. This does not change the hierarchical description of the circuit but does increase the size by 72 capacitances. FDO MODPAR is similarly obtained by adding 112 module parasitic capacitances to FDO. It is important to note that the emphasis is always to obtain compiled ECDs, as they finally will be used in synthesis of analog circuit, where we try to reduce the synthesis time by using pre- compiled symbolic performance models. The results of flat (direct) symbolic analysis of these analog circuits are presented in Tables 6.4 and 6.5. Tables 6.6 and 6.7 present the results of symbolic analysis based on synthesis of transfer functions. The first observation to make is that that the symbolic matrix calculations in Matlab are extremely efficient. This is obtained by spitting each level of transfer function synthesis into different Matlab files and evaluating all of them in the same session. We observe that in the case of R2R, flat symbolic analysis

87 (Vdd) D D F

L M C

G Vout− J K Vout+ H

N N R I Q

(Vss) O O

Vin+ Vin−

B (Vss) (Vdd)

C D F P U

N O V E S I B

(Vss)

Figure 6.15: Differential Operational Amplifier is faster than the hierarchical method by approximately five times, if the time to generate and compile all the component ECDs in the case of the hierarchical method is taken into account. But, if pre-generated and pre-compiled library-based ECDs of the different modules are used then the times are comparable. In the case of R2R MODPAR the effectiveness of our method becomes more obvious. The compilation time for a flat-ECD is approximately 5 times more than a synthesis based method where library-based ECDs are used. Even, if the ECDs have to be generated and compiled the time in our case is less than by around 10 minutes. When it comes to FDO and FDO MODPAR the advantage which our method posses against a flat ECD based approach is obvious, as in the flat symbolic analysis case the compilation failed (C/F) for both the circuits. Our method posses a significant advantage over other hierarchical methods because of the option to use library-based pre-generated and pre-compiled transfer functions.

88 Lines of ECD Compilation Circuit C++ Code Time R2RO 18,373 7m 23.4s R2RO MODPAR 36,828 46m 9.5s FDO 517,502 C/F FDO MODPAR 684,645 C/F

Table 6.5: Results of Flat Symbolic Analysis of Large Practical Analog Circuits: Part II

Transfer Function Synthesis Time Circuit Matlab Files Matlab Top Level Compilation Total Generation Simulation C++ File of C++ ﬁle Time R2R 1.5s 13.3s 76.2s 8m 50.7s 10m 23.1s R2R MODPAR 1.5s 13.3s 76.2s 8m 50.7s 10m 23.1s FDO 3.9s 18.3s 149s 23m 5s 25m 34s FDO MODPAR 3.9s 18.3s 149s 23m 5s 25m 34s

Table 6.6: Results of Hierarchical Symb. Analysis of Large Practical Analog Circuits: Part I

6.5 Conclusion

The key contributions of this work are: a general interconnection template (GIT) for merging any two subcircuits, a formal technique to synthesize the transfer functions of a GIT, results of the GIT analysis that can be used by everyone, a (library-based) hierarchical symbolic analysis method with GIT analysis as the backbone, an efﬁcient framework for implementation of the proposed method, and ﬁnally the use of the hierarchical method for generating SPMs of large parasitic-inclusive topologies and common analog networks. It is shown in the chapter, that the proposed hierarchical method is very effective in generating transfer functions for parasitic-inclusive topologies, as well as large analog networks. The effectiveness and lim- ECDs of Leaf-Level Subcircuits Circuit # of Generation Compilation ECDs Time Time R2R 106 14m 15.2s 10m 5.8s R2R MODPAR 106 14m 19.2s 10m 27s FDO 166 22m 24.6s 15m 47.9s FDO MODPAR 166 22m 42.8s 16m 10.1s

Table 6.7: Results of Hierarchical Symb. Analysis of Large Practical Analog Circuits: Part II

89 itations of using Matlab for symbolic matrix manipulations has also been demonstrated and discussed in details. Issues related to generation and compilation of top level TF-synthesis functions, based on the number of partitions has also been discussed. The method is very suitable for symbolic performance modeling for use in layout-inclusive analog circuit synthesis and it is the only method which satisﬁes all the criteria for such a use. Future work involves using the SPMs generated by this method in layout-inclusive analog circuit synthesis.

90 Chapter 7

Synthesis using Hierarchical Performance Models

As discussed in Chapter 4, the inclusion of layout in the sizing loop, causes the size of parasitic-inclusive circuits topologies, to explode. Table 4.3 shows that even for moderately large circuits the state-of-art symbolic analysis tools generate such large transfer functions, that it leads to compilation failure. To overcome this problem, the large circuits, are partitioned hierarchically and analyzed symbolically using techniques proposed in the previous chapter. The partitioning can be done based on common-modules for analog circuits or by using a partitioning algorithm. As deﬁned earlier, a module is a single device or group of devices. Some of the common modules is analog design are a differential pair, a current mirror, a current source etc. In this work on hierarchical analysis each module in a circuit is characterized by three entities: a set of nodes, a layout template, a set of all possible intra-module parasitics that can be generated when the module is extracted and ﬁnally a parasitic-inclusive circuit topology. The list of module parasitics are generated by a stand-alone extraction of the module. A thorough examination of the layout-template of the module also yields the same set of parasitics.

7.1 Parasitic-Inclusive Generation: Analysis of the Layout-Template

In order to obtain hierarchical symbolic performance models for layout-inclusive synthesis, the parasitic-inclusive topology, which will be hierarchically and symbolically analyzed, has to be generated. The techniques of analysis-based parasitic inclusion described in Chap-

91 ter 4 are used extensively for obtaining the set of parasitics that possibly be generated in any synthesis iteration. The description of the method for generating the parasitic topology follows.

(Vdd) W S G D CM G W S D (out) 4 3 D2 D1 (in_1) 1 G1 D1 W (in_2) 2 G2 DF D2 G2 S G1 W S

D (Vb) G D G W ST W S S

(Gnd)

Figure 7.1: Differential Pair with Active Current Mirror and Realistic Current Source

1. The ﬁrst step is to select the modules essential for building the circuit. In the circuit shown in Figure 7.1, the three module required are: differential pair (DP), current mirror (CM) and a single transistor (ST). As mentioned previously, each module is characterized by a list of nodes. For example the differential pair has the following input/output nodes:

G1, G2, D1, D2, S, W.

2. The nodes of the selected modules are then assigned actual node names from the circuit schematic. Each DC voltage source in the circuit is shorted and DC current sources are open circuited. Therefore any node connected to a power source is connected to the ground for the purpose of symbolic analysis. The nodes S and W are powered by

a DC voltage source Vdd, but in the circuit schematic (ﬁgure 7.1) they are shown to be

connected to ground directly. Similarly, node G of ST, supposed to connected to Vb is shorted.

In ﬁgure 7.1 the ﬁnal assignment of nodes, for the purposes of symbolic analysis, for

the three modules are thus: DP (G1 = 1, G2 = 2, D1 = 3, D2 = 4, S = 5, W = 0), CM (G = 3, D = 4, S = 0, W = 0) and ST (G = 0, D = 5, S = 0, W = 0)

92 3. The assignment of nodes from the circuit topology to modules, enables the generation of the set of actual possible parasitics. The following two conditions can occur which reduce the set of parasitics: Nodes may be connected to the ground directly and two or more nodes of the module may share a circuit topology node. In the case of the current mirror, nodes S and W share the same topology node i.e. 0, which co-incidentally is the ground node.

Let the original set of parasitics associated with any module X be referred to as CAM X .

After the circuit-node assignment this set of parasitics is reduced and yields the set CRM X .

Set CAM CM is the list of parasitics generated by an extraction of the current mirror module.

CAM CM = {CS W , CD G, CG S, CG W , CD W , CD S, CD GND, CG GND, CS GND, CW GND}

The node GND is eventually replaced by the ground (0) node. After replacing the module nodes by circuit nodes:

CAM CM = {C0 0, C4 3, C3 0, C3 0, C4 0, C4 0, C4 0, C3 0, C0 0, C0 0}

In the set above we see nodes of the form CY Y , which implies that both the nodes of the capacitance are the same and therefore such capacitances can be eliminated. We also observe that some capacitances appear multiple times in the set.Only one copy of these is

retained. Capacitances CX Y and CY X are the same in a physical realization and therefore only one is retained. Applying the aforementioned changes, a reduced set of capacitance is obtained from

CAM X . Let the reduced set be referred to as CRM X . For the current mirror module this set is:

CRM CM = {C4 3, C4 0, C3 0} The same transformations are applied to the original capacitance set of each module and the following reduced set of capacitances are obtained.

CRM DP = {C1 5, C5 3, C2 4, C4 5, C3 0, C4 0, C1 0, C2 0, C5 0, C1 3, C2 5}

CRM ST = {C5 0} The reduced set of module parasitics for the whole circuit is obtained by using the method described in Section 4.2.1: [ [ CRM = CRM CM CRM DP CRM ST

93 = {C4 3, C4 0, C3 0, C1 5, C5 3, C2 4, C4 5, C1 0, C2 0, C5 0, C1 3, C2 5}

For the purpose of parasitic topology generation, each module is examined individually in a sequence. If a parasitic capacitance of a module is already included in a previously examined module then it is set to zero else it is retained. Thus the module topologies are generated for the parasitic inclusive topology from original module topologies by either retaining or eliminating all or some capacitances.

Vdd

Channel 2 W S

D G Channel 1 3 4 5 Vb (out) D1 S D2 G D ST DP W

G1 G2 W Channel 0 (in_1) 1 (in_2) 2 Gnd

Figure 7.2: Circuit Layout Template

4. Once the reduced set of module parasitics for the circuit have been determine, the focus shifts to interconnect parasitics. Figure 7.2 shows the template used for layout generation for the circuit in Figure 7.1. This template is written in the module speciﬁcation language described in Chapter 2. The layout template shows the presence of three channels for interconnects.

First, we consider the case where only parasitic capacitances are extracted. The method described in Section 4.2.1 to obtain the parasitic capacitances of interconnects generates the following sets of parasitics. The set of interconnect parasitics for channels 0, 1 and 2,

after assigning the nodes Vdd, Vb and Gnd to 0, are:

φ CIC0 = {C1 2, C1 0, C2 0}; CIC1 = {C3 4, C3 5, C4 5}; CIC2 =

Therefore the complete set of interconnect parasitics is: [ [ CIC = CIC0 CIC1 CIC2 = {C1 2, C1 0, C2 0, C3 4, C3 5, C4 5}

94 5. Most of the interconnect parasitic capacitances also appear in the set of parasitic capac-

itances for modules (CRM). This implies that when generating the parasitic-inclusive topology, these capacitances can be ignored because they are already present in the mod- iﬁed module-topologies. The interconnect parasitic capacitances that do not appear in the set of module parasitic-capacitances have to be added to the topology being generated as

new modules themselves. The set of such capacitances (CIC Add) can be found thus: \ CIC Add = CIC − (CRM CIC ) = {C1 2}

. Each capacitance in this set becomes a new module in the parasitic-inclusive topology.

(Vdd)

1 G1 (in_1) D1 CM D 4 3 D2 G (out) Cap DP

5 (Vb) S D ST 2 G2 (in_2)

(Gnd)

Figure 7.3: Block Diagram for Parasitic Capacitance-Inclusive Circuit

6. The various parts of the parasitic-inclusive topology have been generated. The individual parts (modiﬁed module-topologies and capacitance modules) are stitched together according to the connection template of the original circuit topology to produce the parasitic inclusive topology. Figure 7.3 presents the topology generated after inclusion of the parasitic capacitances, which will be used for hierarchical symbolic analysis. The capacitance

C1 2 is the only capacitance module (Cap) added to the original circuit topology. The topology of modules, which had been selected based on the original circuit topology, have been modiﬁed to eliminate some capacitances. The capacitances retained for each module

are listed: CM (C4 3, C4 0, C3 0); DP (C1 5, C5 3, C2 4, C4 5, C1 0, C2 0, C5 0, C1 3, C2 5); ST (None).

7. If the parasitic resistances of interconnects are also extracted then the technique to include them in the new topology differs from that described above. For each net in the layout,

95 (Vdd) Net_Vdd

1 Net_1 G1 S W (in_1) D1 4 CM D Net_4 (out) D2 Net_4 G DP

S Net_5 D ST G Net_Vb 2 Net_2 G2 S W (in_2) W (Vb)

Net_Gnd (Gnd)

Figure 7.4: Block Diagram for Parasitic Resistance and Capacitance-Inclusive Circuit a resistance-model (based on the number of terminals in the net) as described in Section 4.2.1, is included in the parasitic-inclusive topology, along with the modiﬁed module- topologies. For the circuit under consideration, the parasitic-inclusive topology is shown in Figure 7.4.

7.2 Hierarchical Symbolic Analysis

The parasitic-inclusive topologies are hierarchically analyzed using techniques described in Chapter 6. Before the analysis the circuits have to partitioned and to that purpose three techniques can be used: Module-based partitioning, the use of a partitioning algorithm or manual partitioning ensuring that the size of the cut-sets do not go beyond a set limit. The aforementioned techniques are described below.

7.2.1 Module-Based Partitioning

In this approach, the parasitic-inclusive topology is partitioned in accordance with the modules used for its generation. Figure 7.5 demonstrates such a partitioning, where the topology has been partitioned into four modules: DP, CM, CS and Cap. The advantage of this approach is that, a library of pre-generated transfer functions, in compiled ECD form, can be used to build up the desired transfer function. However, as the number of partitions is large, Matlab takes large amount of time to generate the desired transfer function in terms of circuit functions of the smaller sub-circuits. Often, for very few levels of hierarchy Matlab generates very huge expressions and takes enormous amount of time to

96 1

C CM 4 3 Cap DP A

5 2 ST D B

C 4 3 A B

5 D 2

E F G

Figure 7.5: Module-based Analysis of Parasitic Capacitance-Inclusive Circuit generate them. The way to circumvent the problem is to generate the expressions in parts by splitting the Matlab code in several smaller pieces of code and linking the generated expression with one another. There is an overhead in terms of lines of C++ code to link all the smaller expressions together. This may result in an increased evaluation time during the performance estimation stage of synthesis.

7.2.2 Partitioning Algorithm Based/ Manual Approach

The alternative to module-based partitioning is a partitioning algorithm or a manual technique. Instead of partitioning the circuit into several small sub-circuits, breaking the circuit into fewer sub-blocks, which are reasonably large, often lessens the complications involved in generating the formula for obtaining the desired transfer function. The Matlab code for matrix operations is smaller and hence takes less time to execute. It generates smaller expressions for combining leaf-level transfer functions to obtain top-circuit transfer functions. This results in reduced evaluation time. The main disadvantage of this technique is that the transfer functions (i.e., the ECD’s) have to be generated for benchmark circuit, and this increases the setup time by a considerable amount. Often, the number of transfer functions required is very large and hence makes this technique undesirable. If the circuit is not very tightly connected then the number of transfer functions needed will be smaller and therefore this technique may be more appropriate.

97 S

CM 4 3 Cap DP

5 2 ST

R 4 3 S

Figure 7.6: Partitioning-based Analysis of Parasitic Capacitance-Inclusive Circuit Figure 7.6 presents an alternative to the module-based partitioning in Figure 7.5. One can observe that, the number of sub-blocks in this case are far fewer than the module-based approach. Even though the sub-blocks are larger than modules, they can easily be symbolically analyzed using the ECD Tool. However, the pre-generated compiled ECDs of the leaf-level sub-circuits cant be used as they could be used in the previous method.

7.3 Symbolic Performance Modeling

The framework for the generation of SPMs was first proposed in [71]. The first step is to generate combinations of nodes that appear in a performance characteristic formula. All the active devices in a circuit are expanded to their small-signal models. The symbolic analysis engine uses the node information to generate the required transfer functions as Element Coefficient Diagrams (ECDs). The symbolic model builder uses the node information to generate the formulae for the desired performance characteristics. The combination of the symbolic formulae and transfer functions are called SPMs.

7.4 Layout-Inclusive Synthesis

The layout-inclusive synthesis approach is exactly the same as once proposed on in Figure 4.1. Layouts are generated by using the Module Speciﬁcation Language(MSL) system, which

98 produces parameterized layouts. Simulated annealing is used as the optimization algorithm and a standard circuit extractor is used to extract the devices and parasitics from the layout. The extracted parasitic values along with the passive component values are passed to the pre- compiled SPMs. The SPMs also take in the small-signal parameter values for all active devices obtained by performing an operating point analysis using SPICE. The performance estimates obtained from SPMs are compared to the speciﬁed constraints. If necessary, the optimization engine proposes a new set of design parameter and this process continues till convergence.

7.5 Experimental Results

(Vdd) D D F

L M C

G Vout− J K Vout+ H

N N R I Q

(Vss) O O

Vin+ Vin−

A Module Partitioning Manual (Part :A) Manual (Part: B) B Manual (Part: C) (Vss)

(Vdd)

C D F P U

N O V E S B I

(Vss)

Figure 7.7: Differential Operational Ampliﬁer

99 ECD Generation ECD Statistics Circuit Time Memory Depth # Vertices # Edges FDO NO-PAR 3m 36s 210M 27 516,905 3,888,252 FDO PAR 7m 5.2s 663M 27 683,839 7,707,532

Table 7.1: Results of Flat Symbolic Analysis of FDO: Part I

Lines of ECD Compilation Circuit C++ Code Time FDO NO-PAR 517,502 C/F FDO PAR 684,645 C/F

Table 7.2: Results of Flat Symbolic Analysis of FDO: Part II The results of flat (direct) symbolic analysis of these analog circuits are presented in Tables 7.1 and 7.2. Tables 7.3 and 7.4 present the results of symbolic analysis based on synthesis of transfer functions. The first observation to make is that that the symbolic matrix calculations in Matlab are extremely efficient. This is obtained by spitting each level of transfer function synthesis into different Matlab files and evaluating all of them in the same session. Matlab can become extremely inefficient if all the symbolic matrix manipulations are specified in just one file. The large analog circuit chosen for our experiments is a fully differential opamp (FDO) shown in Figure 7.7. In the figure we have also shown the module-based partitioning with rectangular boxes with solid lines. We observe in Tables 7.1 and 7.2 that, for FDO NO-PAR (module -based partitioning, no parasitics), flat symbolic analysis can generate the ECD very quickly, but due to the large size of the ECDs the generated C++ code is huge. This leads to compilation failure (C/F). Thus we know that flat symbolic analysis is inadequate for fast performance evaluation in each synthesis iteration. A similar trend is observed for FDO PAR (module-based partitioning, module parasitic capacitances). In Tables 7.3 and 7.4, we observe that for both cases, the hierarchical method can generate and compile the ECD and top level C++ files. In the case of FDO NO- PAR the transfer function generation time is similar in both the flat and hierarchical cases, if Transfer Function Synthesis Time Circuit Matlab Files Matlab Top Level Compilation Total Generation Simulation C++ File of C++ file Time FDO NO-PAR 3.9s 18.3s 149s 23m 5s 25m 34s FDO PAR 3.9s 18.3s 149s 23m 5s 25m 34s

Table 7.3: Results of Hierarchical Symbolic Analysis of FDO: Part I

100 ECDs of Leaf-Level Subcircuits Circuit # of Generation Compilation ECDs Time Time FDO NO-PAR 166 22m 24.6s 15m 47.9s FDO PAR 166 22m 42.8s 16m 10.1s

Table 7.4: Results of Hierarchical Symbolic Analysis of FDO: Part II

Parameter Specs Flow1 Flow2 Verif. %Err gain (dB) ≥ 45 45.2 46.7 46.5 0.4% f−3dB (kHz) ≥ 500 711.8 609.3 615.1 1% ug f (MHz) ≥ 5 12.8 13 13.4 3.1% pm (◦) ≥ 80 86.3 86.3 84.2 2.4% Table 7.5: Layout-Inclusive Synthesis Results: FDO PAR - Run #2 ECD-libraries are used. In smaller circuits the flat approach generates faster than the hierarchical approach. As the size of the size of circuits increase hierarchical analysis becomes faster relative to the flat approach. This is seen in the case of FDO PAR where the time taken by flat symbolic analysis to generate the transfer functions is almost thrice the time for the hierarchical method. If ECDs have to be generated then hierarchical approach an additional setup time. Table 7.5 presents the results for two approaches of circuit synthesis.The first approach (Flow1) uses the MSL environment and NG-Spice for layout-inclusive synthesis. The second approach (Flow2) uses MSL with hierarchical SPMs. The inclusion technique used is layout- template analysis, but only the module parasitic capacitances are included. The layout editor used in both approaches is Magic 7.1 and the numerical simulator is Spice. The obtained performance estimates for Flow2 are verified using NG-Spice. The verification is done not against a complete extracted netlist for the final design point, but with a extracted netlist with only the module capacitances. The small error can be attributed in part to the bisection method of solving for roots of the transfer function, to obtain the values of unity gain and -3dB frequencies. Table 7.6 presents the time results for both methodologies. The performance convergence in both cases is fast due to the use of a language-based layout generator. The speedup depends on the number of ac analysis points used in numerical simulation with Spice. Run1 uses 10 points/decade and Run2 uses 25points/decade. Flow2 is 1.3x & 1.9x faster than Flow1, per iteration for Run1 and Run2 respectively. The numeric analysis time of Flow2 (for operating

101 Synthesis Time per Iteration Run Approach Layout Performance Estimation Total & Gen. Numer. Model Total Iter. Speedup & Ext. Analysis Eval. Time Flow1 1.491s 0.512s 0.372s 0.885s 2.379s # 1 Flow2 1.491s 0.277s 0.011s 0.29s 1.797s Speedup - 1.85x 33.8x 3.05x 1.32x Flow1 1.491s 0.895s 1.002s 1.9s 3.395s # 2 Flow2 1.491s 0.277s 0.011s 0.29s 1.797s Speedup - 3.23x 91.1x 6.55x 1.89x

Table 7.6: Time Results of Layout-Inclusive Synthesis for FDO PAR point analysis) is 1.9x & 3.2x faster than Flow1. Model evaluation time of Flow2 (SPM evaluation time) is 33x & 91x faster than model evaluation (the process of obtaining desired performance attributes from the analysis results) time for Flow1. Overall, SPM-based performance estimation time is 3x & 6.6x faster than NG-Spice-based method. All experiments have been conducted on SunBlade 1000 with Solaris(SunOS), 2048MB RAM and 2-750MHz Processors.

7.6 Conclusions

In this chapter we have presented a method for parasitic-aware hierarchical symbolic performance modeling. The underlying technique is the transfer-function based hierarchical symbolic analysis technique. The efﬁciency of the hierarchical symbolic analysis has been demonstrated. We have also developed techniques to generate the parasitic-inclusive topology directly from the layout template. A layout sampling technique can also be used for generation of the topology. The transfer-function synthesis based hierarchical symbolic analysis paves the way for library-based symbolic analysis techniques, where pre-generated ECDs of common analog modules (like current mirrors, differential pairs etc.) are used to obtain the circuit function of large analog circuits.

102 Chapter 8

Solution for the DC Operating Point

The estimation of any performance metric involves a two-stage analysis. The ﬁrst stage is the operating point analysis and the second is either AC, transient or some other analysis. The process is shown in Figure 8.1. In the numerical simulator based approach we have SPICE for all kind of analysis including the DC operating point (OP) and AC analysis for estimating performances like DC gain, UGF, phase margin etc. A breakdown of the analysis time shows thats OP analysis takes up 40-70% of the total analysis time and AC analysis about 30-60%.

Circuit Topology

Operating Point Analysis

Biased Circuit

AC/ Transient/ Other Analysis

Simulation Results

Figure 8.1: Stages of Circuit Analysis

In Chapter 4 the second stage analysis time has been reduced signiﬁcantly by use of symbolic analysis. A breakdown of analysis time reveals that the OP analysis time takes up 90-95% time and the remaining 5-10% of the time is taken up by the AC analysis. Thus it becomes imperative to replace the numerical DC operating point analysis of SPICE by a faster

103 technique.

8.1 Related Work

In this section we ﬁrst discuss the numerical DC operating point analysis technique used in SPICE and it’s variants like Hspice, Spectre etc. Then others technique like OP-driven analysis, relaxed DC formulation, gm/ID method etc. are discussed.

8.1.1 DC Operating Point Analysis in SPICE

In a numerical simulator like SPICE [58] and it’s variants, every analysis starts with a DC operating point analysis. The DC bias is determined using this analysis, where DC voltages and currents are calculated. The process as described in [58]:

1. The analysis starts off with replacing the capacitors with open circuits, and each inductors with a short circuit.

2. The system matrix (A.X = B) is then formulated using a combination of predeﬁned element templates and nodal analysis. The three components of the system matrix are the conductance matrix (A), voltage array (X) and the current array (B).

3. Then for every node in the circuit, an initial voltage is guessed. If the node is connected to a voltage source the DC voltage is set to the speciﬁed in the input ﬁles. The remaining nodes are set to zero value.

4. Once the voltage array is know, equivalent currents and conductances calculated for linearized circuit models of each non-linear element (like diode, transistors etc.). The currents are put in the current array and the conductances in the conductance array.

5. The arrays are then passed onto the Newton-Raphson solver. The solver calculates a new set of voltages.

6. If all the node voltages and currents match the previous iterative values, or if the iteration limit is reached, then the results the process proceeds to step 7 or else jumps backs to step 4.

7. The results of the operating point analysis are stored in a ﬁle. If a solution was not found then a non-convergence error message is printed.

104 From a description of the methodology it is evident that DC operating point analysis is computationally expensive because of the iterative Newton-Raphson solver. Till this point we have used this solution for the DC operating point, which has taken up a huge chunk of the performance estimation time.

8.1.2 Operating Point Driven Method

The operating point driven DC root solving method was proposed by Leyn et al. in [64]. In this approach the operating point is speciﬁed at the start. The operating point implies the independent variables: node voltages (Vn), chord Currents (Ic) and transistor lengths (L). The device dimensions are determined from the given operating point. The essence of this technique is that a circuit level problem is transformed to a transistor level problem. A detailed description of the method follows:

1. The ﬁrst step is to generate the incidence matrix (A) and the basic loopset matrix (B) of the given circuit topology.

2. Using minmax optimization the valid set of node voltages Vn and cord currents Ic are determined. The condition to be satisﬁed is that all transistors must be on. The setup

inequality functions for each transistor are shown: −hi = VDSi & gi = −(VGSi − VT ); where i = 0, 1, ....m; m = # of transistors. This set of inequalities is solved using minmax optimization or randomly generate values till all inequalities are satisﬁed.

T T 3. The branch voltages (Vb) and currents (Ib) are determined: Vb = A Vn, Ib = B Ic. This

generates values of all VGSi , VDSi , VBSi & IDSi for all transistors in the circuit.

4. For each transistor i ( i = 0, 1, .... m) the MOS characteristic equation is:

IDSi = f (VGSi , VDSi , VBSi , Wi, Li). The values of VGSi , VDSi , VBSi &IDSi obtained in the pre-

vious step and the already known value of Li are substituted in the characteristic equation.

The characteristic equation is transformed to: f (Wi) − IDSi = 0.

5. The transformed MOS characteristic equation is then solved to obtain the value of Wi.

The root solving always converges because the equation f (Wi) − IDSi is monotonic and therefore the bisection method can be used for solving it. This method yields a guaranteed solution even if maybe infeasible.

6. It is very likely that Wi obtained by root solving in Step 5 is off the grid. To snap the solution onto the grid a DC simulation strategy is used where a quick numerical simulation

105 is done for solutions in the neighborhood of all Wi’s. Approximate Hermite interpolation technique is used to obtain the on-grid solutions in the neighborhood.

Since the values if all the transistor voltages, currents, width and length is known, all the small signal parameters can be easily obtained from the model equations. The small signal parameters can then be used to evaluate the performance characteristics of the circuit. The method claims guaranteed convergence, as it starts with a feasible operating point.

Even though concepts of parallel computing can be applied in this method to obtain Wi’s for different transistors simultaneously, the fact that DC simulations have to be used to obtain on- grid solutions, slows down the process considerably. It is not clear how much time is spend on obtaining on-grid solutions and the following DC simulation. Intuitively though we can say that since the on-grid sizes are in the vicinity of the off-grid solution, the operating point analysis based on DC simulation will take less time that a full blown DC OP analysis as in the case of SPICE.

8.1.3 Relaxed DC Formulation Approach

Ochotta et al. proposed the relaxed DC formulation approach in [74]. During circuit synthesis this method avoids a computationally expensive DC Operating Point Analysis after each perturbation to design variables. Instead it treats it as an optimization problem and solves it simultaneously with performance optimization. The node voltages are selected as independent design variables subject to some constraints. KCL equations are formulated for each node. For example, KCL at node x : Iout1 + Iout2 − Iin1 = 0. Similar formulation is done for every node in the circuit. To ensure that each KCL equation is satisﬁed when optimization ﬁnishes, these equations are added to cost function as constraint functions. For example, the constraint ε function for the KCL equation above is: g(x) = max ( 0, |Iout1 + Iout2 − Iin1 | − ). Similar constraint functions for every node added to cost function. These additions to cost function contribute penalties to it whenever KCL error occurs at any node. Even though this method avoids computationally expensive numerical OP simulations in every iteration, the gain is negated by it’s effect on the synthesis process itself. Since the root-solving problem has been reformulated as optimization problem, it introduces several local minima [64]. Thus the use of a global optimizer becomes a necessity. A DC inaccurate solution can also misguide the search, thus prolonging the optimization times.

106 8.1.4 The gm/ID Method and Inversion Coefﬁcient Approach

The gm/ID method for design of micropower CMOS analog circuits was proposed by Silveira et.al. in [85] and [38]. Traditional analog design approaches assume that the transistors are in strong inversion, whereas this method used the moderate inversion region to obtain good speed-power tradeoffs. The method is valid for all regions of operation and uses the gm/ID ratio versus the normalized current plot for biasing the circuit and obtaining transistor sizes. Here gm stand for transconductance of a transistor and ID the drain current. The normalized current IN is deﬁned as the ratio of the drain current and the aspect ratio of the transistor. Therefore, the normalized current is given by: IN = ID/(W/L).

Since, both gm/ID and IN are independent of the transistor sizes, therefore the relation between the two is unique for all transistors of the same type in a given fabrication batch. This relationship can be obtained either by using transistor model equations or by experimentation. This method can be used for synthesis of analog circuits by assuming that the total supply current is known prior to synthesis. From the gm/ID vs. IN characteristic, given the value for any two of gm/ID, gm, ID; W/L is determined unambiguously. Therefore, from the total supply the current, the drain of each transistor is found out. Using this ID and a good value of gm/ID (based on which region of operation the transistor should be), the W/L ratio can be determined. Therefore the primary variables in the synthesis process are the drain currents of each transistor and their gm/ID ratio. A similar method, called the inversion coefficient approach, was proposed by Binkley et al. in [11]. This method operates on three degrees of design freedom: drain current (ID); transistor length (L); and inversion coefficient (IC). The inversion coefficient is similar to the normalized current IN in the previous method. Instead of choosing a suitable gm/ID ratio, the inversion coefficient is chosen as the design variable, along with the drain current. The EKV MOS model, which is continuous and valid in all regions of MOS operation, is used for correlating the three degrees of freedom.

8.1.5 Discussion

The operating point driven approach was developed to give the designer the freedom to operate with voltages and currents, and for guaranteed convergence, in order to eliminate the non-convergence issues with SPICE. Even though the method claims to be computationally ef- ﬁcient, it still relies on a bunch of DC simulations involving on-grid points, in the neighborhood

107 of the original solution. An approach to overcome this shortcoming would be, to use the off- grid solutions for AC performance estimation, and use just one set of DC simulations at the end, for snapping the off-grid solutions to on grid. Moreover, the starting point is in the original approach is generated by using a minmax formulation. A better starting point can be obtained by using the set of sizing rules, for electrical transistor quantities, described in [44]. Not only does it guarantee a good starting point, but also ensures that the synthesized design is robust and not very sensitive to process variations. The gm/ID method also can be adopted to replace the current SPICe based method. Regression techniques can be used to capture the relationship between the normalized current (inversion coefﬁcient) and the transconductance-drain current ratio.

In this work we adapt the original gm/ID method, to produce on-grid device dimensions. The methodology accounts for all small-signal parameters, guaranteeing greater accuracy than the traditional gm/ID method.

8.2 The State of MOSFET Modeling for Analog CAD

Traditional MOSFET modeling has been driven by the demands of digital circuits, and therefore when used in the analog domain, often fall woefully short of the expected accuracy levels. Tsividis and Suyama have shown in [91] that these inadequacies become more pronounced when the design objective or constraint is either low power, or low voltage, or high speed, or any combination of the three. The commonly used mean-square error criteria for the drain current in digital applications, is not sufficient to guarantee accurate analog parameters. Some further discussion on the popular MOS modeling methods is needed to highlight the need for dedicated analog MOSFET models. A common criteria to judge the accuracy of a model is to accurately match the drain-current predictions to the actual measurements. Now, this maybe sufficient in digital applications but, analog use also requires accurate results for small-signal parameters like, transconductances, intrinsic-capacitances etc. So, a model which predicts the true IDS-VGS characteristic, should also give correct values of gm. Often, the ”digital” MOSFET models give inaccurate values for ”analog” parameters, under conditions or regions of operation which are important in analog design. For example, the popular industry-standard model BSIM3v3, predicts significantly (almost 40%) erroneous results for transconductance efficiency

(gm/ID) and early voltage (Va) parameters, in the moderate inversion region [90]. Tsividis and Suyama [91] have also compiled a set of twelve characteristics of analog

108 MOSFET models. A synopsis of these requirements is presented here. Any MOSFET model must be accurate enough to for application in the digital domain, i.e., it should predict, with good accuracy, the current-voltage relationships, the shift register speed, the charge conservation, etc. In addition, as mentioned above, it should give true values for the small-signal parameters, and the parameters should be continuous in all regions of operation. The results should be accurate for nonquasi-static operation, as well noise parameters. The model should satisfy the aforementioned requirements for all bias conditions and over the given temperature range. All the conditions mentioned above, should hold for all valid width and lengths. Moreover, the model should have as few model parameters as possible, enough to meet all the requirements mentioned. Also, the parameters must have a strong physical basis, and empirical parameters without a physical link should be discouraged. The model should also account for several phenomena like channel length modulation, drain-induced barrier lowering, etc. The model should also be linked to an efﬁcient parameter-extraction methodology. The paper also proposes a set of test which the models must pass, before they can be classiﬁed as good models. This discussion sets the platform for discussion some recently proposed compact models, suitable for analog design.

8.3 The Enz-Krummenacher-Vittoz (EKV) MOSFET Model [27, 13]

In recent years, there has been a push towards the development of compact MOSFET models geared towards application in analog design, and the EKV MOSFET developed at EFPL, Switzerland, is one of them.

8.3.1 Salient Features

Some of the important features of the EKV MOSFET model, which make it desirable and suited for application in analog circuit synthesis are listed here:

• The model is dedicated to the design of low voltage, low current analog circuits and has been developed by experts in analog design.

• It is a fully analytical model, with simple expression for transconductance generation

efﬁciency gm/ID in terms of the inversion coefﬁcient (IC)

• The model has a string physics base, which implies that it has very few empirical parameters. This make the parameter extraction a much simpler job. Only 18 intrinsic DC

109 parameters are required.

• It is valid from weak to strong inversion region. All large and small-signal parameters are continuous in all regions of operation including, weak, moderate, strong inversion, along with conduction and saturation modes. The model is derived by ﬁrst analyzing the weak and strong inversion asymptotes. The an appropriate interpolation function is used to accurately model the various parameters in the moderate inversion region.

• Exploits inherent symmetry of MOSFETs. All voltages are referred to the local substrate.

8.3.2 Drain Current and MOS Inversion Coefﬁcient

In the EKV MOSFET Model the drain current can be decomposed into a forward current

IF and a reverse current IR as shown below:

ID = IF − IR (8.1)

The drain current is normalized to yield the inversion coefficient, which is a measure of the channel inversion. Inversion coefficient is defined as:

ID IC = W (8.2) IT · ( L )

Here, W is the effective channel width of the transistor, L the effective channel length, and IT is the technology current and is given by:

2 0 IT = 2 · n · µ ·COX ·UT = n · IT (8.3) where n is the slope factor, µ is the surface mobility, COX is the gate oxide capacitance per unit 0 area, UT = kT/q is the thermal (thermodynamic) voltage. The value of IT is a constant for a 0 given technology and temperature. The value of IT for a 0.5µ technology used in this work is 197.89nA for nMOS and 46.18nA for pMOS.

W The quantity IT · ( L ) is also known as the speciﬁc current or the normalization current, W and can be represented by IS. The quantity ID/( L ) is also know as the normalized current and can be represented by IN. Therefore, Equation 8.2 can be also written as:

ID IN IN IC = = = 0 (8.4) IS IT n · IT When the Equation 8.1 is plugged into Equation 8.4, we obtain

IF − IR ⇒ IC = = i f − ir (8.5) IS

110 where i f ≡ IF /IS is the forward normalization current and ir ≡ IR/IS is the reverse normalization current. In forward saturation conditions, ir ≈ 0, and therefore from Equation 8.5.

i f = IC (8.6)

8.3.3 Large-Signal Interpolation Function and Intrinsic Voltages

The VS & VD are the drain and source voltages referred to the local substrate, to exploit the inherent symmetry of MOSFETs. Similarly, VG is the gate voltage referred to the substrate.

The pinch off voltage VP is deﬁned as follows: V − V V − V V =∼ G T0 = GB T0 (8.7) p n n The forward and the reverse normalization currents are functions of the terminal and the pinch off voltages. VP −VS VP −VD i f = F( ) & ir = F( ) (8.8) UT UT The function, F(v), relates normalized currents to normalized voltages. Using, a simple, yet accurate, expression for the transconductance interpolation function, G(IC), the large-signal interpolation, given below, is found.

VP − Vy p p = 2 · 0.25 + ix − 1 + ln( 0.25 + ix − 0.5) = f (ix) (8.9) UT where x = f , y = S or x = r, y = D.

The expressions of voltages VS and VD are derived from Equation 8.9

VS = VSB = VP − UT · f (i f ) p p = VP − UT ·{2 · 0.25 + i f − 1 + ln( 0.25 + i f − 0.5)} (8.10)

VD = VDB = VP − UT · f (ir) p p = VP − UT ·{2 · 0.25 + ir − 1 + ln( 0.25 + ir − 0.5)} (8.11)

∴ VDS = VD − VS = UT ·{ f (i f ) − f (ir)} p p p 0.25 + i f − 0.5 = UT ·{ 2 · ( 0.25 + i f − 0.25 + ir) + ln( √ ) } (8.12) 0.25 + ir − 0.5

111 8.3.4 Small-Signal Parameters

Transconductances

The following set of equations can are obtained from [12]. Transconductances are normalized with resect to the drain current as shown below:

gmx ·UT Gx = where : x = g, d, s, b (8.13) ID The ideal relation between the normalized transconductance and the inversion coefﬁcient, for a transistor in saturation is given by: 1 G(IC) = √ (8.14) 0.5 + 0.25 + IC From Equation 8.14, the ideal expressions for transconductances can be easily obtained as shown below. The assumption is that the transistor is in saturation and the second order effects have not been taken into account.

Gs = G(IC) (8.15) ∼ gmg ·UT G(IC) Gg = = (8.16) ID n

By plugging Equation 8.14 in Equation 8.16, and solving for gmg, we obtain the following:

ID ⇒ gm = gmg = √ (8.17) n · UT · (0.5 + 0.25 + IC) Similarly, the ideal expression for bulk-transconductance is deﬁned as:

∼ gmb ·UT (n − 1) · G(IC) Gb = = (8.18) ID n

(n − 1) · ID ⇒ gmb = √ (8.19) n · UT · (0.5 + 0.25 + IC)

It is difﬁcult to obtain the normalized drain-transconductance, Gd, and in [12] an approximate expression for weak inversion is presented. A better way to obtain the normalized drain- transconductance is to relate it to the early voltage VA.

∼ gmd ·UT UT Gd = = (8.20) ID VA

The early voltage, VA, is plotted against the inversion coefﬁcient in [11]. It is shown that VA is a function of channel length L. For inversion coefﬁcients between 0.001 to 100, VA increases at

112 nearly a linear rate with the channel length. The rate of increase (VAL) is around 10-15V/µm. Therefore, the early voltage can be deﬁned as thus:

VA ≈ VAL · L ≈ 10 (Volts/µm) · L (µm) = 10 · L (Volts) (8.21)

This leads to the derivation of a simpliﬁed expression for the drain-transconductance, by inserting Equation 8.21 into Equation 8.20:

Gd · ID ID ID ⇒ gds = gmd = = = (8.22) UT VA 10 · L

It is important to note that the derivation of gm, gmb and gds presented above excludes the velocity saturation effects at high inversion and short channel lengths. In the case of gds the effects due to drain barrier induced lowering (DIBL) at low inversion and short channel length are also ignores, along with the inﬂuence of impact ionization at high inversion and short channel length [11, 12]. Therefore, we apply the results obtained above for long channel lengths and inversion coefﬁcients ranging from 0.01 to 100.

Intrinsic Capacitances

The intrinsic capacitances are obtained in two steps. First, the normalized intrinsic capacitances are derived, and then are multiplied by a factor dependent on the device dimensions, to obtain the total intrinsic capacitances. The equations follow: √ x f = 0.25 + IC (8.23) p xr = 0.25 + ir = 0.5 ∵ ir = 0 f or f orwardsaturation (8.24)

Cox = COX ·We f f · Le f f = COX ·W · L (8.25)

COX is the gate oxide capacitance per unit area. We f f = W − DW = W, as we assume that the channel width correction (DW) is zero. Similarly, Le f f = L − DL = L, based on the assumption that the channel length correction(LW) is zero. Normalized Intrinsic Capacitances

2 1 2 xr + xr + 2 · x f cgs = · [1 − 2 ] (8.26) 3 (x f + xr)

2 1 2 x f + x f + 2 · xr cgd = · [1 − 2 ] (8.27) 3 (x f + xr)

113 (n − 1) c = · [1 − c − c ] (8.28) gb n gs gd

csb = (n − 1) · cgs (8.29)

cdb = (n − 1) · cgd (8.30)

Total Intrinsic Capacitances

C(gs, gd, gb, sb, db) = Cox · c(gs, gd, gb, sb, db) (8.31)

8.4 The Universal gm/ID vs IN Curve

It is imperative to discuss the universality of the gm/ID curve as it offers a fundamental analog design method, on which our synthesis methodology is based. Silveira et. al. proposed in [38], a new design method based on the relationship between the transconductance generation efﬁciency and the normalized drain current. In the paper, it is quoted that: ”the relationship between gm/ID and the normalized current is a unique characteristic for all transistors of the same type (nMOS or pMOS) in a given batch.”. To examine the statement closely we plotted gm/ID vs. the normalized current IN. The results are shown in Figure 8.2 for nMOS and Figure 8.3 for pMOS.

gm/ID vs. IN (0.5−um nmos) 30 W = 4u W = 40u 25 W = 400u

Transconductance Efficiency: gm/ID 5

0 −9 −8 −7 −6 −5 10 10 10 10 10 Normalized Current: IN = ID/(W/L)

Figure 8.2: Transconductance Efﬁciency vs Normalized Current (NMOS)

114 gm/ID vs. IN (0.5u−PMOS) 30 W = 4u W = 40u 25 W = 400u

Transconductance Efficiency: gm/ID 5

0 −9 −8 −7 −6 −5 10 10 10 10 10 Normalized Current: IN = ID/(W/L)

Figure 8.3: Transconductance Efﬁciency vs Normalized Current (PMOS)

The ﬁgures show that for three different widths (4µ, 40µ and 400µ) the gm/ID vs IN plots exactly overlap each other. However, this plot is valid only for long-channels (L=4µ) and does- not take into account velocity saturation at high inversion. These plots are only valid for forward saturation, which is the region of our interest. The transistors were kept in saturation by connecting the gate and drain nodes of the transistor. The plots were obtained by simulations using the EKV2.6 MOSFET Model parameters for 0.5uµ [13, 2] technology. The simulations were carried out using the WinSpice simulator [3]. WinSpice was chosen over HSpice because of it’s operating point output format, which enables the user to examine important EKV MOSFET model parameters like i f , ir, n, VP etc.

We examined the dependence of the gm/ID vs IN curve for two reasons. The ﬁrst was to demonstrate it universality for transistors of a given technology. A detailed study of the dependence of this curve on the device bias, sizes and temperature can be found in [4]. The second reason for studying these plots was to obtain an explicit expression between gm/ID and

IN. Matlab’s polynomial regression package, was used to obtain the equations.

8.5 Conditions for Forward Saturation

When a MOS transistor is in forward saturation, the following conditions are true:

1. i f = IC & ir ≈ 0

115 √ 0.25 + i − 0.5 2. √ f ≥ ε where ε = e4 0.25 + ir − 0.5

The second condition has been used previously for the ACM model in [19] to derive the saturation condition. In this work the condition mentioned above has been applied to the

EKV MOSFET model. To obtain the expression for VDSsat the conditions mentioned above are inserted into Equation 8.12. √ √ √ VDSsat = UT ·{ 2 · ( 0.25 + IC − 0.25) + ln(ε) } = UT ·{ 2 · ( 0.25 + IC) − 1 + 4 } √ ∴ VDSsat = 2 ·UT · ( 0.25 + IC + 1.5) = fDSsat(IC) (8.32)

Santos and Cunha [80] have proposed that the saturation of a transistor can be veriﬁed by comparison to drain-to-bulk voltage, in place of drain-to source voltage. A very straightforward way of veriﬁcation is proposed for the ACM model has been presented in the aforementioned work. In this work the technique has been extended to the EKV MOSFET model. By manipu- lating the Equation 8.11, the expression for VDB can be rewritten as follows: p p 0.25 + i f − 0.5 p VDB = VP + UT ·{1 − 2· 0.25 + ir + ln ( √ ) − ln( 0.25 + i f − 0.5)} 0.25 + ir − 0.5 (8.33) Therefore for forward saturation Equation 8.33 is transformed to the following by plugging in the saturation conditions mentioned above: √ VDBsat = VP + UT ·{ 4 − ln( 0.25 + IC − 0.5)} = VP + UT · fDBsat(IC) (8.34)

In forward saturation, the equation for VSB given by Equation 8.10 is transformed to:

VS = VSB = VP − UT · f (IC) (8.35)

Equations 8.32, 8.34 and 8.35 are used in this work to ensure that all transistors are biased in forward saturation.

8.6 Synthesis Approach based on Modiﬁed gm/ID Method

The proposed synthesis methodology is shown in Figure 8.4. This method is a slightly modiﬁed version of the original gm/ID design method. The original gm/ID design method uses the quantity gm/ID of each transistor as the primary design variable. From the gm/ID vs IN curve the value of IN is found. Now since IN = ID/(W/L), if the drain current is known the

116 START

Simulated Annealing

Saturation All Yes No Conditions Specifications STOP Satisfied? Met?

Yes

Generate Evaluate Symbolic Small−Signal Parameters Values Performance Models

Figure 8.4: Synthesis Methodology device dimensions can be found. The drain current is generally pre-decided, to ensure correct bias conditions, and also because it traditionally used by designer to bias unsized topologies. Though this method gives the designer a simple yet powerful way handling analog design, it often yields device dimension which are off the grid. For example if the obtained value of W/L is 100.34 and the transistor length is ﬁxed at 4µ then the obtained value of width 25.085µ which is off the grid for a 0.5µ technology. Such a device dimension cannot be used for layouts and therefore would require readjusting of device dimensions, or drain current, which in turn would change the small-signal parameters. Another method which uses the inversion coefﬁcient at the primary design variable, also produces device sizes which are off the grid. To ensure that the

ﬁnal transistor sizes are suitable for layout, a modiﬁed gm/ID method is proposed in this work.

In our method, Instead of choosing gm/ID and the current as primary design variables, the drain current ID and the width of transistors are used as the primary variables. The proposed methodology is shown in Figure 8.4. The various stages of the synthesis process are explained below:

• Simulated Annealing based Optimization Engine :

The optimizer has been described in details in Section 2.4. The input to the sizer is a set of performance speciﬁcations, and he search range for each primary design variable. In this work, the primary variables are the bias currents and the widths of each transistor. The length of the devices are ﬁxed at 4µ.

• Saturation Condition Check :

117 It is imperative to check if the saturation conditions has have been satisfied before pro- ceeding onto the next stage. The saturation conditions for each circuit are calculated by hand and provided to this stage in the synthesis. An example of how to derive the saturation conditions will be presented in the setup section of the two-stage opamp. The first step is to calculate the slope-factor n, for each transistor, which can be obtained in two ways. The first way is to assume a constant slope-factor, which is a fairly valid assumption [94]. To obtain a more accurate value of slope factor, an explicit expression is

generated for the slope factor n in terms of IN, by using Matlab’s polynomial regression package. The second step is to determine the inversion coefﬁcient IC for each transistor.

The variables ID, W, L and n are plugged into the Equation 8.2, which yields ICm, where

m = 1,2,....,n. These ICx are then used to verify the saturation conditions.

• Calculation of Small-Signal Parameters Values :

In order to calculate the values of the small-signal parameters the following must be known: inversion-coefﬁcient IC; and the slope-factor n. The values of transconductances

gm, gmb and gdscan be found by using equations 8.17, 8.19 and 8.22 respectively. The

value of gm can also be found out by using the expressions, relating the transconductance

generation efﬁciency gm/ID and the normalized current IN. The expression is derived from Matlab using the polynomial regression package, where the input is simulation data

obtained by HSpice or WinSpice. If the later method is used for obtaining gm, then the

input will include ID, W and L for every transistor. The capacitances are found using the equations for normalized intrinsic capacitances (Equations 8.26- 8.30). The normalized capacitances are then multiplied by the quantity

Cox, to obtain the total intrinsic capacitances Cgs, Cgd, Cgb, Csb, and Cdb. Thus, all the small signal parameters are accounted for. This is one of the signiﬁcant contributions

of this work, as no previous gm/ID or similar technique accounts for all the small signal parameters.

• Evaluation of Symbolic Performance Models

The symbolic performance models are generated using ECD-based symbolic analysis. At this stage of the proposed methodology, the compiled symbolic performances, which have been pre-generated before the start of synthesis, are evaluated by substituting the real numerical values of the small signal parameters. The output of this stage is the set of numerical values of the performance parameters like DC gain, CMRR, phasemargin etc.

118 8.7 Experimental Setup and Results

8.7.1 Twostage Operational Ampliﬁer

The first benchmark is a twostage operational amplifier (TSO) [97] and is shown in the figure 8.5. Synthesis setup and derivation of saturation for TSO are described next.

Synthesis Setup

Minimum Maximum Scaling Parameter Value Value Factor

WM1 = WM2 100 200 1e-6

WM3 = WM4 4 40 1e-6

WM5 50 200 1e-6

WM6 50 200 1e-6

WM7 500 700 1e-6

WM8 300 500 1e-6 Cc 10 50 1e-13 Ibias 10 100 1e-12 Table 8.1: Search Ranges for Primary Design Variables of TSO

The ﬁrst step is to identify all the primary design variables in the circuit. The primary variables are the circuit parameters, values of which are explored by the optimization engine. Once the primary variables have been determined, the secondary variables are recognized and relationships linking them to the primary variables are obtained. The search range, i.e., the range of values which the parameters lied within, is then determined. A scaling factor is also decided for each primary variable. The scaling factor is the number which determines the actual search range and the step size to be used for a particular variable. Table 8.1 shows the search- range for all the primary variables of the twostage opamp. Let us take a look at one primary variable WM1 to understand better, the importance of scaling factor. The search range is from 100 to 200, and the scaling factor is 10−6. The upper and lower limit of are multiplied by the scaling factor to yield the actual search range of 0.00001 - 0.00002, with a step size same as the scaling factor. The secondary variables, are circuit parameters whose values are not directly changed by the optimizer. They are related to the primary variables by equations. The secondary variables are the equations relating them to the primary variables, are shown in table 8.2.

119 Vdd

M5 M6 M7 a

b Vout Vin− Vin+ M2 M1 Cc Ibias CL

d M8 c

M3 M4

Vss

Figure 8.5: Twostage Op Amp

Secondary Variables Equations

Ibias·WM5 IDM1 = IDM2 = IDM3 = IDM4 2·WM6 Ibias·WM5 IDM5 WM6

IDM6 Ibias

Ibias·WM7 IDM7 = IDM8 WM6 Table 8.2: Secondary Variables in Terms of the Primary Design Variables for TSO Derivation of the Conditions for Saturation

To obtain the saturation conditions the Equations 8.34 and 8.35 are used extensively. We show how to derive the saturation conditions for M4 and provide the results for all transistors in

Table 8.3. For transistor M4 to be in saturation the following condition should be true:

VDB4 = VD4 − VB4 > VDBsat4

Replacing the terms in equation above by node voltages and Equation 8.34 we get:

V(d) − Vss > VP4 + UT · fDBsat(IC4) (8.36)

In order to obtain an equation for VP4 , we take a look at the equation for VSB4 .

VSB4 = 0 = VP4 − UT · f (IC4) ⇒ VP4 = UT · f (IC4) (8.37)

120 Device Saturation Conditions

V − V − V − V M , M f (IC ) + n · f (IC ) < in− ss T0P T0N 1 2 DBsat 2 3 3 UT V M f (IC ) + f (IC ) + n · f (IC ) < T0N 4 4 DBsat 4 8 8 UT V − V − V M f (IC ) + f (IC ) + f (IC ) < dd in+ T0P 5 1 5 DBsat 5 n1·UT M f (IC ) + f (IC ) < Vdd − Voutmax 7 7 DBsat 7 UT V − V M f (IC ) + f (IC ) < outmin ss 8 8 DBsat 8 UT Table 8.3: Saturation conditions for the Transistors of TSO

Now, in order to ﬁnd the equation for node voltage V(d), the equation for transistor M8 are analyzed. By substituting VSB8 = 0 and by using Equation 8.7 for the pinch-off voltage, we get the following equation:

V(d) − Vss − VT0N VP8 = UT · f (IC8) ⇒ = UT · f (IC8) n8

⇒ V(d) = UT · n8 · f (IC8) + Vss + VT0N (8.38) By inserting Equations 8.37 and 8.38 in Equation 8.36, the following condition for saturation of M4 is obtained in terms of the inversion coefﬁcients of M4 (IC4) and M8 (IC8):

VT0N f (IC4) + fDBsat(IC4) + n8 · f (IC8) < (8.39) UT

8.7.2 Miller-Compensated Operational Transconductance Ampliﬁer

Minimum Maximum Scaling Parameter Value Value Factor

WM1 = WM2 4 100 1e-6

WM3 = WM4 4 100 1e-6

WM5 4 100 1e-6

WM6 100 1000 1e-6

WM7 100 1000 1e-6 CM 1 10 1e-12

IDM5 1 50 1e-12 Table 8.4: Search Ranges for Primary Design Variables of MC-OTA

The second benchmark is a miller-compensated operational transconductance ampliﬁer (MC-OTA) [80] and is shown in the ﬁgure 8.6. The primary variables are their search ranges

121 are presented in Table 8.4; secondary variables are presented in Table 8.5. The saturation conditions for MC-OTA are shown in Table 8.6.

Vdd

M3 M4

a b M6

M1 M2 Vin− Vin+ Vout 2 c

Vg M7 M5

Vss

Figure 8.6: Miller Compensated OTA

Secondary Variables Equations

IDM5 IDM1 = IDM2 = IDM3 = IDM4 2

IDM5 ·WM7 IDM6 = IDM7 WM5 Table 8.5: Secondary Variables in Terms of the Primary Design Variables for MC-OTA

8.7.3 Results and Discussion

Tables 8.7 and 8.8 present the synthesis results for the TSO. Tables 8.9 and 8.10 present the synthesis results for the MC-OTA. All the speciﬁcations were and the circuit was simulated to verify the accuracy of the resulting performance parameters. It can be seen in Tables 8.7 and 8.9 that the deviation of the synthesis results from the simulation results is within 10%. The accuracy of the results in Table 8.7 show a signiﬁcant improvement when compared to a similar gm/ID method used by Cortes et. al. in [18], which uses BSIM3v3 model gm/ID vs IN characteristics along with hand derived equation for performance parameters. The use

122 Device Saturation Conditions

M1, M2 fDBsat(IC2) + n6 · f (IC6) n ·V − V − (n − 1)·V + n ·V + V < 2 dd in+ 2 ss 2 T0P T0N UT −V M f (IC ) + f (IC ) − n · f (IC ) < T0P 4 4 DBsat 4 6 6 UT V − V − V M f (IC ) + f (IC ) + f (IC ) < ss in− T0N 5 2 5 DBsat 5 n1·UT M f (IC ) + f (IC ) < Vdd − Voutmax 6 6 DBsat 6 UT V − V M f (IC ) + f (IC ) < outmin ss 7 7 DBsat 7 UT Table 8.6: Saturation conditions for the Transistors of MC-OTA

%Err (EKV + %Err (BSIMv3 + Parameter Specs. Mod. gm/ID Syn. HSpice Sim. SPM) Eqn) [18] gain (dB) ≥ 90 94.89 101.32 -6.35% +16.83% f−3dB (Hz) ≥ 100 113.59 107.13 +5.69% -2.39% ug f (Hz) ≥ 106 3.80 × 106 3.82 × 106 -0.52% -0.92% pm (◦) ≥ 60 60.16 59.09 +1.81% +6.38%

Table 8.7: Modified gm/ID Synthesis Results for Twostage Opamp of simplified equations leads to significant inaccuracy as it does not take into account all the small-signal parameters, and uses approximate equations. Therefore, by using the complete small-signal model for deriving complete expressions for performance parameters, our method offer huge improvement. The use of EKV MOSFET model, instead of BSIM3v3, leads to a significantly smaller current (14µA versus 280µA) for similar performance specifications. This can be attributed to better modeling of the weak and moderate inversion region in the EKV Model. The values of the primary variables (device sizes and bias current) for TSO, obtained by synthesis, is presented in Table 8.8. Transistors M1, M2, M3, M4 & M8 operate close to the moderate inversion region, and transistors M5, M6 & M7 operate close to the strong inversion region. The values of the primary variables for MC-OTA is presented in Table 8.10. Table 8.11 presents the timing results for the synthesis of TSo & MC-OTA using the proposed methodology. Our method is compared to two synthesis approaches. The first comparison (#1) is with

123 Device/ Size/ Inversion Parameter Value Current Coefﬁcient (IC)

M1 = M2 142 µm 6.44 µA 2.91 M3 = M4 38 µm 6.44 µA 2.56 M5 115 µm 12.88 µA 7.18 M6 125 µm 14 µA 7.18 M7 601 µm 67.312 µA 7.18 M8 406 µm 67.312 µA 2.50 Cc 3.5 pF - - Ibias 14 µA - - Table 8.8: Synthesis Results for Primary Design Variables of Twostage Op Amp

%Err (EKV + Parameter Specs. Mod. gm/ID Syn. HSpice Sim. SPM) gain (dB) ≥ 95 101.993 102.078 -0.08% f−3dB (Hz) ≥ 400 439.449 446.684 -1.62% ug f (Hz) ≥ 106 7.397 × 106 7.586 × 106 -2.49%

Table 8.9: Modified gm/ID Synthesis Results for MC-OTA a method which uses SPICE for numerical operating point analysis, and symbolic performance models for performance estimation. For TSO, the speedup is 12× for the total time per iteration. The small-signal values are estimated 17× faster per iteration using our synthesis method. The second comparison (#2) if with a method which uses, SPICE for both operating point and AC analysis. The analysis time speedup in each iteration is 42×. The performance model evaluation time is 37× faster, and the total per iteration time is 40× faster than the numerical-simulator based synthesis approach. Enforcing the saturation conditions help in three ways. It ensures that valid performance results are obtained, since gm/ID vs. IN characteristics presented in this work are valid only for saturation. So for correctness of synthesis results, saturation conditions can be classified as a necessity. The other two advantages are by-products of applying the saturation conditions. The design which result from such a synthesis are robust, as they satisfy the sizing rules constraints of keeping transistors in saturation. The other benefit is a further reduction in the per iteration time. In several iteration, if any one transistor is found to be in saturation, the performance estimation part of that iteration is skipped. In Figure 8.7, it can be seen that the number of saturation iteration is a mere fraction of the total number of iteration, near the start of synthesis. As the optimizer explores several areas of the design space, the number of valid designs (number

124 Device/ Size/ Inversion Parameter Value Current Coefﬁcient (IC)

M1 = M2 25 µm 2.5 µA 1.51 M3 = M4 34 µm 2.5 µA 4.78 M5 20 µm 5 µA 3.80 M6 350 µm 25 µA 4.64 M7 100 µm 25 µA 3.80 CM 0.1 pF - -

IDM5 5 µA - - Table 8.10: Synthesis Results for Primary Design Variables of MC-OTA of designs satisfying the saturation constraints) is very small. But, as the optimizer zeros in on a certain design space, towards the end of the synthesis process, the number of valid designs increasing signiﬁcantly. So, all the invalid designs have a much smaller per-iteration time, which further reduces the average total iteration time.

8.8 Discussion on Possible Improvements

The deviation in the results obtained from synthesis and simulation can be attributed to two parameters: slope factor (n), drain-transconductance (gds). Here, a method is examined which can possibly lead to a better characterization of the slope factor. As is mentioned earlier, that a way to obtain gm, is to use the gm/ID vs. IN curve. The value is gm obtained from such a curve is very accurate. Now, in Equation 8.17, it can be observed that, gm is inversely √ proportional to n and IC. From this observation, there can be two possible way to characterize the slope factor better. The ﬁrst way is to replace the expression for IC (Equation 8.2, in

Equation 8.17. The result is an equation relating gm and n, since the parameters ID, W, L, and

IT are known. The other way to proceed is to plot the gm/ID vs. IC characteristics, as shown in figures 8.8 and 8.9. From these plots it is observed that for different transistor widths (with constant length), the curves vary only very slightly in the strong inversion region. The gm/ID obtained from the gm/ID vs. IN plot can be used to obtain IC from gm/ID vs. IC curve. The value of IC thus obtained can be plugged into equation 8.17 to get the value of slope factor. A way to improve the entire idea is to enhance the synthesis methodology itself. It can be modified to stop only when several design points, which satisfy all performance constraints, have been obtained. This ensures that the probability of obtaining a design, which satisfies

125 Synthesis Performance Estimation Total Comparison Approach & Small-Signal Model Iter. Speedup + AC Analysis Eval. Time Numeric OP + SPM 0.223s 0.0055s 0.229s TSO#1 Mod gm/ID + SPM 0.013s 0.0055s 0.019s Speedup ≈ 17x 1x ≈ 12x Numeric OP + SPICE 0.551s 0.205s 0.756s TSO#2 Mod gm/ID + SPM 0.013s 0.0055s 0.019s Speedup ≈ 42x ≈ 37x ≈ 40x Numeric OP + SPM 0.217s 0.0052s 0.223s MC-OTA#1 Mod gm/ID + SPM 0.014s 0.0052s 0.02s Speedup ≈ 16x 1x ≈ 11x Numeric OP + SPICE 0.54s 0.198s 0.743s MC-OTA#2 Mod gm/ID + SPM 0.014s 0.0052s 0.02s Speedup ≈ 39x ≈ 38x ≈ 37x

Table 8.11: Time Results of Synthesis for TSO & MC-OTA all constraints during verification by simulation, is increased. Since the synthesis is sped up significantly by using the modified gm/ID method in synthesis, the additional cost of obtaining several design solution can be tolerated. Techniques to improve the characterization of gds also need to be explored.

8.9 Future Application to Layout-Inclusive Synthesis

The synthesis method presented here can also be applied to layout-inclusive circuit synthesis. An extracted netlist, with parasitic capacitances, is the same as the original netlist, for operating point analysis. The value of small-signal transconductances can be generated by using the method presented earlier. The method to obtain saturation conditions also remains valid. The difference arises in the calculation of capacitance values for the small-signal model. In addition to the intrinsic capacitances, the external capacitances due to the layout-geometry of the transistors, will have to be taken into account. The symbolic performance models will also differ, as the parasitic-capacitances will be accounted for in the SPM’s for layout-inclusive synthesis.

126 Saturation/Non−Saturation Iteration Counts 8000 Sat 7000 Not−Sat Total 6000

5000

4000

Iteration Count 3000

2000

1000

0 0 1000 2000 3000 4000 5000 6000 7000 8000 Iteration Count

Figure 8.7: Saturation/Non-Saturation Iteration Counts 8.10 Conclusions

In this work we have presented a modified gm/ID design methodology, which produced on-grid device sizes. A systematic way to obtain the saturation conditions for the EKV MOS- FET Model has been developed in this work. Other EKV MOSFET model based techniques do not verify if the transistor is in saturation [85, 38, 4], and therefore are inherently flawed. Our approach also accounts for all small-signal parameters, transconductances and intrinsic capacitances, instead of a subset of these parameters. The other important contribution of the proposed technique is the use of variable slope factor, related to the inversion-levels, instead of using a fixed slope-factor [80, 11, 4]. The proposed design approach is then used for synthesis of analog circuits. Numerical operating point analysis is avoided during each iteration, and performances are evaluated only for design points which satisfy saturation conditions. Because of these reasons there is significant gain in speed. The synthesis results in robust designs, since the sizing rules constraints, proposed by Graeb et. al in [44], is satisfied by ensuring that transistors are in saturation. These designs are also conducive for layout generation since the device dimensions lie on the layout grid.

127 gm/ID vs. IC (0.5um − nmos) 30 W = 4u W = 40u 25 W = 400u

Transconductance Efficiency: gm/ID 5

0 −2 −1 0 1 2 10 10 10 10 10 Inversion Coefficient: IC = if

Figure 8.8: Transconductance Efﬁciency vs Inversion Coefﬁcient (NMOS)

gm/ID vs. IC (0.5u PMOS) 30 W = 4u W = 40u 25 W = 400u

Transconductance Efficiency: gm/ID 5

0 −1 0 1 2 10 10 10 10 Inversion Coefficient: IC = if

Figure 8.9: Transconductance Efﬁciency vs Inversion Coefﬁcient (PMOS)

128 Chapter 9

Conclusions and Future Work

Analog circuit synthesis is a critical piece in the productivity-puzzle for today’s, and tomorrow’s, consumer driven electronics market. By developing efficient tools, which yield robust analog designs quickly, the time-to-market for systems-on-chip can be decreased significantly. A good analog synthesis tool will make it easier to handle complex designs, and therefore increase the productivity of the designer. The focus of the research, presented in this dissertation, has been to solve some of the basic, yet critical, issues plaguing traditional analog synthesis methodologies. As has been mentioned earlier, the two serious arguments against the prevalent analog synthesis approaches are: A) the unawareness to layout parasitics, and B) expensive computation cost involved in performance estimation. The first concern threatens the validity of a synthesized design itself. Since, a design is obtained without taking into account the post-extraction parasitics, it often happens that, in the verification stage the design fails to yield the desired performance. The second problem, is directly linked to growing paranoia of time-to-market. How fast can a design be synthesized? Both these issues have been addressed by researchers in recent times. To account for layout-parasitics, parasitic estimation techniques have been proposed. Even though an estimation technique is speedy, we argue that with shrinking feature size and growing demand for high performance, it is just not enough to ”estimate” parasitic-effects. We propose a synthesis approach with complete layout generation and extraction inside each iteration, and we term this approach the layout-inclusive methodology. It is important to note here that, the type of synthesis process discussed here is optimization- based, i.e., a search-algorithm guide the entire process. There are several ways to speed up this

129 kind of a synthesis algorithm, namely, by developing better, more efficient, search techniques, or by using performance models instead of full-blown simulations to predict performance. The work presented here, assumes that we have a good search-algorithm, and the focus is on reducing the performance estimation time. We believe that a performance model that captures accurately, the behavior of a circuit, should be easy and fast to generate, and should have a physical base, i.e., a direct correlation to the circuit parameters. Two promising performance modeling techniques are: marcomodeling and symbolic analysis-based modeling. While performance macromodels can be evaluated extremely fast, they are difficult to generate, require pre-generated data, hence are inefficient to obtain, and are limited by the number of circuit variables that can be handled. Symbolic-analysis based models (named, symbolic performance models (SPMs) by us), can be generated very efficiently, can handle several circuit parameters and can be evaluated very fast, and therefore, are the models of our choice. So, to summarize, the research presented here focusses on two aspects of analog synthesis - layout-parasitics and performance estimation. Next, the specific contributions of this endeavor to the area of analog synthesis, are listed and discussed next. Also highlighted are their advantages and limitations. The last section of this chapter presents future directions of research.

9.1 Contributions

Symbolic Performance Models (SPMs) and their use in Synthesis [15, 71]

• Element-Coefﬁcient Diagrams (ECDs) have been used for generating symbolic performance models. The accuracy of SPMs in comparison to the numerical simulator Ngspice has been studied. The efﬁciency of using SPMs, over numerical simulations, is shown. ECDs have been converted to C++, compiled to create ECD libraries. A study has been conducted to analyze the evaluation time of compiled ECDs vs ECDs residing in the memory. It has been concluded that it is advantageous to used compiled ECDs for performance estimation during circuit synthesis.

• A new comprehensive symbolic performance modeling framework has been developed. It includes modules like nodes information generator, circuit expander, symbolic analyzer etc.

• A technique to model noise ﬁgure using symbolic analysis has been researched and devel-

130 oped. The technique is extension of a previously used method for spectral noise density. Compiled ECDs have been used to capture the effect of several noise sources ta the output.

• Symbolic performance models for distortion parameters, based on weakly-nonlinear symbolic analysis, have been used in this work. These models have been integrated to the SPM framework mentioned above and have been modiﬁed to use compiled ECDs.

Generation of Parasitic-Inclusive Topologies and Performance Models [68, 71]

• Techniques to generate topologies including parasitic capacitances have been developed. The capacitances accounted for are module and interconnect parasitic capacitances, which include both area and coupling capacitances. Three approaches for capacitance inclusion have been developed. The impact of each of these technique on generation and compilation of ECDs has been studied. The accuracy of each of the methods has also been studied. Techniques to include interconnect parasitic-resistances have also been developed.

• For the layout-inclusive synthesis of an LNA using SPMs, parasitic-inclusion techniques for interconnects represented by the PEEC Model have been developed.

Hierarchical Symbolic Analysis and Performance Modeling [69]

• Even the determinant decision diagram based ECDs can not analyze medium-to-large analog circuits. The problem is compounded in the case by parasitic-inclusive topologies. A transfer-function synthesis based hierarchical symbolic analysis technique has been developed. The technique lays the foundation for library-based symbolic analysis. The efﬁciency and limitations of the technique have been thoroughly analyzed.

• The aforementioned hierarchical technique is used to generate symbolic performance models for large parasitic-inclusive analog circuits. The topologies are generated by ex- ploiting the modular structure of any analog circuit.

Layout-Inclusive Synthesis Approaches [68, 70, 71]

• A layout-inclusive synthesis for analog circuits, like opamps and ﬁlters, has been developed. The approach uses module-speciﬁcation language (MSL) system for layout gener-

131 ation and instantiation; MAGIC extractor for layout extraction and symbolic performance models for performance estimation. The optimization engine uses simulated annealing.

• A synthesis methodology, similar to the one proposed for analog circuits, for Low Noise Ampliﬁer is developed. The method uses a quasi-static extraction tool, VPEC, for interconnect parasitic inductances and resistances.

• Layout-inclusive circuit synthesis is extended to parasitic-inclusive large analog circuits using hierarchical symbolic performance models.

Solution to the DC Operating Point and it’s use in Synthesis

• The equations for small signal parameters have been extracted from the EKV MOSFET model manual and papers. Conditions for saturation of a MOS transistor have been derived from EKV model equations.

• A modiﬁed gm/ID methodology for analog design has been proposed which results in on-grid device sizes. This method is then used for synthesis of analog circuits along with symbolic performance models.

9.2 Directions for Future Work

In this dissertation, we have used symbolic performance models in place of numerical simulations, during synthesis. The advantage of SPMs over simulators like SPICE, is that, during synthesis, the circuit is not analyzed in every iteration. Instead, equations in form of element-coefficient diagrams, are used for performance estimation. In spite of these advantages the use of SPMs is not very prevalent in automated circuit synthesis. This is attributed to the fact that today only linear or weakly nonlinear AC analysis is possible using them, whereas, numerical simulators can handle strongly nonlinear behavior and time-domain analysis. In this work, we have shown that use of SPMs in layout-inclusive synthesis holds significant promise in terms of speedup and parasitic closure. We have also developed a synthesis technique based on modified gm/ID method, in order to bypass the DC operating point analysis in each iteration. We have shown that a combination of gm/ID based synthesis and SPMs has tremendous potential. Keeping in mind, the promise of techniques presented in this dissertation, the directions for the future work can be divided the following areas.

132 1. Symbolic Performance Modeling: The focus should be on developing models for nonlinear performance parameters like slew rate, IIP3, etc. In order to generate SPMs for these parameters, symbolic analysis techniques, targeting circuits with hard non-linearity, have to be developed. Some very promising work on highly non-linear symbolic analysis is presented in [66]. This work uses concepts of piecewise linear modeling and determinant decision diagrams for analyzing non-linearities. The other area of focus should be on symbolic transient analysis. Techniques have proposed in [45], [53] and [52] but stable and mature algorithms are still scarce in this field. A very recent work in symbolic techniques for time domain analysis [15], is being integrated in a our layout-inclusive synthesis flow. Another area related to symbolic performance modeling, is model order reduction (MOR), where the aim is to generate reduced order models, while retaining the accuracy of complete models. Recent efforts in symbolic model order reduction by Shi et al. [56], show that SMOR techniques are very effective, both in terms of accuracy and speed of evaluation, for large analog circuits. Further advancements in SMOR techniques, could possibly eliminate the need for hierarchical analysis, and prove to be a very efficient tool for performance estimation.

2. Hierarchical Symbolic Analysis: The hierarchical symbolic analysis presented in this dissertation, can be used to develop a completely library-based symbolic analysis technique. We have shown exactly how libraries of transfer functions can be used in hierarchial symbolic analysis. Now, the focus should be on development of libraries for all possible variations of common analog modules. Our hierarchical technique can be improved by developing an efficient technique for the inversion of symbolic matrices. Currently, we use MATLAB/Mathematica to obtain this inverse. However, we believe that if determinant decision diagrams are used to store the determinants of the target matrix and it’s co-factors, a very efficient technique for symbolic matrix inversion can be developed. The advantage of such a technique would be significantly reduced spatial complexity, in comparison to techniques like LU decomposition, which are used in symbolic packages of Matlab/Mathematica.

3. Operating Point Analysis: As was mentioned earlier in Chapter 8, the deviation in the results obtained from synthesis, and those from simulations, can be attributed to two

parameters: slope factor (n), drain-transconductance (gds). We have discussed two techniques accurately characterize these parameters. We believe that the deviation in results can be reduced greatly by taking these measures. The synthesis methodology can also

133 be improved to produce several design points which meet all performance speciﬁcation.

Such modiﬁcation is possible because of extremely fast synthesis. The proposed gm/ID design method can be applied to layout-inclusive synthesis. In order to do so, techniques to accurately model extrinsic MOS capacitances will have to be developed.

4. Layout-inclusive synthesis: The proposed synthesis methodology can be improved by using pre-layout extraction techniques proposed in [9]. A possible area of research is combining the parasitic-aware synthesis method proposed in [28] and SPMS, to produce

even faster synthesis techniques. Symbolic time domain method from [15] and gm/ID design method, can also used in layout-inclusive synthesis to improve the efﬁciency of our proposed algorithm. These techniques can also be used, in conjunction with hierarchical SPMs, for layout-inclusive synthesis of large analog circuits. One area where our method can be improved is in the quality of layouts obtained after synthesis. We believe, that multi-placement structures [10] can help in that aspect. The other areas of research can focus on improving the yield by using techniques of design for manufacturability like design centering, yield optimization etc.

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