University of Cincinnati

UNIVERSITY OF CINCINNATI Date:___________________ I, _________________________________________________________, hereby submit this work as part of the requirements for the degree of: in: It is entitled: This work and its defense approved by: Chair: _______________________________ _______________________________ _______________________________ _______________________________ _______________________________ Automated Layout-Inclusive Synthesis of Analog Circuits using Symbolic Performance Models A dissertation submitted to the Division of Research and Advanced Studies of the University of Cincinnati in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY in the Department of Electrical and Computer Engineering and Computer Science of the College of Engineering 2005 by MUKESH RANJAN B.E. Electrical Engineering S.V. National Institute of Technology, Surat, India, 2000 Thesis Advisor and Committee Chair: Dr. Ranga Vemuri Abstract A key task in the automated design of analog/RF circuits is circuit sizing, a process that involves assigning numerical values to unknown circuit parameters of a fixed topology, while being subjected to a set of performance constraints. Over the years, the terms sizing and synthesis have been used interchangeably, and have become synonymous in the analog domain. Mature tools for the synthesis of digital circuits are abundant, but the market for analog synthesis tools is still growing and very few commercial products exist. Several techniques have been developed in the past for analog synthesis, ranging from knowledge-based methods to techniques using numerical simulation. A frequently used technique involves an iterative stochastic search, which uses numerical simulations at every probable design point, in order to obtain the performance metrics. Expensive computations and parasitics unawareness of this traditional method necessitates a scheme which can produce fast layout aware designs. In this dissertation a new synthesis methodology, which uses parameterized layout generators and symbolic performance models (SPMs) inside the synthesis loop, has been developed to overcome the deficiencies of the previous circuit sizing method. This layout-inclusive (layout- in-loop) approach uses efficient parameterized procedural layout generators, obtained using the module-specification language (MSL) system, for speedy layout instantiation. Fast performance estimation is achieved by using pre-compiled SPMs, which are symbolic representation of circuit performances, obtained using symbolic analysis. The transfer functions of SPMs are stored as efficient symbolic graphs called element-coefficient diagrams (ECDs). Techniques to include layout geometry effects in the SPMs have also been developed. This method is used for the synthesis of opamps and filters. The method proposed above for analog circuits is then applied to the synthesis of an RF low-noise amplifier (LNA). This method also uses symbolic performance models (SPMs), and parameterized layout generator along with high-frequency extraction techniques in the synthesis loop. SPMs for noise figure and distortion parameters are developed using repetitive and weakly nonlinear symbolic analysis and are stored as pre-compiled ECDs. Full parasitic extraction is done by using multiple extractors. Quasi-static extraction is used to obtain the critical parasitic effects of interconnects and on-chip inductors. Further in the dissertation, efforts are made to overcome the shortcomings of the proposed method. The first limitation is the size of circuits that can be synthesized. It arises because of the limit on the size of ECD-code that can be compiled by a standard GNU C++ compiler. To overcome this bottleneck, a new comprehensive method and framework for exact symbolic analysis of large analog circuits is developed. The method is based on the concepts of hierarchical circuit decomposition, subcircuit symbolic analysis and transfer function synthesis. Node tearing methods have been used for decomposition and element-coefficient diagrams (ECD) based method is used for symbolic analysis of subcircuits. One of the key contributions of this work is a generalized methodology for transfer function synthesis, encompassing all interconnection templates for any two subcircuits. The method leads to the development of an easily automatable and efficient algorithm for generation of symbolic transfer function of large circuits. The hierarchical technique, developed in this work, is then used for layout-inclusive synthesis of large analog circuits. Techniques have been developed to generate the list and interconnection of subcircuits which undergo hierarchical symbolic analysis. A circuit is decomposed into common building blocks of analog circuits, for which netlists are obtained by an extraction of corresponding layout modules. The interconnection parasitics may or may not exist in the module netlists and therefore they may form subcircuits of their own. The other shortcoming of this work is that of time during performance estimation is spent on operating point analysis using SPICE, a numerical simulator. To remove this dependence on numerical simulation and further speedup synthesis, we have developed a modified gm=ID method and used it for synthesis of analog circuits. EKV MOSFET model equations for all small-signal parameters, have been extracted, and the conditions for a transistor to be in satura- tion, have been derived. To My Parents Asha & Sureshwar Pandey Acknowledgements I would like to express my deepest gratitude and sincerest thanks to Dr.Ranga Vemuri for his guidance and support throughout my PhD work. I would like to thank Dr. Hal Carter, Dr. Wen-Ben Jone, Dr. Carla Purdy and Dr. Adrian Nunez-Aldana for being a part of my dissertation committee and offering me valuable suggestions. This work was supported in part by the Defense Advanced Research Projects Agency and the Sensors Directorate of the Air Force Research Laboratory, U.S. Air Force, Wright- Patterson AFB, OH, under Contract F33615-01-C-1977, and the National Science Foundation under award number CCF-0429717. I would like to acknowledge their support. I would like to thank Dr Georges Gielen and Wim Verhaegen, Katholieke Universiteit, Leuven, Belgium, for their permission to use the DDKUL software. Their guidance also has been very important in my research. I thank Dr. Andrea Pacelli for the VPEC software suite. I also thank my colleagues Anuradha and Amitava for letting me use their software. My life has been shaped by ideals of my parents, and I thank them for setting such a good example for me to follow. I thank them for all their sacrifices, their unwavering support and constant encouragement. I thank all my family members for all the love and care they have showered on me. My life in Cincinnati has been made special by the presence of Varsha. She has been a wonderful companion and my best friend. It is difficult to imagine the completion of my PhD without her support. Finally, I thank all my friends, who have made this stay wonderful - Andy and Bharath, my roommates; Anuradha, Raoul, Hemanth, and Veena, my closest friends and colleagues; Beth, Heather and Matt, for teaching me the ropes of the american culture; DDELites - Mad- hubanti, Jawad, Vijay, Glenn, Amitava, Vipul, Manish, Ritochit, Shubhankar, Huiying, Meng- meng, Xin, Bala, Akhil, Prasun, Harish, Renqui, Vikas, Shyam, Jayanthi, Siva, Sairavi, Sunder, Srinivas, Rajesh, Elena, Iyad, Sree; AIDers - DC, Senthil, Mahesh, Sri; SACUBers - Rishi and Jim, and 310-ers - Nitin, Arjun, Jill, Alex, Joshi, Nawab, Shagun, Ashima, Anurag, Dilip, Aditi, Anand, Dhananjay, Avinash, Rama, Manish, Anshul. Thank you all. Contents List of Figures v List of Tables vii 1 Introduction 1 1.1 Analog/Mixed-Signal Design . 2 1.2 Analog Circuit Synthesis: An Overview . 3 1.3 Issues with Analog Synthesis and Related Work . 6 1.3.1 Performance Evaluation . 6 1.3.2 Parasitic Closure . 6 1.4 Research Overview . 8 1.4.1 Symbolic Performance Modeling . 8 1.4.2 Parasitic-Inclusive Topology Generation . 9 1.4.3 Layout-Inclusive Synthesis using Symbolic Performance Models . 10 1.4.4 Hierarchical Symbolic Analysis and Performance Modeling . 10 1.4.5 Solution to the Operating Point and Use in Synthesis . 11 1.5 Dissertation Outline . 12 2 Layout-Aware Analog Circuit Synthesis 14 2.1 Introduction . 14 2.1.1 Parasitic-Aware Circuit Synthesis . 14 2.1.2 Layout-Inclusive Circuit Synthesis . 15 2.2 Related Work . 16 2.3 Layout-Inclusive Synthesis using Numerical Simulations . 17 2.4 Circuit Sizer . 18 2.4.1 Optimization Engine . 20 2.5 Layout Generation and Instantiation . 20 2.5.1 MSL Program Structure . 21 2.6 Layout Extraction . 24 i 2.7 Summary . 26 3 Symbolic Analysis based Performance Modeling 27 3.1 Introduction . 27 3.1.1 Symbolic Analysis . 27 3.1.2 Symbolic Analyzers vs. Numerical Analyzers . 28 3.2 Symbolic Analysis Techniques . 29 3.3 Hierarchical Symbolic Analysis . 32 3.3.1 Circuit-level hierarchy . 32 3.3.2 Expression-level hierarchy . 32 3.4 Symbolic Performance Model Generation . 32 3.4.1 Determinant Decision Diagrams . 35 3.4.2 Element-based Coefficient Diagrams . 35 3.4.3 Compilation and Evaluation of ECDs . 37 3.4.4 Accuracy of Symbolic Performance Models . 39 3.5 Summary . 39 4 Layout-Inclusive Analog Synthesis using Symbolic Performance Models 40 4.1 Proposed Circuit Synthesis Approach . 40 4.1.1 Layout Generation and Instantiation . 41 4.1.2 Symbolic Performance Modeling . 41 4.2 Inclusion of Layout Effects in Symbolic performance Models . 42 4.2.1 Inclusion of Layout Parasitic Elements . 43 4.2.2 General Inclusion of Fingered Transistor Effects . 50 4.3 Experimental Results . 51 4.4 Conclusions . 52 5 RF Low Noise Amplifier Synthesis 54 5.1 Proposed RF Circuit Synthesis Method . 55 5.1.1 Layout Generation and Instantiation . 55 5.1.2 Multi-way Layout Extraction . 56 5.1.3 Post Processing of Extracted Netlists . 57 5.1.4 High-Frequency Symbolic Performance Models . 58 5.2 Inclusion of Layout Effects in SPMs . 60 5.3 Experimental Results . 62 5.3.1 Setup . 62 5.3.2 Results and Discussion . 63 5.4 Conclusions . 64 ii 6 Exact Hierarchical Symbolic Analysis of Large Analog Circuits 65 6.1 Introduction & Related Work .

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