YMTC 64L 3D NAND Product Brief

March 2020 GLOBAL LEADER IN IP & TECHNOLOGY INTELLIGENCE

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Markets Devices Scope

Consumer Electronics DRAM Memory Product Teardowns & Costing / BOM Mobile Devices NAND Flash Memory Structural / Materials Analysis Medical Devices Microprocessors / Controllers Packaging Analysis Storage Devices Wireless R/F Circuit Extraction and Analysis Automotive Electronics Analog Transistor Characterization Internet of Things Antennas Waveform Analysis Semiconductors Power Management Functional Testing Wi-Fi Sensors Software Analysis Clean-Tech Devices Displays Optoelectronics

▪ TechInsights constantly monitors the product releases of new advanced memory products. ▪ As new products are launched, we conduct exploratory analysis to find industry innovations and disruptions. When we find a device of interest, we subject it to more comprehensive analysis

Analysis complete; reports available now Analysis in progress Samsung Toshiba Intel/Micron SK hynix YMTC 92L 3D V-NAND 96L 3D BiCS 96L 3D NAND Flash 4D (PUC) 96L NAND 3D 64L Xtacking TLC • Samsung 970 EVO Plus • Toshiba XG6 SSD • Crucial BX500 960GB SSD • SK hynix SSD NAND SSD KXG60ZNV256G CT960BX500SSD1 • HFB1A8MQ431A0MR • K9DUGY8J5B-DCK0 • TH58LJT0T24BADE • MT29F512G08EBHBFJ4-R (H25FT4MM1 die)

Semiconductors play a pivotal role in China's state-backed investment in Market share held by leading NAND Flash memory cutting-edge memory chips. The "Made manufacturers worldwide in China 2025" initiative, unveiled three years ago, aims to upgrade the country's manufacturing sector.

Yangtze Memory Technologies was poised to become China's first mass- producer of 3D NAND flash memory chips and TechInsights has now confirmed it’s presence.

This will be sure to disrupt the 52 billion NAND Memory Market and its respective https://www.statista.com/statistics/275886/market-share-held-by-leading-nand-flash-memory- Market Leaders. manufacturers-worldwide/

We have found 3D 64L Xtacking® TLC NAND devices manufactured by Yangtze Memory Technologies Co., Ltd. (YMTC).

We are seeing 73 gates in total for a vertical NAND string with nine vertical Top-metal viewed die photo showing the very small/compact die with higher memory bit density channel (VC) holes, including one dummy hole between common source line contacts. It is likely that 5 select gates (1 SSG and 4 DSGs) and 4 dummy gates are also used.

Delayering NAND array level die photo (Hybrid bonded)

B-ploy die photo (Hybrid bonded)

▪ In Xtacking architecture, periphery circuits and memory cell operations are processed on a separate wafer, resulting in higher array efficiency and memory bit density than conventional 3D NAND solutions, such as Samsung 64L V-NAND and KIOXIA/WD 64L BiCS NAND. For example: ▪ YMTC 64L 256 Gb die bit density is 4.41 Gb/mm2 which is higher than Samsung 64L 256 Gb die (3.42 Gb/mm2), and comparable to Micron/Intel 64L CuA FG 256 Gb TLC die (4.40 Gb/mm2)

YMTC Xtacking uses Wafer-to-Wafer hybrid bonding technology, meaning the NAND array is upside-down on periphery circuits. The process integration consists of: 1. Metal 1 through Metal 4 for periphery circuits on a wafer 2. NAND array with a source plate (SP) and Metal 1’ through Metal 3’ on a separate wafer

3. Wafer-to-Wafer hybrid bonding to connect M4 X-section SEM image along BL direction showing Xtacking architecture and Metal 3’ 4. Through SP Via and Metal 5. Here, Metal 1’ is for BL

Teardown and Costing Floorplan and Node Design Elements

Transistor Advanced Process & Characterization Circuit Analysis Packaging Process Flows

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Custom Analysis TechInsights has been providing technology analysis for over 30 years, enabling our customers to advance their intellectual property and product strategies. If our library does not currently have LEARN MORE the analysis you are looking for, we want to speak with you. Our custom analysis capabilities span the following markets, devices, and scope.

TechInsights has a considerable amount of analysis planned for this part, including the reports listed below:

Report Name Description Report Code Subscription Channel

Top metal and polysilicon planar die image, SEM X-section, YMTC 64L NAND Memory NAND Floorplan process proof, floorplan analysis and die utilization including MFR-2003-801 Floorplan Analysis Report (MFR) block sizes and functionality, die and package cost

YMTC 64L NAND Memory Design Plan view SEM image set with hierarchical schematics of NAND Peripheral MDP-2003-801 – Periphery target blocks Design (MDP)

YMTC 64L NAND Process Flow Spreadsheets showing process architecture, mask list, and Process Flow Analysis PFA-2003-803 Analysis integration-level process steps (PFA)

SEM planar and X-sections, TEM EDS and EELS, SCM, SIMS YMTC 64L NAND Advanced and other advanced techniques of structural and material AME-2003-801 Process (AME) Memory Essentials analysis

YMTC 64L NAND Process Flow Process flow steps and 3D emulations of advanced Process Flow Analysis PFF-2003-802 Full Analysis semiconductor technologies. (PFF)

Plan view SEM image set with hierarchical schematics of Circuit Analysis YMTC 64L NAND Circuit Analysis CAR-2003-801 target blocks Reports (CAR)

10 TechInsights CONFIDENTIAL. All content © 2020. TechInsights Inc. All rights reserved. Memory Floorplan Analysis Report (MFR) An overview of leading-edge NAND and 3D NAND design SEM X-Section WL SEM X-Section BL Floor Plan Analysis

This report includes: ▪ High-resolution SEM cross-sections Critical Dimensions ▪ Critical dimensions ▪ Functional Block Summary ▪ Detailed images of package and die ▪ CircuitVision™ enabled stack images

A concise analyst’s summary of critical device metrics: ▪ Circuit schematic diagram of a page buffer: decoder, switch, and controller ▪ Circuit schematic diagram of a wordline driver: decoder and switch ▪ Detailed stacked plan view SEM images of a beveled NAND page buffer and wordline driver delivered in CircuitVision™. Includes calibrated measurement and annotation tools.

Critical Dimensions Memory Array Block Layout and CircuitVision: Stacked Dimensions plan view SEM Images

Schematics: Page Buffer Wordline Driver SEM Layout

This report will provide: ▪ A detailed understanding of all aspects of an advanced memory technology ▪ An opportunity to leverage this broad understanding to guide your next-node technology choices

Advanced Memories Advanced Memories Advanced Packaging V-NAND DRAM Performance/Cost Paradigm Shift

Package

Tightest pitches New Materials Interposer TSV First to 3D Novel Integrations

PoP

AME Report Details Deep Analysis Process Process Assumptions Process Steps Emulation Tabulation

Process flows are reconstructed from images and material analysis in the TechInsights’ database Layout Analysis (Memory Cell)

Front End of Line Middle End of Line Back End of Line (FEOL) (MEOL) (BEOL)

Full Circuit Analysis covers: ▪ Memory Array and Peripherals ▪ Address Path ▪ Data Path ▪ Control Blocks, Configuration and Test Block ▪ Voltage Generators System

TechInsights has over 30 years of experience working with circuit patent holders and circuit design teams to deliver analysis that supports IP and technology investment decisions. Whether mining your circuit portfolio to develop a licensing campaign and generate EoU, or providing a design team with standard cell analysis and design, we have got your needs covered. Easily study circuit hierarchy and analyze layout through schematics or multilayer metallization including search, index and trace signals functionality. Hierarchical schematics demonstrate the design from the block down to gate level - all linked to the original layout, showing the extracted gates and associated interconnects. Our reports feature: ▪ Fully reconstructed metallization with associated signal names CLICK IMAGE FOR A DEMONSTRATION ▪ Annotation of all active devices – gates, transistors, passives ▪ Signal tracing through layout and schematics

Report Name Manufacturer Analysis Type Product Code Availability

Micron 512 Gbit TLC 96L 3D NAND (MT29F512G08EBHBFJ4-R:B) Micron Technology Functional – WAR-1912-801 In Creation Internal Waveform Analysis Testing Samsung K9DUGY8J5B 92L 3D V-NAND Selected Area SEM Samsung Circuit ICS-2002-901 In Creation Image Set CircuitVision Analysis on the SK Hynix HFB1A8MQ431A0MR 96- SK Hynix Circuit CAR-1904-802 Published Layer 3D NAND Flash Memory Intel/Micron MT29F512G08EBHBF-R_B Selected Block Circuit Micron Technology Circuit CAR-2002-801 Published Analysis Report Intel 29F04T2ANCQJ1 96L 1Tb QLC 3D NAND Memory Floorplan Intel Process MFR-1912-802 Published Analysis TH58LJT0T24B 96L NAND Process Flow Full Toshiba Process PFF-2001-802 In Creation SK Hynix 96L 3D NAND Flash (HFB1A8MQ431A0MR) - Memory SK hynix Process MFR-1909-801 Published Floorplan Analysis SK Hynix 96L 3D NAND Flash (HFB1A8MQ431A0MR) - Advanced SK hynix Process AME-1909-801 Published Memory Essentials SK Hynix 96L 3D NAND Memory Design - Periphery SK hynix Circuit MDP-1909-801 Published Intel/Micron 96L 3D NAND (MT29F512G08EBHBFJ4-R) Full Circuit Micron Technology Circuit CAR-1906-202 Published Analysis SK Hynix 96L 3D NAND Full Analog Circuit Analysis Report SK hynix Circuit CAR-1904-802 Published Circuit Vision Analysis on the Samsung K9DUGY8J5B-DCK0 (with Samsung Circuit MDP-1905-803 Published a die marking of K9AFGD8J0B) 92-layer NAND Flash - Memory Design - Periphery

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