Pubtex Output 2006.05.23:1026

Cray XD1™ FPGA Development Private S–6400–14 © 2006 Cray Inc. All Rights Reserved. Unpublished Private Information. This unpublished work is protected to trade secret, copyright and other laws. Except as permitted by contract or express written permission of Cray Inc., no part of this work or its content may be used, reproduced or disclosed in any form. U.S. GOVERNMENT RESTRICTED RIGHTS NOTICE The Computer Software is delivered as "Commercial Computer Software" as defined in DFARS 48 CFR 252.227-7014. All Computer Software and Computer Software Documentation acquired by or for the U.S. Government is provided with Restricted Rights. Use, duplication or disclosure by the U.S. Government is subject to the restrictions described in FAR 48 CFR 52.227-14 or DFARS 48 CFR 252.227-7014, as applicable. Technical Data acquired by or for the U.S. Government, if any, is provided with Limited Rights. Use, duplication or disclosure by the U.S. Government is subject to the restrictions described in FAR 48 CFR 52.227-14 or DFARS 48 CFR 252.227-7013, as applicable. Autotasking, Cray, Cray Channels, Cray Y-MP, GigaRing, LibSci, UNICOS and UNICOS/mk are federally registered trademarks and Active Manager, CCI, CCMT, CF77, CF90, CFT, CFT2, CFT77, ConCurrent Maintenance Tools, COS, Cray Ada, Cray Animation Theater, Cray APP, Cray Apprentice2, Cray C++ Compiling System, Cray C90, Cray C90D, Cray CF90, Cray EL, Cray Fortran Compiler, Cray J90, Cray J90se, Cray J916, Cray J932, Cray MTA, Cray MTA-2, Cray MTX, Cray NQS, Cray Research, Cray SeaStar, Cray S-MP, Cray SHMEM, Cray SSD-T90, Cray SuperCluster, Cray SV1, Cray SV1ex, Cray SX-5, Cray SX-6, Cray T3D, Cray T3D MC, Cray T3D MCA, Cray T3D SC, Cray T3E, Cray T90, Cray T916, Cray T932, Cray UNICOS, Cray X1, Cray X1E, Cray XD1, Cray X-MP, Cray XMS, Cray XT3, Cray XT4, Cray Y-MP EL, Cray-1, Cray-2, Cray-3, CrayDoc, CrayLink, Cray-MP, CrayPacs, Cray/REELlibrarian, CraySoft, CrayTutor, CRInform, CRI/TurboKiva, CSIM, CVT, Delivering the power..., Dgauss, Docview, EMDS, Gigaring, HEXAR, HSX, IOS, ISP/Superlink, Libsci, MPP Apprentice, ND Series Network Disk Array, Network Queuing Environment, Network Queuing Tools, OLNET, RapidArray, RQS, SEGLDR, SMARTE, SSD, SUPERLINK, System Maintenance and Remote Testing Environment, Trusted UNICOS, TurboKiva, UNICOS MAX, UNICOS/lc, and UNICOS/mp are trademarks of Cray Inc. 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New Features Cray XD1™ FPGA Development S–6400–14 This manual contains the following changes from the previous version: • Incorporates chapters on developing software applications, including the API details. These were moved (and restructured) from Cray XD1 Programming (S–2433) to this manual. • Some existing chapters are restructured and renamed. • Describes the interrupts feature, including how the FPGA generates an interrupt and how the application program enables interrupt processing: the new fpga_int_wait(3) function. • Documents the clock frequency requirement for all designs. • Describes the new command-line utilities for reading and writing values in the FPGA: fpga_read(1) and fpga_write(1). Record of Revision Version Description 1.4 May 2006 Supports Cray XD1 release 1.4. 1.3.1 October 2005 Supports Cray XD1 release 1.3.1 (1.3 general availability). 1.3 July 2005 Supports Cray XD1 release 1.3 (limited availability). 1.2 April 2005 Supports Cray XD1 releases 1.2 and 1.2.1. 1.1 October 2004 Supports Cray XD1 releases 1.1. 1.0 August 2004 Supports Cray XD1 releases 1.0. S–6400–14 Cray Private i Contents Page Preface xiii Accessing Product Documentation . xiii Conventions . xiv Reader Comments . xv Cray User Group . xv Cray XD1 Support . xvi Part I: Introduction Introduction [1] 3 About This Manual . 3 Who Should Read this Manual . 3 Scope of this Manual . 3 How this Manual is Organized . 3 Related Publications . 4 Cray XD1 Publications . 4 Third-party Publications . 5 About FPGA Development . 6 What is an FPGA AAP? . 6 Advantages and Disadvantages of FPGAs . 6 Target Applications . 8 Characteristics of Target Applications . 8 Sample Application . 9 The Development Process . 10 S–6400–14 Cray Private iii Cray XD1™ FPGA Development Page Part II: The Cray XD1 System Cray XD1 Architecture [2] 15 Cray XD1 High-level Physical Layout . 15 Chassis . 15 Compute Blade . 17 Expansion Module . 18 RapidArray Interconnect . 19 Expansion Module [3] 21 Expansion Module Variants . 21 FPGA AAP . 21 Configurable Logic Blocks . 22 Block SelectRAM+ Memory Modules . 22 Embedded Multiplier Blocks . 22 XtremeDSP Slices . 22 Digital Clock Manager Blocks . 23 Embedded IBM PowerPC 405 RISC Processor Blocks . 23 Programmability . 23 Comparison of Xilinx FPGAs . 23 RapidArray Processor . 24 QDR II SRAM . 24 Programmable Clock . 24 Communication Paths . 24 Part III: Developing FPGA Logic Quick Start [4] 29 Reference Design Overview . 29 Command-line Manipulation of FPGAs . 30 Overview . 30 Copying the Design Directory . 30 iv Cray Private S–6400–14 Contents Page Converting FPGA Binary Files . 31 Downloading Files to the FPGA . 32 Accessing the FPGA . 32 Erasing the FPGA . 34 Running the C Reference Programs . 34 Hardware Development Flows [5] 37 Basic HDL Development Flow . 37 Overview of the HDL Development Process . 37 Design Entry . 38 Synthesis . 39 Simulation . 39 Implementation . 40 Development Flow Using Software-Oriented Languages . 40 Design Entry . 41 Synthesis . 42 Simulation . 42 Implementation . 42 Third-Party Vendors and Tools . 42 Celoxica, Inc. 43 DSPlogic, Inc. 43 Impulse Accelerated Technologies, Inc. 43 Mitrionics Inc. 43 General Design Considerations [6] 45 Clock Frequency . 45 FPGA Memory Resources . 45 Fabric Bandwidth and Data Flow . 47 SMP Processor-initiated Fabric Transactions . 48 FPGA-initiated Fabric Transactions . 48 Limitations . 48 S–6400–14 Cray Private v Cray XD1™ FPGA Development Page Using the Design Template [7] 49 Overview . 49 Contents of the Design Template . 52 Design Files . 52 Directory Structure . 53 Working with the Design Template . 56 Copying the Design Template . 56 Procedure 1: To copy the design template . 56 Tools . 56 Required Customizations . 57 Command Line Execution and Makefile Targets . 58 Example 1: Using makefile targets . 59 Using the Xilinx ISE GUI . 59 Simulating the Design . 60 Interfaces [8] 63 RapidArray Transport Interface . 63 QDR II SRAM Interface . 65 Interfacing User Logic to Other Cray XD1 Resources . 67 Interfacing Considerations . 67 Disabling Unused Core Interfaces . 68 Interaction with the SMP Software Application . 68 Memory Map . 69 SMP-initiated RT Requests . 70 I/O Mapped Accesses . 71 Example 2: I/O mapped writes to the AAP . 71 API Function Accesses . 72 Example 3: Accessing the AAP with fpga_wrt_appif_val ....... 72 FPGA-initiated RT Requests . 73 Example 4: Initializing the AAP to access the SMP memory . 74 FPGA-initiated Interrupt Requests . 74 vi Cray Private S–6400–14 Contents Page Example 5: Generating an interrupt request (VHDL notation) . 74 Simulation and Debugging [9] 77 Simulation Models . 77 Cray XD1 Core Simulation Models . 77 RapidArray Fabric Behavioral Model . 77 Fabric Model Inputs . 77 Example 6: Format of the fabric.in file.............. 79 FPGA Transfer Region . 80 Using the JTAG Interface Card . 81 The JTAG Interface Card . 81 Mapping JTAG Interface Ports to FPGAs . 81 Viewing JTAG Interface Port Connections . 82 Connecting a JTAG Interface Port to an FPGA . 83 Example 7: Connecting a JTAG interface port to an FPGA . 83 Restoring the Default JTAG Interface Port Connections . 83 Connecting a Workstation to a JTAG Interface Port . 83 Reading and Writing Data Values . 85 Reading Data from the FPGA . 86 Example 8: Using the fpga_read command . 86 Writing Data.

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