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Der Cell Prozessor Der Cell Prozessor Seminarvortrag von Viacheslav Mlotok SS2005 Universität Mannheim, Lehrstuhl für Rechnerarchitektur 1 Inhalt • Entwicklungsziele • Cell Architektur – Power Processor Element – Synergistic Processor Element – Memory Interface Controller – Bus Interface Controller – Element Interconnect Bus • Software Cells • Anwendungs- und Produktbeispiele • Fazit • Quellenangaben 2 Entwicklungsziele Quelle: [9] • Hauptziel: neue Architektur für die Storage effiziente Verarbeitung von Logic Multimedia- und Grafikdaten der Cache nächsten Generation • Aufbau eines modernen RISC Control Logic Prozessors IF ID – großer Cache Dispatch – out-of-order execution, speculative execution, hardware branch prediction, predication, etc. – superscalare Architektur, tiefe Pipelines Issue Logic • 40% Performancezuwachs bei Execution Verdoppelung der Anzahl von Logic Vector FP Units Unit Integer Units LS Unit Transistoren Execution Core Reorder Commit Commit Unit 3 Entwicklungsziele • Performance pro Transistor als Quelle: [9] Maß Storage Logic • Mikroarchitektur vereinfachen und Komplexität auf die Software Local Storage verlagern • Control Logic kein Cache - nur ein schneller IF lokaler Speicher ID • großes allgemeines Registerfile, Dispatch data fetch und branch prediction Execution Logic in Software • Multicore anstatt tiefen Pipelines Vector Arithmetic Units Permute LS Channel Branch Unit Unit Unit Unit Execution Core Commit Commit Unit 4 Cell Architektur Quelle: [8] • gemeinsame Entwicklung von IBM, Sony und Toshiba • 90nm SOI, 8 Metalllagen • 234 Mio. Transistoren 2 • 221mm Die-Größe 5 Cell Architektur Quelle: [1] • SoC-Design • besteht aus – PowerPC Core mit L2 Cache – 8 SIMD Prozessoren – Memory und I/O Interfaces – Testeinheit für testing, monitoring und debugging • 9 Prozessorkerne, 10-way Multithreading Quelle: [1] • high performance distributed, parallel computing • Virtualization technology • modularer Aufbau • universeller Einsatz: vom PDA bis zum Server 6 Cell Architektur • 4 GHz @ 1.1 Volt, 50-80 Watt Verlustleistung • 4.6 GHz @ 1.3 Volt • Zukunft: 5.6 GHz @ 1.4 Volt, 180 Watt Verlustleistung • 256 GFlops @ 4 GHz (single precision, nicht IEEE kompatibel) • 26 GFlops @ 4 GHz (double precision, IEEE kompatibel) Quelle: [2] 7 Power Processor Element (PPE) • modifizierter 64bit PowerPC mit VMX-Erweiterung (Vector Multimedia Extension) • in-order execution, dual-issue • 2-way Multithreading, round-robin scheduling • 32 KB L1 Instruktions- und Datencache, 512 KB L2 Cache • Hostprozessor für die SIMD Prozessoren, führt allgemeine Aufgaben aus Quelle: [1] 8 Synergistic Processor Element (SPE) • 128bit unabhängige SIMD-Einheit, single-precision optimiert • in-order execution, dual-issue • 21 Mio. Transistoren • 2.5 x 5.81 mm • von PPE verwaltet, programmierbar in Hochsprachen (z.B. C, C++) Quelle: [1] 9 Synergistic Processor Element (SPE) Quelle: [3] • Instruktionsformat: 32bit fixed-length, 3 Operanden, 1 Ergebnis • 128bit Operanden (4 x 32bit) • dreistufiges Memorymodell – Hauptspeicher, lokaler Speicher, Register – Speicherzugriffe mit DMA (kohärent auf den Hauptspeicher) • Stream Processing (Chaining) möglich – SPEs von anderen Cells können dabei benutzt werden, falls eine längere Kette gebraucht wird • 4 Operationen/Takt => 256 GFlops für 8 SPEs @ 4 GHz (8SPEs x 4GHz x 2 FPUs x 4 Operationen) • data fetch und branch prediction in Software – 18 Takte branch misprediction penalty 10 Synergistic Processor Element (SPE) Quelle: [3] • 256 KB Local Store (LS) • 128 x 128bit Registerfile mit 6 read ports und 2 write ports, 2 Takte Zugriffslatenz • DMA-Einheit (Speicherzugriffe) • MMU • BIU - Bus Interface Unit (zur Anbindung an den gemeinsamen Bus) • RTB - Testblock mit ABIST (Array Build In Self Test) • ATO - Atomic Memory Unit (Kohärenz) 11 Synergistic Processor Element (SPE) Local Store (LS) Quelle: [3] • array of single ported, pipelined SRAMs • 256 KB groß (4 x 64 KB) • L1 Cache-Ersatz für Instruktionen und Daten • nicht kohärent, nur lokale Zugriffe • Leselatenz = 6 Takte, Schreiblatenz = 4 Takte • quadword (16 Byte) oder line (128 Byte) Zugriffe • drei Prioritätsstufen – DMA – Load und store – Instruction fetch • 16 Byte/Takt L/S Bandbreite • 128 Byte/Takt DMA Bandbreite 12 Synergistic Processor Element (SPE) DMA Einheit Quelle: [3] • steuert den Datenverkehr • lokale und externe requests • Adressübersetzung durch MMU • bis zu 16 outstanding requests werden unterstützt • 16 KB pro request • programmiert durch channel interface – message passing interface – bis zu 128 unidirektionale Kanäle (blocking oder nonblocking) – read channel, write channel und read channel count 13 Synergistic Processor Element (SPE) Quelle: [3] • zwei Pipelines, „even“ und „odd“ • 6 Ausführungseinheiten Quelle: [3] 14 Synergistic Processor Element (SPE) Pipelinetiefe, Latenzen Quelle: [3] Execution Pipeline Instruction Unit Instructions Pipe Depth Latency Simple Fixed Word arithmetic, logicals, counting Even 2 2 leading zeros, selects and compares Simple Fixed Word shifts and rotates Even 3 4 Single Precision Multiply-accumulate Even 6 6 Single Precision Integer multiply-accumulate Even 7 7 Pop count, absolute sum of differences, byte Byte Odd 3 4 average, byte sum Quadworld shifts, rotates, gathers, Permute shuffles as well as reciprocal estimates Odd 3 4 Load Store Load and store Odd 6 6 Channel Channel read/write Odd 5 6 Branch Branches Odd 3 4 15 Memory Interface Controller (MIC) • Unterstüzung von 3.2 GHz XDR DRAM Memory von Rambus (lizensiert von Sony und Toshiba) • XIO Interface - ultra high-speed parallel interface between multiple chips • 25.6 GB/s memory bandwidth (dual channel) • maximal 4.5 GB adressierbar (72 DRAM Devices @ 512Mb) Quelle: [1] 16 XDR Memory System • 1024bit Blockzugriff • unterteilt in „sandboxes“ – Statusbits bestimmen, welche SPEs darauf zugreifen darf (memory protection) Quelle: [11] • command and address bus – unidirektional, 12bit breit, 800 Mb/s – bis zu 36 DRAM Devices • Datenbus – 36 bidirektionale point-to-point Verbindungen (3.2 Gb/s) – konfigurierbar nach Anzahl der Devices – 3.2 GHz (8 x 400 MHz) - octal data rate (ODR) – maximale Bandbreite 12.8 GB/s (2 Devices, 16bit, 1 channel) 17 Bus Interface Controller • Kommunikation mit dem Rest des Systems • FlexIO Interface (entwickelt von Rambus) • kohärentes Interface für SMP (Symmetrical Multi Processing), nicht kohärentes Interface für I/O • 44.8 GB/s outbound bandwidth, 32 GB/s inbound bandwidth • zusammen 76.8 GB/s I/O Bandbreite Quelle: [1] 18 Bus Interface Controller • 12 byte lanes • Byte lane - 8bit breite, unidirektionale, point-to-point Verbindung • 6.4 GB/s pro byte lane • asymmetrische Konfiguration – 7 byte lanes outbound, 5 byte lanes inbound – Bildung von kohärenten und nicht kohärenten Gruppen Quelle: [1] 19 Element Interconnect Bus (EIB) • verbindet alle Einheiten des Cells miteinander • kohärent • Datenstruktur – 4 unidirektionale 128bit Ringe – 96 Byte/Takt, bis zu 128 outstanding requests • Kontrollstruktur Quelle: [1] – ein Bus • läuft mit halber Cell-Taktfrequenz 20 Software Cells • Apulet - Bündel aus einem Datenobjekt und erforderlichem Programmcode • vom PPE initialisiert und direkt von SPEs ausgeführt • systemunabhängig • können über das Netzwerk verschickt werden Quelle: [4] 21 Beispiel - Digital TV Receiver • erforderliche Schritte (MPEG 2) – COFDM demodulation – MPEG audio and video decode – Error correction – Video scaling – Demultiplexing – Display construction – Descrambling – Contrast and brightness processing COFDM Error Demuliplexing Audio & Video Display Contrast & Demodulation Correction & Descrambling Video Decode Scaling Construction Brightness Processing Quelle: [10] 22 Flexibilität Quelle: [1] • direkte Verbindung zweier Cells durch FlexIO, indirekt über einen Switch • unterschiedliche Systemkonfigurationen – Spielekonsolen, HDTVs – Home entertaiment Anlagen – Workstations, Supercomputers Quelle: [1] Quelle: [1] 23 Cell Processor Based Workstation (CPBW) • Cell Based Blade Server Board Prototype – 2 Cells, 512MB XDR DRAM, 2 South Bridges Quelle: [6] – 2.4-2.8 GHz (3 GHz im Labor) – 200 GFlops @ 3 GHz (400 GFlops pro Board) – 7 Boards pro Rack – 23 x 43 cm – Linux 2.6.11 Quelle: [6] 24 Playstation 3 • 1 Cell mit 7 SPEs @ 3.2 GHz, 256 MB XDR DRAM • Grafikchip von NVidia @ 550 MHz, 256 GDDR3 DRAM • 3 Ethernet-Ports, 802.11b/g WLAN, Bluetooth 2.0, optionale Festplatte • Verfügbarkeit: Frühling 2006, Preis: 300-400 Euro Quelle: [7] Quelle: [7] 25 Fazit • ungewöhnliche Architektur, die sich von der Architektur aktueller Prozessoren unterscheidet • vereinfachtes Design, teilweise ohne klassische Ansätze der Rechnerarchitektur • hohe Performance durch massive Parallelisierung der Aufgaben • neues Programmiermodell notwendig, um SPEs effizient nutzen zu können • SPEs werden schwierig zu programmieren sein • primärer Einsatz im Bereich des Multimedia (single precision) • offene Frage: Verwendung in Supercomputern (double precision) und in Desktop-PCs (Konkurrenz zu x86) 26 Quellenangaben • [1]: H. Peter Hofstee, Ph. D., „Power Efficient Processor Design and the Cell Processor“ http://www.hpcaconf.org/hpca11/slides/Cell_Public_Hofstee.pdf http://www.hpcaconf.org/hpca11/papers/25_hofstee-cellprocessor_final.pdf • [2]: D. Pham et. al. „The Design and Implementation of a First-Generation CELL Processor“, International Solid-State Circuits Conference Technical Digest, Feb. 2005 http://www-306.ibm.com/chips/techlib/techlib.nsf/products/Cell • [3]: B. Flachs et. al. „A Streaming Processing Unit for a CELL Processor“, International Solid-State
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