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Programming Environment, Run-Time System and Simulator for Many-Core Machines Olivier Certner

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Programming Environment, Run-Time System and Simulator for Many-Core Machines Olivier Certner Programming Environment, Run-Time System and Simulator for Many-Core Machines Olivier Certner To cite this version: Olivier Certner. Programming Environment, Run-Time System and Simulator for Many-Core Ma- chines. Distributed, Parallel, and Cluster Computing [cs.DC]. Université Paris Sud - Paris XI, 2010. English. tel-00826616 HAL Id: tel-00826616 https://tel.archives-ouvertes.fr/tel-00826616 Submitted on 27 May 2013 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. UNIVERSITÉ de PARIS-SUD U.F.R. SCIENTIFIQUE d’ORSAY THÈSE présentée pour obtenir le grade de DOCTEUR en SCIENCES de l’UNIVERSITÉ de PARIS XI ORSAY Spécialité : Informatique par Olivier CERTNER Sujet : Environnement de programmation, support à l’exécution et simulateur pour machines à grand nombre de cœurs Programming Environment, Run-Time System and Simulator for Many-Core Machines Soutenue le 15 décembre 2010 devant le jury composé de : M. Lieven Eeckhout Rapporteur M. François Bodin Rapporteur M. Pascal Sainrat Examinateur M. Jean-José Bérenguer Examinateur M. Bruno Jégo Examinateur M. Olivier Temam Directeur © 2010–2011, 2013 Olivier Certner Tous droits réservés pour tous pays. Imprimé en France. All rights reserved. Printed in France. Revisions of this document: 0.1 This is the first version released to the jury. It missed the content of the “Distributed Work Management” chapter, the “General Conclusion”, some appendices and a summary of the thesis in French. 0.2 The contents of the “Distributed Work Management” (Chapter9) and of the “General Conclusion” are now released. An appendix containing some example Capsule code has been added. 1.0 This is the version that was released to the jury on the defense day. It includes minor modifications. Most of the suggestions by some members of the jury are among them. 1.1 Added dedications and acknowledgements. 1.2 Added an appendix (some example code for the Capsule distributed-memory run-time system). Added an index. Reworked some figures. Minor corrections throughout the manuscript. À mes grands-parents À mes professeurs Résumé L’accroissement régulier de la fréquence des micro-processeurs et des importants gains de puissance qui en avaient résulté ont pris fin en 2005. Les autres principales techniques matérielles d’amélioration de performance pour les programmes séquentiels (exécution dans le désordre, antémémoires, prédiction de branchement, etc.) se sont largement essouflées. Conduisant à une consommation de puissance toujours plus élevée, elles posent de délicats problèmes économiques et techniques (refroidissement des puces). Pour ces raisons, les fabricants de micro-processeurs ont choisi d’exploiter le nombre croissant de transistors disponibles en plaçant plusieurs cœurs de processeurs sur une même puce. Par cette thèse, nous avons pour objectif et ambition de préparer l’arrivée probable, dans les prochaines années, de processeurs multi-cœur à grand nombre de cœurs (une centaine ou plus). À cette fin, nos recherches se sont orientées dans trois grandes di- rections. Premièrement, nous améliorons l’environnement de parallélisation Capsule, dont le principe est la parallélisation conditionnelle, en lui adjoignant des primitives de synchronization de tâches robustes et en améliorant sa portabilité. Nous étudions ses performances et montrons ses gains par rapport aux approches usuelles, aussi bien en terme de rapidité que de stabilité du temps d’exécution. Deuxièmement, la compétition entre de nombreux cœurs pour accéder à des mémoires aux performances bien plus faibles va vraisemblablement conduire à répartir la mémoire au sein des futures architectures multi-cœur. Nous adaptons donc Capsule à cette évolution en présentant un modèle de données simple et général qui permet au système de déplacer automatiquement les données en fonction des accès effectués par les programmes. De nouveaux algorithmes répartis et locaux sont également proposés pour décider de la création effective des tâches et de leur répartition. Troisièmement, nous développons un nouveau simulateur d’évènements discrets, Si- Many, pouvant prendre en charge des centaines à des milliers de cœurs. Nous montrons qu’il reproduit fidèlement les variations de temps d’exécution de programmes observées sur un simulateur de niveau cycle jusqu’à 64 cœurs. SiMany est au moins 100 fois plus rapide que les meilleurs simulateurs flexibles actuels. Il permet l’exploration d’un champ plus large d’architectures ainsi que l’étude des grandes lignes du comportement des logiciels sur celles-ci, ce qui en fait un outil majeur pour le choix et l’organisation des futures architectures multi-cœur et des solutions logicielles qui les exploiteront. Abstract Since 2005, chip manufacturers have stopped raising processor frequencies, which had been the primary mean to increase processing power since the end of the 90s. Other hardware techniques to improve sequential execution time (out-of-order processing, caches, branch prediction, etc.) have also shown diminishing returns, while raising the power envelope. For these reasons, commonly referred to as the frequency and power walls, manufacturers have turned to multiple processor cores to exploit the growing number of available transistors on a die. In this thesis, we anticipate the probable evolution of multi-core processors into many-core ones, comprising hundreds of cores and more, by focusing on three important directions. First, we improve the Capsule programming environment, based on condi- tional parallelization, by adding robust coarse-grain synchronization primitives and by enhancing its portability. We study its performance and show its benefits over common parallelization approaches, both in terms of speedups and execution time stability. Second, because of increased contention and the memory wall, many-core architectures are likely to become more distributed. We thus adapt Capsule to distributed-memory architectures by proposing a simple but general data structure model that allows the associated run-time system to automatically handle data location based on program accesses. New distributed and local schemes to implement conditional parallelization and work dispatching are also proposed. Third, we develop a new discrete-event-based simulator, SiMany, able to sustain hundreds to thousands of cores with practical execution time. We show that it success- fully captures the main program execution trends by comparing its results to those of a cycle-accurate simulator up to 64 cores. SiMany is more than a hundred times faster than the current best flexible approaches. It pushes further the limits of high-level architectural design-space exploration and software trend prediction, making it a key tool to design future many-core architectures and to assess software scalability on them. ix Contents Remerciements xv Introduction1 I Capsule: Parallel Programming Made Easier7 1 Parallel Programming Is Hard9 1.1 Work Splitting and Dispatching . 10 1.2 Working on the Same Data at the Same Time . 10 1.2.1 Atomic Operations and Mutual Exclusion Primitives . 11 1.2.2 Transactional Memory . 11 1.3 Task Dependencies . 12 1.4 The Capsule Environment . 13 2 The Capsule Programming Model 15 2.1 Tasks . 16 2.2 Conditional Parallelization . 17 2.3 Recursive Work Declaration . 19 2.4 Coarse-Grain Task Synchronization . 22 2.5 Other Primitives and Abstractions . 27 3 Run-Time System Implementation 29 3.1 Task Abstraction and Scheduling . 30 3.2 Conditional Parallelization . 32 3.3 Synchronization Groups . 35 3.4 Portability Abstractions . 37 x CONTENTS 4 Performance Study 41 4.1 Performance Scalability and Stability . 41 4.1.1 Motivating Example . 43 4.1.2 Benchmarks and Experimental Framework . 46 4.1.3 Iterative Execution Sampling . 48 4.1.4 Experimental Results . 50 4.2 Performance Dependence on the Run-Time Platform . 54 4.2.1 Run-Time System Implementation . 54 4.2.2 Hardware Architecture . 56 4.2.3 Task Granularity and Other Program Characteristics . 58 5 Related Work 63 5.1 Data Parallel Environments . 63 5.1.1 Languages . 63 5.1.2 STAPL . 64 5.2 Asynchronous Function Calls . 65 5.2.1 Cool . 65 5.2.2 Cilk . 66 5.2.3 Thread Building Blocks . 68 5.3 Parallel Semantics Through Shared-Objects . 69 5.3.1 Orca . 69 5.3.2 Charm++ . 70 6 Conclusion and Future Work 73 II Distributed Architecture Support in Capsule 75 7 Towards Distributed Architectures 77 8 Distributed Data Structures 81 8.1 Data Structure Model . 84 8.1.1 Concepts . 85 8.1.2 Programming Interface . 87 8.2 Implementation Traits . 90 8.2.1 Object Management Policy . 91 8.2.2 Object References . 92 8.2.3 Cell Structuration . 96 CONTENTS xi 8.2.4 Hardware Support . 98 8.3 Status and Future Directions . 100 9 Distributed Work Management 103 9.1 Probe Policy and Task Queues . 104 9.2 Design Considerations . 106 9.2.1 Classical Strategies . 106 9.2.2 Push or Pull? . 108 9.3 Load-Balancing Policy . 108 9.3.1 Migration Decision Algorithm . 109 9.3.2 From Local Decisions to Global Balance . 111 9.4 Migration Protocol and Interactions With Task Queues . 113 9.4.1 Concurrent Task Migrations . 113 9.4.2 Preserving Locality . 115 10 Related Work 117 10.1 SPMD and Task-Based Languages . 117 10.1.1 SPMD Languages . 117 10.1.2 Cilk . 119 10.2 Memory Consistency . 120 10.2.1 Sequential Consistency . 120 10.2.2 Strong Ordering . 122 10.2.3 Practical Sufficient Conditions for Sequential Consistency . 124 10.2.4 Weak Ordering . 125 10.2.5 Processor Consistency . 127 10.2.6 Slow and Causal Memories . 128 10.2.7 Release Consistency .
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