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Linpack Evaluation on a Supercomputer with Heterogeneous Accelerators
Linpack Evaluation on a Supercomputer with Heterogeneous Accelerators Toshio Endo Akira Nukada Graduate School of Information Science and Engineering Global Scientific Information and Computing Center Tokyo Institute of Technology Tokyo Institute of Technology Tokyo, Japan Tokyo, Japan [email protected] [email protected] Satoshi Matsuoka Naoya Maruyama Global Scientific Information and Computing Center Global Scientific Information and Computing Center Tokyo Institute of Technology/National Institute of Informatics Tokyo Institute of Technology Tokyo, Japan Tokyo, Japan [email protected] [email protected] Abstract—We report Linpack benchmark results on the Roadrunner or other systems described above, it includes TSUBAME supercomputer, a large scale heterogeneous system two types of accelerators. This is due to incremental upgrade equipped with NVIDIA Tesla GPUs and ClearSpeed SIMD of the system, which has been the case in commodity CPU accelerators. With all of 10,480 Opteron cores, 640 Xeon cores, 648 ClearSpeed accelerators and 624 NVIDIA Tesla GPUs, clusters; they may have processors with different speeds as we have achieved 87.01TFlops, which is the third record as a result of incremental upgrade. In this paper, we present a heterogeneous system in the world. This paper describes a Linpack implementation and evaluation results on TSUB- careful tuning and load balancing method required to achieve AME with 10,480 Opteron cores, 624 Tesla GPUs and 648 this performance. On the other hand, since the peak speed is ClearSpeed accelerators. In the evaluation, we also used a 163 TFlops, the efficiency is 53%, which is lower than other systems. -
Quietrock Case Study | Sony Computer Entertainment America
Studios & Entertainment Quiet® Success Story Project: ® Sony Computer Entertainment ‘Sh-h-h-h!’ PlayStation 4 game- America, LLC making in progress! Location: San Mateo, California New sound studios spearhead renovations for Sony Computer General Contractor: Entertainment America, with an acoustical assist from Magnum Drywall Magnum Drywall and PABCO® Gypsum’s QuietRock® Products: QuietRock® FLAME CURB® San Mateo, California The Sound of Silence means a lot to engineers producing video games for Sony PlayStation®4 (PS4™) enthusiasts. At Sony Computer Entertainment America LLC headquarters in San Mateo, California, producers’ tolerance for intrusive noise from beyond studio walls is zero. Only the intense action on-screen matters while creating audio effects that dramatize, punctuate and heighten the deeply immersive experience for video gamers. In these studios Sony Entertainment sound engineers make the most of that capability while keeping the PlayStation® pipeline full for weekly launches of new games. The gaming experience draws players to PS4™ and its predecessor PlayStation® consoles, and PS4™ elevates 3D excitement ever higher. It’s the world’s most powerful games console, with a Graphics Processing Unit (GPU) able to perform 1,843 teraflops*. “When sound is important, we prefer to submit QuietRock as a good solution for the architect and the owner. There’s nothing else on the market that’s comparable. I even used it in my own home movie theatre.”” – Gary Robinson, Owner Magnum Drywall what the job demands Visit www.QuietRock.com or call Call 1.800.797.8159 for more information On top of its introductory lineup in November 2013, over 180 PS4™ games are in development, including “Be the Batman”, the epic conclusion of the “Batman: Arkham Knight” trilogy, that is due out in June 2015. -
List of Notable Handheld Game Consoles (Source
List of notable handheld game consoles (source: http://en.wikipedia.org/wiki/Handheld_game_console#List_of_notable_handheld_game_consoles) * Milton Bradley Microvision (1979) * Epoch Game Pocket Computer - (1984) - Japanese only; not a success * Nintendo Game Boy (1989) - First internationally successful handheld game console * Atari Lynx (1989) - First backlit/color screen, first hardware capable of accelerated 3d drawing * NEC TurboExpress (1990, Japan; 1991, North America) - Played huCard (TurboGrafx-16/PC Engine) games, first console/handheld intercompatibility * Sega Game Gear (1991) - Architecturally similar to Sega Master System, notable accessory firsts include a TV tuner * Watara Supervision (1992) - first handheld with TV-OUT support; although the Super Game Boy was only a compatibility layer for the preceding game boy. * Sega Mega Jet (1992) - no screen, made for Japan Air Lines (first handheld without a screen) * Mega Duck/Cougar Boy (1993) - 4 level grayscale 2,7" LCD - Stereo sound - rare, sold in Europe and Brazil * Nintendo Virtual Boy (1994) - Monochromatic (red only) 3D goggle set, only semi-portable; first 3D portable * Sega Nomad (1995) - Played normal Sega Genesis cartridges, albeit at lower resolution * Neo Geo Pocket (1996) - Unrelated to Neo Geo consoles or arcade systems save for name * Game Boy Pocket (1996) - Slimmer redesign of Game Boy * Game Boy Pocket Light (1997) - Japanese only backlit version of the Game Boy Pocket * Tiger game.com (1997) - First touch screen, first Internet support (with use of sold-separately -
14789093.Pdf
iNIS-mf—8658 THE INFLUENCE OF COLLISIONS WITH NOBLE GASES ON SPECTRAL LINES OF HYDROGEN ISOTOPES PROEFSCHRIFT TER VERKRIJGING VAN DE GRAAD VAN DOCTOR IN DE WISKUNDE EN NATUURWETENSCHAPPEN AAN DE RIJKSUNIVERSITEIT TE LEIDEN, OP GEZAG VAN DE RECTOR MAGNIFICUS DR. A.A.H. KASSENAAR, HOOGLERAAR IN DE FACULTEIT DER GENEESKUNDE, VOLGENS BESLUIT VAN HET COLLEGE VAN DEKANEN TE VERDEDIGEN OP WOENSDAG 10 NOVEMBER 1982 TE KLOKKE 14.15 UUR DOOR PETER WILLEM HERMANS GEBOREN TE ROTTERDAM IN 1952 1982 DRUKKERIJ J.H. PASMANS B.V., 's-GRAVENHAGE Promotor: Prof. dr. J.J.M. Beenakker Het onderzoek is uitgevoerd mede onder verantwoordelijkheid van wijlen prof. dr. H.F.P. Knaap Aan mijn oudeva Het 1n dit proefschrift beschreven onderzoek werd uitgevoerd als onderdeel van het programma van de werkgemeenschap voor Molecuul fysica van de Stichting voor Fundamenteel Onderzoek der Materie (FOM) en is mogelijk gemaakt door financiële steun van de Nederlandse Organisatie voor Zuiver- WetenschappeHjk Onderzoek (ZWO). CONTENTS PREFACE 9 CHAPTER I THEORY OF THE COLLISIONAL BROADENING AND SHIFT OF SPECTRAL LINES OF HYDROGEN INFINITELY DILUTED IN NOBLE GASES 11 1. Introduction 11 2. General theory 12 a. Rotational Raman 15 b. Depolarized Rayleigh 16 3. Experimental preview 16 a. Rotational Raman lines; broadening and shift 17 b. Depolarized Rayleigh line 17 CHAPTER II EXPERIMENTAL DETERMINATION OF LINE BROADENING AND SHIFT CROSS SECTIONS OF HYDROGEN-NOBLE GAS MIXTURES 21 1. Introduction 21 2. Experimental setup 22 2.1 Laser 22 2.2 Scattering cell 24 2.3 Analyzing system 27 2.4 Detection system 28 3. Measuring technique 28 3.1 Width measurement 28 3.2 Shift measurement 32 3.3 Gases 32 4. -
POWER® Processor-Based Systems
IBM® Power® Systems RAS Introduction to IBM® Power® Reliability, Availability, and Serviceability for POWER9® processor-based systems using IBM PowerVM™ With Updates covering the latest 4+ Socket Power10 processor-based systems IBM Systems Group Daniel Henderson, Irving Baysah Trademarks, Copyrights, Notices and Acknowledgements Trademarks IBM, the IBM logo, and ibm.com are trademarks or registered trademarks of International Business Machines Corporation in the United States, other countries, or both. These and other IBM trademarked terms are marked on their first occurrence in this information with the appropriate symbol (® or ™), indicating US registered or common law trademarks owned by IBM at the time this information was published. Such trademarks may also be registered or common law trademarks in other countries. A current list of IBM trademarks is available on the Web at http://www.ibm.com/legal/copytrade.shtml The following terms are trademarks of the International Business Machines Corporation in the United States, other countries, or both: Active AIX® POWER® POWER Power Power Systems Memory™ Hypervisor™ Systems™ Software™ Power® POWER POWER7 POWER8™ POWER® PowerLinux™ 7® +™ POWER® PowerHA® POWER6 ® PowerVM System System PowerVC™ POWER Power Architecture™ ® x® z® Hypervisor™ Additional Trademarks may be identified in the body of this document. Other company, product, or service names may be trademarks or service marks of others. Notices The last page of this document contains copyright information, important notices, and other information. Acknowledgements While this whitepaper has two principal authors/editors it is the culmination of the work of a number of different subject matter experts within IBM who contributed ideas, detailed technical information, and the occasional photograph and section of description. -
Zoned Storage for HDD and SSD Technologies
Zoned Storage Now Encompasses Both HDD & SSD Technologies WHITE PAPER 3 Western Digital | WHITE PAPER WHITE PAPER Zoned Storage Now Encompasses Both HDD & SSD Technologies Both HDDs and SSDs have their own on-device controllers that are used to provide low-level manipulation of the drives. The division of compute tasks performed by the host-side CPUs and the drive-side controllers has evolved over time, with the boundaries moving back and forth between them. Computational architectures have evolved, especially in data centers where — as systems started to scale — local optimizations performed by the devices began to impact global optimizations. The concept of Zoned Storage is a relatively recent development that refers to a class of storage devices — both HDDs and SSDs — that enable the host system and the storage devices to cooperate so as to achieve higher storage capacities. As its name suggests, Zoned Storage involves organizing or partitioning the drives into zones. In the case of HDDs, Zoned Storage is implemented using a technology known as shingled magnetic recording (SMR). In the case of SSDs, Zoned Storage is implemented using a technology known as Zoned Namespaces (ZNS). Data Taken As-Is Serialize Data Zoned Storage Zoned Storage 2 HDDs An HDD contains one or more rigid rapidly rotating platters coated with a magnetic material. Electromagnetic read/write heads are positioned above and below each platter. Data is stored on the platter as a series of thin concentric rings called tracks. In turn, the tracks are sub-divided into sectors. The HDD also contains a hard disk controller (HDC), which may be thought of as a small processor that is used to provide low-level control of the drive. -
Storage Solutions for Embedded Applications
White Paper Storage Solutions Brian Skerry Sr. Software Architect Intel Corporation for Embedded Applications December 2008 1 321054 Storage Solutions for Embedded Applications Executive Summary Any embedded system needs reliable access to storage. This may be provided by a hard disk drive or access to a remote storage device. Alternatively there are many flash solutions available on the market today. When considering flash, there are a number of important criteria to consider with capacity, cost, and reliability being foremost. This paper considers hardware, software, and other considerations in choosing a storage solution. Wear leveling is an important factor affecting the expected lifetime of any flash solution, and it can be implemented in a number of ways. Depending on the choices made, software changes may be necessary. Solid state drives offer the most straight forward replacement option for Hard disk drives, but may not be cost-effective for some applications. The Intel® X-25M Mainstream SATA Solid State Drive is one solution suitable for a high performance environment. For smaller storage requirements, CompactFlash* and USB flash are very attractive. Downward pressure continues to be applied to flash solutions, and there are a number of new technologies on the horizon. As a result of reading this paper, the reader will be able to take into consideration all the relevant factors in choosing a storage solution for an embedded system. Intel® architecture can benefit the embedded system designer as they can be assured of widespread -
Introduction to the Cell Multiprocessor
Introduction J. A. Kahle M. N. Day to the Cell H. P. Hofstee C. R. Johns multiprocessor T. R. Maeurer D. Shippy This paper provides an introductory overview of the Cell multiprocessor. Cell represents a revolutionary extension of conventional microprocessor architecture and organization. The paper discusses the history of the project, the program objectives and challenges, the design concept, the architecture and programming models, and the implementation. Introduction: History of the project processors in order to provide the required Initial discussion on the collaborative effort to develop computational density and power efficiency. After Cell began with support from CEOs from the Sony several months of architectural discussion and contract and IBM companies: Sony as a content provider and negotiations, the STI (SCEI–Toshiba–IBM) Design IBM as a leading-edge technology and server company. Center was formally opened in Austin, Texas, on Collaboration was initiated among SCEI (Sony March 9, 2001. The STI Design Center represented Computer Entertainment Incorporated), IBM, for a joint investment in design of about $400,000,000. microprocessor development, and Toshiba, as a Separate joint collaborations were also set in place development and high-volume manufacturing technology for process technology development. partner. This led to high-level architectural discussions A number of key elements were employed to drive the among the three companies during the summer of 2000. success of the Cell multiprocessor design. First, a holistic During a critical meeting in Tokyo, it was determined design approach was used, encompassing processor that traditional architectural organizations would not architecture, hardware implementation, system deliver the computational power that SCEI sought structures, and software programming models. -
Sony Computer Entertainment Inc. Introduces Playstation®4 (Ps4™)
FOR IMMEDIATE RELEASE SONY COMPUTER ENTERTAINMENT INC. INTRODUCES PLAYSTATION®4 (PS4™) PS4’s Powerful System Architecture, Social Integration and Intelligent Personalization, Combined with PlayStation Network with Cloud Technology, Delivers Breakthrough Gaming Experiences and Completely New Ways to Play New York City, New York, February 20, 2013 –Sony Computer Entertainment Inc. (SCEI) today introduced PlayStation®4 (PS4™), its next generation computer entertainment system that redefines rich and immersive gameplay with powerful graphics and speed, intelligent personalization, deeply integrated social capabilities, and innovative second-screen features. Combined with PlayStation®Network with cloud technology, PS4 offers an expansive gaming ecosystem that is centered on gamers, enabling them to play when, where and how they want. PS4 will be available this holiday season. Gamer Focused, Developer Inspired PS4 was designed from the ground up to ensure that the very best games and the most immersive experiences reach PlayStation gamers. PS4 accomplishes this by enabling the greatest game developers in the world to unlock their creativity and push the boundaries of play through a system that is tuned specifically to their needs. PS4 also fluidly connects players to the larger world of experiences offered by PlayStation, across the console and mobile spaces, and PlayStation® Network (PSN). The PS4 system architecture is distinguished by its high performance and ease of development. PS4 is centered around a powerful custom chip that contains eight x86-64 cores and a state of the art graphics processor. The Graphics Processing Unit (GPU) has been enhanced in a number of ways, principally to allow for easier use of the GPU for general purpose computing (GPGPU) such as physics simulation. -
Download Presentation
Computer architecture in the past and next quarter century CNNA 2010 Berkeley, Feb 3, 2010 H. Peter Hofstee Cell/B.E. Chief Scientist IBM Systems and Technology Group CMOS Microprocessor Trends, The First ~25 Years ( Good old days ) Log(Performance) Single Thread More active transistors, higher frequency 2005 Page 2 SPECINT 10000 3X From Hennessy and Patterson, Computer Architecture: A ??%/year 1000 Quantitative Approach , 4th edition, 2006 52%/year 100 Performance (vs. VAX-11/780) VAX-11/780) (vs. Performance 10 25%/year 1 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 • VAX : 25%/year 1978 to 1986 RISC + x86: 52%/year 1986 to 2002 Page 3 CMOS Devices hit a scaling wall 1000 Air Cooling limit ) 100 2 Active 10 Power Passive Power 1 0.1 Power Density (W/cm Power Density 0.01 1994 2004 0.001 1 0.1 0.01 Gate Length (microns) Isaac e.a. IBM Page 4 Microprocessor Trends More active transistors, higher frequency Log(Performance) Single Thread More active transistors, higher frequency 2005 Page 5 Microprocessor Trends Multi-Core More active transistors, higher frequency Log(Performance) Single Thread More active transistors, higher frequency 2005 2015(?) Page 6 Multicore Power Server Processors Power 4 Power 5 Power 7 2001 2004 2009 Introduces Dual core Dual Core – 4 threads 8 cores – 32 threads Page 7 Why are (shared memory) CMPs dominant? A new system delivers nearly twice the throughput performance of the previous one without application-level changes. Applications do not degrade in performance when ported (to a next-generation processor). -
Clearspeed Technical Training
ENVISION. ACCELERATE. ARRIVE. ClearSpeed Technical Training December 2007 Overview 1 Copyright © 2007 ClearSpeed Technology Inc. All rights reserved. www.clearspeed.com Presenters Ronald Langhi Technical Marketing Manager [email protected] Brian Sumner Senior Engineer [email protected] 2 Copyright © 2007 ClearSpeed Technology Inc. All rights reserved. www.clearspeed.com ClearSpeed Technology: Company Background • Founded in 2001 – Focused on alleviating the power, heat, and density challenges of HPC systems – 103 patents granted and pending (as of September 2007) – Offices in San Jose, California and Bristol, UK 3 Copyright © 2007 ClearSpeed Technology Inc. All rights reserved. www.clearspeed.com Agenda Accelerators ClearSpeed and HPC Hardware overview Installing hardware and software Thinking about performance Software Development Kit Application examples Help and support 4 Copyright © 2007 ClearSpeed Technology Inc. All rights reserved. www.clearspeed.com ENVISION. ACCELERATE. ARRIVE. What is an accelerator? 5 Copyright © 2007 ClearSpeed Technology Inc. All rights reserved. www.clearspeed.com What is an accelerator? • A device to improve performance – Relieve main CPU of workload – Or to augment CPU’s capability • An accelerator card can increase performance – On specific tasks – Without aggravating facility limits on clusters (power, size, cooling) 6 Copyright © 2007 ClearSpeed Technology Inc. All rights reserved. www.clearspeed.com All accelerators are good… for their intended purpose Cell and GPUs FPGAs •Good for video gaming tasks •Good for integer, bit-level ops •32-bit FLOPS, not IEEE •Programming looks like circuit design •Unconventional programming model •Low power per chip, but •Small local memory 20x more power than custom VLSI •High power consumption (> 200 W) •Not for 64-bit FLOPS ClearSpeed •Good for HPC applications •IEEE 64-bit and 32-bit FLOPS •Custom VLSI, true coprocessor •At least 1 GB local memory •Very low power consumption (25 W) •Familiar programming model 7 Copyright © 2007 ClearSpeed Technology Inc. -
Introduction Hardware Acceleration Philosophy Popular Accelerators In
Special Purpose Accelerators Special Purpose Accelerators Introduction Recap: General purpose processors excel at various jobs, but are no Theme: Towards Reconfigurable High-Performance Computing mathftch for acce lera tors w hen dea ling w ith spec ilidtialized tas ks Lecture 4 Objectives: Platforms II: Special Purpose Accelerators Define the role and purpose of modern accelerators Provide information about General Purpose GPU computing Andrzej Nowak Contents: CERN openlab (Geneva, Switzerland) Hardware accelerators GPUs and general purpose computing on GPUs Related hardware and software technologies Inverted CERN School of Computing, 3-5 March 2008 1 iCSC2008, Andrzej Nowak, CERN openlab 2 iCSC2008, Andrzej Nowak, CERN openlab Special Purpose Accelerators Special Purpose Accelerators Hardware acceleration philosophy Popular accelerators in general Floating point units Old CPUs were really slow Embedded CPUs often don’t have a hardware FPU 1980’s PCs – the FPU was an optional add on, separate sockets for the 8087 coprocessor Video and image processing MPEG decoders DV decoders HD decoders Digital signal processing (including audio) Sound Blaster Live and friends 3 iCSC2008, Andrzej Nowak, CERN openlab 4 iCSC2008, Andrzej Nowak, CERN openlab Towards Reconfigurable High-Performance Computing Lecture 4 iCSC 2008 3-5 March 2008, CERN Special Purpose Accelerators 1 Special Purpose Accelerators Special Purpose Accelerators Mainstream accelerators today Integrated FPUs Realtime graphics GiGaming car ds Gaming physics