DOCSLIB.ORG

Power Efficient Processor Design and the Cell Processor

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Power Efficient Processor Design and the Cell Processor Systems and Technology Group Power Efficient Processor Design and the Cell Processor H. Peter Hofstee, Ph. D. [email protected] Architect, Cell Synergistic Processor Element IBM Systems and Technology Group Austin, Texas © 2005 IBM Corporation Systems and Technology Group Agenda Power Efficient Processor Architecture System Trends Cell Processor Overview 2 © 2005 IBM Corporation Systems and Technology Group Power Efficient Architecture 3 © 2005 IBM Corporation Systems and Technology Group Limiters to Processor Performance Power wall Memory wall Frequency wall 4 © 2005 IBM Corporation Systems and Technology Group Power Wall (Voltage Wall) 1000 Power components: 100 ) 2 Active – Active power Power – Passive power 10 Passive Power • Gate leakage 1 • Sub-threshold leakage (source- 0.1 drain leakage) 0.01 Power Density (W/cm Power Density 1994 2004 Gate10S Tox=11A Stack 0.001 1 0.1 0.01 NET: INCREASINGGate Length PERFORMANCE (microns) REQUIRES INCREASING EFFICIENCY Gate dielectric approaching a fundamental limit (a few atomic layers) 5 © 2005 IBM Corporation Systems and Technology Group Memory wall Main memory now nearly 1000 cycles from the processor – Situation worse with (on-chip) SMP Memory latency penalties drive inefficiency in the design – Expensive and sophisticated hardware to try and deal with it – Programmers that try to gain control of cache content, but are hindered by the hardware mechanisms Latency induced bandwidth limitations – Much of the bandwidth to memory in systems can only be used speculatively – Diminishing returns from added bandwidth on traditional systems 6 © 2005 IBM Corporation Systems and Technology Group Frequency wall Increasing frequencies and deeper pipelines have reached diminishing returns on performance Returns negative if power is taken into account Results of studies depend on issue width of processor – The wider the processor the slower it wants to be – Simultaneous Multithreading helps to use issue slots efficiently Results depend on number of architected registers and workload – More registers tolerate deeper pipeline – Fewer random branches in application tolerates deeper pipelines 7 © 2005 IBM Corporation Systems and Technology Group Microprocessor Efficiency Recent History: –Gelsinger’s law • 1.4x more performance for 2x more transistors –Hofstee’s corollary • 1/1.4x efficiency loss in every generation • Examples: Cache size, OoO, Superscalar, etc. etc. Re-examine microarchitecture with performance per transistor as metric –Pipelining is last clear win 8 © 2005 IBM Corporation Systems and Technology Group Attacking the Performance Walls Multi-Core Non-Homogeneous Architecture – Control Plane vs. Data Plane processors – Attacks Power Wall 3-level Model of Memory – Main Memory, Local Store, Registers – Attacks Memory Wall Large Shared Register File & SW Controlled Branching – Allows deeper pipelines (11FO4 … helps power!) – Attacks Frequency Wall 9 © 2005 IBM Corporation Systems and Technology Group System Trends 10 © 2005 IBM Corporation Systems and Technology Group System Trends toward Integration Memory Northbridge Memory Cell Accel Processor Processor IO Southbridge IO Increased integration is driving processors to take on many functions typically associated with systems – Integration forces processor developers to address off- load and acceleration in the design of the processor – Integration of bridge chip functionality Virtualization technology is used to support non- homogeneous environments 11 © 2005 IBM Corporation Systems and Technology Group Next Generation Processors address Programming Complexity and Trend Towards Programmable Offload Engines with a Simpler System Alternative Streaming 64b Power Mem. Graphics Processor GPU Processor Contr. NIC Network Synergistic Processor Processor CPU CPU Security Security Processor .. Media . Media Processor Config. … Synergistic IO … Processor Hardwired Programmable Function ASIC Cell 12 © 2005 IBM Corporation Systems and Technology Group “Outward Facing” Aspects of Cell Cell is designed to be responsive .. to human user – Real-time response – Supports rich visual interfaces .. to network – Flexible, can support new standards – High-bandwidth – Content protection, privacy & security Contrast to traditional processors which evolved from “batch processing” mentality (inward focused). 13 © 2005 IBM Corporation Systems and Technology Group Cell Overview 14 © 2005 IBM Corporation Systems and Technology Group Key Attributes of Cell Cell is Multi-Core – Contains 64-bit Power Architecture TM – Contains 8 Synergistic Processor Elements (SPE) Cell is a Flexible Architecture – Multi-OS support (including Linux) with Virtualization technology – Path for OS, legacy apps, and software development Cell is a Broadband Architecture – SPE is RISC architecture with SIMD organization and Local Store – 128+ concurrent transactions to memory per processor Cell is a Real-Time Architecture – Resource allocation (for Bandwidth Measurement) – Locking Caches (via Replacement Management Tables) Cell is a Security Enabled Architecture – SPE dynamically reconfigurable as secure processors 15 © 2005 IBM Corporation Systems and Technology Group Cell Chip Block Diagram SPU SPE SXU SXU SXU SXU SXU SXU SXU SXU LS LS LS LS LS LS LS LS SMF SMF SMF SMF SMF SMF SMF SMF EIB (up to 96 Bytes/cycle) PPE L2 MIC BIC TM Dual XDRTM FlexIO L1 PXU 16 © 2005 IBM Corporation Systems and Technology Group Cell Prototype Die (Pham et al, ISSCC 2005) S S S S P P P P U U U U P M P R B I U MIB R I C A C C S S S S P P P P U U U U 17 © 2005 IBM Corporation Systems and Technology Group Cell Highlights Observed clock speed – > 4 GHz Peak performance (single precision) – > 256 GFlops Peak performance (double precision) – >26 GFlops Area 221 mm2 Technology 90nm SOI Total # of transistors 234M 18 © 2005 IBM Corporation Systems and Technology Group Element Interconnect Bus EIB data ring for internal communication – Four 16 byte data rings, supporting multiple transfers – 96B/cycle peak bandwidth – Over 100 outstanding requests 19 © 2005 IBM Corporation Systems and Technology Group Power Processor Element PPE handles operating system and control tasks – 64-bit Power ArchitectureTM with VMX – In-order, 2-way hardware Multi-threading – Coherent Load/Store with 32KB I & D L1 and 512KB L2 20 © 2005 IBM Corporation Systems and Technology Group Synergistic Processor Element SPE provides computational performance – Dual issue, up to 16-way 128-bit SIMD – Dedicated resources: 128 128-bit RF, 256KB Local Store – Each can be dynamically configured to protect resources – Dedicated DMA engine: Up to 16 outstanding request 21 © 2005 IBM Corporation Systems and Technology Group SPE Highlights User-mode architecture – No translation/protection within SPU – DMA is full Power Arch protect/x-late LS DP Direct programmer control SFP SPU – DMA/DMA-list LS FXU EVN – Branch hint FWD VMX-like SIMD dataflow FXU ODD LS – Broad set of operations – Graphics SP-Float GPR – IEEE DP-Float (BlueGene-like) CONTROL LS CHANNEL Unified register file DMA SMM – 128 entry x 128 bit ATO SMF RTB 256kB Local Store SBI B E B – Combined I & D 14.5mm2 (90nm SOI) – 16B/cycle L/S bandwidth – 128B/cycle DMA bandwidth 22 © 2005 IBM Corporation Systems and Technology Group SPE Organization (Flachs et al, ISSCC 2005) 23 © 2005 IBM Corporation Systems and Technology Group SPE PIPELINE (Flachs et al, ISSCC 2005) 24 © 2005 IBM Corporation Systems and Technology Group I/O and Memory Interfaces I/O Provides wide bandwidth – Dual XDRTM controller (25.6GB/s @ 3.2Gbps) – Two configurable interfaces (76.8GB/s @6.4Gbps) – Flexible Bandwidth between interfaces – Allows for multiple system configurations 25 © 2005 IBM Corporation Systems and Technology Group Cell Processor Can Support Many Systems Game console systems XDRtm XDRtm XDRtm XDRtm Workstations (CPBW) HDTV Home media servers CELL CELL Processor Processor Supercomputers IOIF BIF IOIF XDRtm XDRtm XDRtm XDRtm XDRtm XDRtm CELL CELL Processor Processor IOIF IOIF BIF BIF SW IOIF IOIF Processor Processor CELL CELL CELL Processor XDR XDR XDR XDR tm tm tm IOIF0 IOIF1 tm 26 © 2005 IBM Corporation Systems and Technology Group Cell Processor Based Workstation (CPBW) (Sony Group and IBM) CELL Processor Board High BW Sys First Prototype “Powered On” Storage Networks Mgmt I/O 16 Tera-flops in a rack (est.) Bridge CELL Processor – ( equals 1 Peta-flop in 64 racks ) (2-Way SMP) Memory Optimized for Digital Content 16 TFlop rack Creation, including • Computer entertainment • Movies • Real-time rendering … • Physics simulation 27 © 2005 IBM Corporation Systems and Technology Group Cell Processor Example Application Areas Cell is a processor that excels at processing of rich media content in the context of broad connectivity – Digital content creation (games and movies) – Game playing and game serving – Distribution of (dynamic, media rich) content – Imaging and image processing – Image analysis (e.g. video surveillance) – Next-generation physics-based visualization – Video conferencing (3D?) – Streaming applications (codecs etc.) – Physical simulation & science 28 © 2005 IBM Corporation Systems and Technology Group Summary Cell ushers in a new era of leading edge processors optimized for digital media and entertainment Desire for realism is driving a convergence between supercomputing and entertainment New levels of performance and power efficiency beyond what is achieved by PC processors Responsiveness to the human user and the network are key drivers for Cell Cell will enable entirely new classes of applications, even beyond those we contemplate today 29 © 2005 IBM Corporation Systems and Technology Group Acknowledgements Cell is the result of a deep partnership between SCEI/Sony, Toshiba, and IBM Cell represents the work of more than 400 people starting in 2001 More detailed papers on the Cell implementation and the SPE micro-architecture can be found in the ISSCC 2005 proceedings 30 © 2005 IBM Corporation.
Load more

Recommended publications
  • Quietrock Case Study | Sony Computer Entertainment America
    Studios & Entertainment Quiet® Success Story Project: ® Sony Computer Entertainment ‘Sh-h-h-h!’ PlayStation 4 game- America, LLC making in progress! Location: San Mateo, California New sound studios spearhead renovations for Sony Computer General Contractor: Entertainment America, with an acoustical assist from Magnum Drywall Magnum Drywall and PABCO® Gypsum’s QuietRock® Products: QuietRock® FLAME CURB® San Mateo, California The Sound of Silence means a lot to engineers producing video games for Sony PlayStation®4 (PS4™) enthusiasts. At Sony Computer Entertainment America LLC headquarters in San Mateo, California, producers’ tolerance for intrusive noise from beyond studio walls is zero. Only the intense action on-screen matters while creating audio effects that dramatize, punctuate and heighten the deeply immersive experience for video gamers. In these studios Sony Entertainment sound engineers make the most of that capability while keeping the PlayStation® pipeline full for weekly launches of new games. The gaming experience draws players to PS4™ and its predecessor PlayStation® consoles, and PS4™ elevates 3D excitement ever higher. It’s the world’s most powerful games console, with a Graphics Processing Unit (GPU) able to perform 1,843 teraflops*. “When sound is important, we prefer to submit QuietRock as a good solution for the architect and the owner. There’s nothing else on the market that’s comparable. I even used it in my own home movie theatre.”” – Gary Robinson, Owner Magnum Drywall what the job demands Visit www.QuietRock.com or call Call 1.800.797.8159 for more information On top of its introductory lineup in November 2013, over 180 PS4™ games are in development, including “Be the Batman”, the epic conclusion of the “Batman: Arkham Knight” trilogy, that is due out in June 2015.
    [Show full text]
  • List of Notable Handheld Game Consoles (Source
    List of notable handheld game consoles (source: http://en.wikipedia.org/wiki/Handheld_game_console#List_of_notable_handheld_game_consoles) * Milton Bradley Microvision (1979) * Epoch Game Pocket Computer - (1984) - Japanese only; not a success * Nintendo Game Boy (1989) - First internationally successful handheld game console * Atari Lynx (1989) - First backlit/color screen, first hardware capable of accelerated 3d drawing * NEC TurboExpress (1990, Japan; 1991, North America) - Played huCard (TurboGrafx-16/PC Engine) games, first console/handheld intercompatibility * Sega Game Gear (1991) - Architecturally similar to Sega Master System, notable accessory firsts include a TV tuner * Watara Supervision (1992) - first handheld with TV-OUT support; although the Super Game Boy was only a compatibility layer for the preceding game boy. * Sega Mega Jet (1992) - no screen, made for Japan Air Lines (first handheld without a screen) * Mega Duck/Cougar Boy (1993) - 4 level grayscale 2,7" LCD - Stereo sound - rare, sold in Europe and Brazil * Nintendo Virtual Boy (1994) - Monochromatic (red only) 3D goggle set, only semi-portable; first 3D portable * Sega Nomad (1995) - Played normal Sega Genesis cartridges, albeit at lower resolution * Neo Geo Pocket (1996) - Unrelated to Neo Geo consoles or arcade systems save for name * Game Boy Pocket (1996) - Slimmer redesign of Game Boy * Game Boy Pocket Light (1997) - Japanese only backlit version of the Game Boy Pocket * Tiger game.com (1997) - First touch screen, first Internet support (with use of sold-separately
    [Show full text]
  • 14789093.Pdf
    iNIS-mf—8658 THE INFLUENCE OF COLLISIONS WITH NOBLE GASES ON SPECTRAL LINES OF HYDROGEN ISOTOPES PROEFSCHRIFT TER VERKRIJGING VAN DE GRAAD VAN DOCTOR IN DE WISKUNDE EN NATUURWETENSCHAPPEN AAN DE RIJKSUNIVERSITEIT TE LEIDEN, OP GEZAG VAN DE RECTOR MAGNIFICUS DR. A.A.H. KASSENAAR, HOOGLERAAR IN DE FACULTEIT DER GENEESKUNDE, VOLGENS BESLUIT VAN HET COLLEGE VAN DEKANEN TE VERDEDIGEN OP WOENSDAG 10 NOVEMBER 1982 TE KLOKKE 14.15 UUR DOOR PETER WILLEM HERMANS GEBOREN TE ROTTERDAM IN 1952 1982 DRUKKERIJ J.H. PASMANS B.V., 's-GRAVENHAGE Promotor: Prof. dr. J.J.M. Beenakker Het onderzoek is uitgevoerd mede onder verantwoordelijkheid van wijlen prof. dr. H.F.P. Knaap Aan mijn oudeva Het 1n dit proefschrift beschreven onderzoek werd uitgevoerd als onderdeel van het programma van de werkgemeenschap voor Molecuul fysica van de Stichting voor Fundamenteel Onderzoek der Materie (FOM) en is mogelijk gemaakt door financiële steun van de Nederlandse Organisatie voor Zuiver- WetenschappeHjk Onderzoek (ZWO). CONTENTS PREFACE 9 CHAPTER I THEORY OF THE COLLISIONAL BROADENING AND SHIFT OF SPECTRAL LINES OF HYDROGEN INFINITELY DILUTED IN NOBLE GASES 11 1. Introduction 11 2. General theory 12 a. Rotational Raman 15 b. Depolarized Rayleigh 16 3. Experimental preview 16 a. Rotational Raman lines; broadening and shift 17 b. Depolarized Rayleigh line 17 CHAPTER II EXPERIMENTAL DETERMINATION OF LINE BROADENING AND SHIFT CROSS SECTIONS OF HYDROGEN-NOBLE GAS MIXTURES 21 1. Introduction 21 2. Experimental setup 22 2.1 Laser 22 2.2 Scattering cell 24 2.3 Analyzing system 27 2.4 Detection system 28 3. Measuring technique 28 3.1 Width measurement 28 3.2 Shift measurement 32 3.3 Gases 32 4.
    [Show full text]
  • POWER® Processor-Based Systems
    IBM® Power® Systems RAS Introduction to IBM® Power® Reliability, Availability, and Serviceability for POWER9® processor-based systems using IBM PowerVM™ With Updates covering the latest 4+ Socket Power10 processor-based systems IBM Systems Group Daniel Henderson, Irving Baysah Trademarks, Copyrights, Notices and Acknowledgements Trademarks IBM, the IBM logo, and ibm.com are trademarks or registered trademarks of International Business Machines Corporation in the United States, other countries, or both. These and other IBM trademarked terms are marked on their first occurrence in this information with the appropriate symbol (® or ™), indicating US registered or common law trademarks owned by IBM at the time this information was published. Such trademarks may also be registered or common law trademarks in other countries. A current list of IBM trademarks is available on the Web at http://www.ibm.com/legal/copytrade.shtml The following terms are trademarks of the International Business Machines Corporation in the United States, other countries, or both: Active AIX® POWER® POWER Power Power Systems Memory™ Hypervisor™ Systems™ Software™ Power® POWER POWER7 POWER8™ POWER® PowerLinux™ 7® +™ POWER® PowerHA® POWER6 ® PowerVM System System PowerVC™ POWER Power Architecture™ ® x® z® Hypervisor™ Additional Trademarks may be identified in the body of this document. Other company, product, or service names may be trademarks or service marks of others. Notices The last page of this document contains copyright information, important notices, and other information. Acknowledgements While this whitepaper has two principal authors/editors it is the culmination of the work of a number of different subject matter experts within IBM who contributed ideas, detailed technical information, and the occasional photograph and section of description.
    [Show full text]
  • Zoned Storage for HDD and SSD Technologies
    Zoned Storage Now Encompasses Both HDD & SSD Technologies WHITE PAPER 3 Western Digital | WHITE PAPER WHITE PAPER Zoned Storage Now Encompasses Both HDD & SSD Technologies Both HDDs and SSDs have their own on-device controllers that are used to provide low-level manipulation of the drives. The division of compute tasks performed by the host-side CPUs and the drive-side controllers has evolved over time, with the boundaries moving back and forth between them. Computational architectures have evolved, especially in data centers where — as systems started to scale — local optimizations performed by the devices began to impact global optimizations. The concept of Zoned Storage is a relatively recent development that refers to a class of storage devices — both HDDs and SSDs — that enable the host system and the storage devices to cooperate so as to achieve higher storage capacities. As its name suggests, Zoned Storage involves organizing or partitioning the drives into zones. In the case of HDDs, Zoned Storage is implemented using a technology known as shingled magnetic recording (SMR). In the case of SSDs, Zoned Storage is implemented using a technology known as Zoned Namespaces (ZNS). Data Taken As-Is Serialize Data Zoned Storage Zoned Storage 2 HDDs An HDD contains one or more rigid rapidly rotating platters coated with a magnetic material. Electromagnetic read/write heads are positioned above and below each platter. Data is stored on the platter as a series of thin concentric rings called tracks. In turn, the tracks are sub-divided into sectors. The HDD also contains a hard disk controller (HDC), which may be thought of as a small processor that is used to provide low-level control of the drive.
    [Show full text]
  • Storage Solutions for Embedded Applications
    White Paper Storage Solutions Brian Skerry Sr. Software Architect Intel Corporation for Embedded Applications December 2008 1 321054 Storage Solutions for Embedded Applications Executive Summary Any embedded system needs reliable access to storage. This may be provided by a hard disk drive or access to a remote storage device. Alternatively there are many flash solutions available on the market today. When considering flash, there are a number of important criteria to consider with capacity, cost, and reliability being foremost. This paper considers hardware, software, and other considerations in choosing a storage solution. Wear leveling is an important factor affecting the expected lifetime of any flash solution, and it can be implemented in a number of ways. Depending on the choices made, software changes may be necessary. Solid state drives offer the most straight forward replacement option for Hard disk drives, but may not be cost-effective for some applications. The Intel® X-25M Mainstream SATA Solid State Drive is one solution suitable for a high performance environment. For smaller storage requirements, CompactFlash* and USB flash are very attractive. Downward pressure continues to be applied to flash solutions, and there are a number of new technologies on the horizon. As a result of reading this paper, the reader will be able to take into consideration all the relevant factors in choosing a storage solution for an embedded system. Intel® architecture can benefit the embedded system designer as they can be assured of widespread
    [Show full text]
  • Introduction to the Cell Multiprocessor
    Introduction J. A. Kahle M. N. Day to the Cell H. P. Hofstee C. R. Johns multiprocessor T. R. Maeurer D. Shippy This paper provides an introductory overview of the Cell multiprocessor. Cell represents a revolutionary extension of conventional microprocessor architecture and organization. The paper discusses the history of the project, the program objectives and challenges, the design concept, the architecture and programming models, and the implementation. Introduction: History of the project processors in order to provide the required Initial discussion on the collaborative effort to develop computational density and power efficiency. After Cell began with support from CEOs from the Sony several months of architectural discussion and contract and IBM companies: Sony as a content provider and negotiations, the STI (SCEI–Toshiba–IBM) Design IBM as a leading-edge technology and server company. Center was formally opened in Austin, Texas, on Collaboration was initiated among SCEI (Sony March 9, 2001. The STI Design Center represented Computer Entertainment Incorporated), IBM, for a joint investment in design of about $400,000,000. microprocessor development, and Toshiba, as a Separate joint collaborations were also set in place development and high-volume manufacturing technology for process technology development. partner. This led to high-level architectural discussions A number of key elements were employed to drive the among the three companies during the summer of 2000. success of the Cell multiprocessor design. First, a holistic During a critical meeting in Tokyo, it was determined design approach was used, encompassing processor that traditional architectural organizations would not architecture, hardware implementation, system deliver the computational power that SCEI sought structures, and software programming models.
    [Show full text]
  • Sony Computer Entertainment Inc. Introduces Playstation®4 (Ps4™)
    FOR IMMEDIATE RELEASE SONY COMPUTER ENTERTAINMENT INC. INTRODUCES PLAYSTATION®4 (PS4™) PS4’s Powerful System Architecture, Social Integration and Intelligent Personalization, Combined with PlayStation Network with Cloud Technology, Delivers Breakthrough Gaming Experiences and Completely New Ways to Play New York City, New York, February 20, 2013 –Sony Computer Entertainment Inc. (SCEI) today introduced PlayStation®4 (PS4™), its next generation computer entertainment system that redefines rich and immersive gameplay with powerful graphics and speed, intelligent personalization, deeply integrated social capabilities, and innovative second-screen features. Combined with PlayStation®Network with cloud technology, PS4 offers an expansive gaming ecosystem that is centered on gamers, enabling them to play when, where and how they want. PS4 will be available this holiday season. Gamer Focused, Developer Inspired PS4 was designed from the ground up to ensure that the very best games and the most immersive experiences reach PlayStation gamers. PS4 accomplishes this by enabling the greatest game developers in the world to unlock their creativity and push the boundaries of play through a system that is tuned specifically to their needs. PS4 also fluidly connects players to the larger world of experiences offered by PlayStation, across the console and mobile spaces, and PlayStation® Network (PSN). The PS4 system architecture is distinguished by its high performance and ease of development. PS4 is centered around a powerful custom chip that contains eight x86-64 cores and a state of the art graphics processor. The Graphics Processing Unit (GPU) has been enhanced in a number of ways, principally to allow for easier use of the GPU for general purpose computing (GPGPU) such as physics simulation.
    [Show full text]
  • Re-Imaging an Exadata Storage Cell Using an Internal Or External Usb Drive
    RE-IMAGING AN EXADATA STORAGE CELL USING AN INTERNAL OR EXTERNAL USB DRIVE www.hexaware.com Table of Contents Oracle Exadata Storage Server Software Rescue Procedure – A Brief Introduction 3 A Fast Forward experience to backup/restore/recovery 3 testing of your Future Exadata Environment Cell Node Re-Imaging - Ideal Scenarios 3 Pragmatic Scenarios where cell node re-imaging is not required 3 Recovering a Cell Node using Internal USB 4 Recovering Cell Node using External USB 7 Summary 7 1 Oracle Exadata Storage Server Software Rescue Procedure - A Brief Introduction A Fast Forward experience to backup/restore/recovery testing of your Future Exadata Environment • Have you experienced a disk failure and are deeply concerned about your operating system? • Has your system volume got corrupted due to the loss of disks? • Does your operating system have a corrupt file system? You can resolve these issues yourself using the Exadata Cell rescue functionality provided by Oracle on Exadata Storage Server Software CELLBOOT USB flash drive. The whole procedure is quite straightforward, but enough due diligence must be done to make the recovery a delightful experience. Oracle performs automatic backups of the operating system and cell software on each Exadata Storage Server without any Oracle DMA or operational process intervention. The critical files from the storage cells are backed up into the internal USB drive called CELLBOOT USB Flash Drive. The internal USB (/dev/sdm) maintains the most recent configuration and the updated copy of the OS and storage cell software. The internal USB serves as the default first boot device. The Master Boot Record (MBR) and GRand Unified Boot loader (GRUB) are loaded from the USB.
    [Show full text]
  • Annual Report 2011
    Contents 02-19 Letter to Shareholders: A Message from Howard Stringer, CEO Dear Shareholders Operating Results in Fiscal Year 2010 Focus Areas for Growth Networked Products and Services 3D World Competitive Advantages through Differentiated Technologies Emerging Markets 06 10 Expanding 3D World Networked Products 3D World and Services 12 15 Competitive Advantages through Emerging Markets Differentiated Technologies 20 26 Special Feature: Special Feature: Sony’s “Exmor RTM” Sony in India 34 40 Financial Highlights Products, Services and Content 50 51 Board of Directors and Financial Section Corporate Executive Officers 64 65 Stock Information Investor Information ©2011 Columbia Pictures Industries, Inc., All Rights Reserved. For more information on Sony’s financial performance, corporate governance, CSR and Financial Services business, please refer to the following websites. 2011 Annual Report on Form 20-F http://www.sony.net/SonyInfo/IR/library/sec.html Corporate Governance Structure http://www.sony.net/SonyInfo/csr/governance/index.html CSR Report http://www.sony.net/SonyInfo/Environment/index.html Financial Services Business http://www.sonyfh.co.jp/index_en.html (Sony Financial Holdings Inc.) Artist: Adele Photo credit: Mari Sarai 01 Letter to Shareholders: A Message from Howard Stringer, CEO 02 Dear Shareholders, A review of the fiscal year ended March 31, 2011 (fiscal year 2010) must first mention the Great East Japan Earthquake, which occurred near the end of the fiscal year. On March 11, at 2:46 p.m. local time, East Japan was struck by a 9.0-magnitude earthquake, immedi- ately followed by a giant tsunami, which had, in addition to the tragic loss of life and property, a profound psychological and financial impact on the people of Japan.
    [Show full text]
  • Download Presentation
    Computer architecture in the past and next quarter century CNNA 2010 Berkeley, Feb 3, 2010 H. Peter Hofstee Cell/B.E. Chief Scientist IBM Systems and Technology Group CMOS Microprocessor Trends, The First ~25 Years ( Good old days ) Log(Performance) Single Thread More active transistors, higher frequency 2005 Page 2 SPECINT 10000 3X From Hennessy and Patterson, Computer Architecture: A ??%/year 1000 Quantitative Approach , 4th edition, 2006 52%/year 100 Performance (vs. VAX-11/780) VAX-11/780) (vs. Performance 10 25%/year 1 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 • VAX : 25%/year 1978 to 1986 RISC + x86: 52%/year 1986 to 2002 Page 3 CMOS Devices hit a scaling wall 1000 Air Cooling limit ) 100 2 Active 10 Power Passive Power 1 0.1 Power Density (W/cm Power Density 0.01 1994 2004 0.001 1 0.1 0.01 Gate Length (microns) Isaac e.a. IBM Page 4 Microprocessor Trends More active transistors, higher frequency Log(Performance) Single Thread More active transistors, higher frequency 2005 Page 5 Microprocessor Trends Multi-Core More active transistors, higher frequency Log(Performance) Single Thread More active transistors, higher frequency 2005 2015(?) Page 6 Multicore Power Server Processors Power 4 Power 5 Power 7 2001 2004 2009 Introduces Dual core Dual Core – 4 threads 8 cores – 32 threads Page 7 Why are (shared memory) CMPs dominant? A new system delivers nearly twice the throughput performance of the previous one without application-level changes. Applications do not degrade in performance when ported (to a next-generation processor).
    [Show full text]
  • Building a Distributed Supercomputer Using Cell Processors
    PS3GRID.NET: Building a distributed supercomputer using Cell processors Gianni De Fabritiis, Computational Biochemistry and Biophysics Laboratory (GRIB), Universitat Pompeu Fabra, Barcelona Biomedical Research Park (PRBB) [email protected] Molecular simulations (MS) methods will mature in the next few years to be able to simulate temporal scales of biological interests, changing drastically its importance in biological discovery. Gianni De Fabritiis, Uniiversity Pompeu Fabra 2 Why not now? . MD: Newton Equation . Characteristic scales . Timescale: 10E-15 s . Lengthscale: 10E-10 m . Application scales (biology) . Micro-milli seconds . 10-100 nm . Current resolution: . Nanoseconds . 10 nm Helical dimer (PDB: 1JNO) Lipids not shown Gianni De Fabritiis, Uniiversity Pompeu Fabra 3 Where are we going? Source: NVIDIA Gianni De Fabritiis, Uniiversity Pompeu Fabra 4 Accelerator processors: A new challenging era for computational science We are at a crucial critical point in . Data-memory the evolution of microprocessors: Single core => multi-core . Every CPU maker (IBM, INTEL, AMD, NVIDIA) is working on Memory heavily multi-core chips handling bottleneck hundreds of threads. A different memory architecture is needed => IBM Cell processor, GPUs Computation-cpus Gianni De Fabritiis, Uniiversity Pompeu Fabra 5 Cell Processor . 9 cores (1 PPE + 8 SPEs) . Only 80$ per chip . 230 Gflops in single precision . 8 SPE cores are specialized for number crunching with local memory access. Altivec-like, memory alignment, async DMA, mailboxes, signals, memory mapped (16 SPEs in shared mem) Gianni De Fabritiis, Uniiversity Pompeu Fabra 6 Sony-Toshiba-IBM Cell Processor . Available: IBM blades (roadrunner, 16,000 Cell) and PlayStation3 . Software barriers: . Codes do not automatically run faster .
    [Show full text]