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RZ FAMILY Renesas Microprocessor 2018.10 THE NEXT-GENERATION PROCESSOR TO MEET THE NEEDS OF THE SMART SOCIETY HAS ARRIVED. achine In M te n r a f a m c u e H ntr wo Co ol Net rk CONTENTS RZ/A SERIES ___________________________________________ 04 RZ/G SERIES ___________________________________________ 10 RZ/T SERIES ___________________________________________ 16 RZ/N SERIES ___________________________________________ 22 RZ SPECIFICATIONS ______________________________________ 28 PACKAGE LINEUP _______________________________________ 38 02-03 The utilization of intelligent technology is advancing in all aspects of our lives, including electric household appliances, industrial equipment, building management, power grids, and transportation. The cloud-connected “smart society” is coming ever closer to realization. Microcontrollers are now expected to provide powerful capabilities not available previously, such as high-performance and energy-efficient control combined with interoperation with IT networks, support for human-machine interfaces, and more. To meet the demands of this new age, Renesas has drawn on its unmatched expertise in microcontrollers to create the RZ family of embedded processors. The lineup of these “next-generation processors that are as easy to use as conventional microcontrollers” to meet different customer requirements. The Zenith of the Renesas micro As embedded processors to help build the next generation of advanced products, the RZ family offers features not available elsewhere and brings new value to customer applications. ¢ RZ Family Roadmap RZ/G1H Cortex®-A15x4 (1.4GHz) Cortex®-A7x4 (780MHz) G6400, H.264 32bit×2ch DDR3-1600 RZ/G1M Cortex®-A15x2 (1.5GHz) SGX544MP2, H.264 RZ/G2x RZ/G series 32bit×2ch DDR3L-1600 3D Graphics RZ/G1N HMI MPU Cortex®-A15x2 (1.5GHz) SGX544MP2, H.264 32bit×1ch DDR3L-1600 RZ/G1E RZ/G1C Cortex®-A7x2 (1.0GHz) Cortex®-A7x2 (1.0GHz) SGX540, H.264 SGX531, H.264 32bit×1ch DDR3-1333 32bit×1ch DDR3-1000 RZ/A2M RZ/A1H Cortex®-A9 (528MHz) Cortex®-A9 (400MHz) RZ/A1LU 4MB, XGA, 2D 10MB, WXGA, 2D Cortex®-A9 (400MHz) RZ/A series RZ/A1M 3MB, XGA, JPEG Cortex®-A9 (400MHz) for HMI Apps. RZ/A1L 5MB, WXGA, 2D Cortex®-A9 (400MHz) RZ/A1LC 3MB XGA Cortex®-A9 (400MHz) 2MB, XGA RZ/N1D Cortex®-A7 Dual (500MHz) RZ/N-next(TBD) RZ/N series RZ/N1S Cortex®-A7 Connectivity (500MHz) PLC RZ/N1L Cortex®-M3 (125MHz) RZ/T1 Cortex®-R4 (600/450MHz) RZ/T-next(TBD) 544K TCM + 1MB, R-IN Engine RZ/T series RZ/T1 Cortex®-R4 (600/450/300MHz) for Real-time Ctrl. 544K TCM + 1MB, EtherCAT RZ/T1 Development Cortex®-R4 (450MHz) Planning 544K TCM under discussion Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the EU and/or elsewhere. RZ/A Series RZ/A Series: Roadmap RZ/A2M RZ/A1H Cortex®-A9 (528MHz) Cortex®-A9 (400MHz) RZ/A1LU 4MB, XGA, 2D 10MB, WXGA, 2D Cortex®-A9 (400MHz) RZ/A series RZ/A1M 3MB, XGA, JPEG for HMI Apps. Cortex®-A9 (400MHz) RZ/A1L 5MB, WXGA, 2D Cortex®-A9 (400MHz) RZ/A1LC 3MB XGA Cortex®-A9 (400MHz) 2MB, XGA 2014 2015 2016 2017 2018 2019 2020 2021 CY RZ/A Series: Application Fields Intercoms White goods White goods Vending machines Digital signage Diagnostic panels Industrial panels Barcode scanners Office equipment Image sensor Data communication modules Robot Biometrics Handwriting recognition input devices (telematics, emergency communications) RZ/A Series Features • Large-capacity on-chip RAM: 10MB • Graphics display and camera input capabilities on a single chip • Rich peripheral functions and software ¢ Large-capacity on-chip RAM: 10MB DRAM-less solution Conventional MPU concept RZ/A concept 5V/12V 5V/12V Higher costs Regulator Regulator Regulator Regulator Regulator 3.3V 1.2V 1.5V / 0.75V 3.3V 1.2V NOR Conventional MPU DDR3 SPI Flash Flash RZ/A Advantages •No need to design a high-speed interface •Reduced mounting area Higher costs •Reduced PCB cost •No DRAM procurement issues •Reduced EMI noise 4 PCB layers for 1.2V, 3.3V 6 PCB layers for 1.2V, 3.3V, 1.5V/0.75V (DDR3) 04-05 ¢ Graphics display and camera input capabilities on a single chip Video Display Controller ch1 (A1H and A1M only) Integration of multiple layers of data and output to LCD Video Display Controller ch0 Buffer CPU Internal CPU bus Storage of input images Use of graphics bus by 1 via graphics bus VDC to fetch multiple Internal 2 layers of display data Graphics bus { 3 4 Page0 Page1 Page2 Page3 Page4 Page0 Page1 Page2 Page3 Page4 A1H (10MB) (2MB) (2MB) (2MB) (2MB) (2MB) Large-capacity on-chip RAM (2MB) (2MB) (2MB) (2MB) (2MB) A1M [5MB] [1MB] [1MB] [1MB] [1MB] [1MB] [1MB] [1MB] [1MB] [1MB] [1MB] A2M《 4MB》 《{512KB}512KB》 《{512KB}512KB》 《{512KB}1MB》 《{512KB}1MB》 《{1MB}1MB》 A1L、A1LU {3MB} {512KB} {512KB} {512KB} {512KB} {1MB} A1LC〈 2MB〉 〈512MB〉 〈512MB〉 〈512MB〉 〈512MB〉 〈—〉 The bus configuration with independent buses for images and hardware-based superimposition processing make it easy to create graphical applications. ¢ Rich peripheral functions and software Graphics Camera Example system solution Real-time correction of distorted images RZ/A Input image Output image On-chip 2D graphics “Smooth” and“beautiful” CPU accelerator for fast image graphics display by utilizing Ability to process imported Ability to connect analog rendering large-capacity on-chip RAM images and extract a variety of CMOS cameras to the full HMI functions information Large-capacity on-chip RAM Network DRP (Dynamically Reconfigurable Processor) Wired LAN/wireless LAN • Software • Graphics • Face recognition, human sensing • Image compression, Narrowing down by RZ/A1 Reduction of network decompression of only valuable information communication • Voice synthesis, Ability to accelerate image processing for applications for transmission over the volume/ability to increase etc. such as barcode readers and biometric authentication network number of cameras flexibly With ample peripheral functions and software, a single chip can cover a wide range of fields, including display, camera input, communication, and audio functions. HMI Solutions Full HD (1920×1080) RZ/G Series Large-capacity on-chip memory RTOS Simple HMI development as Compact HMI with microcontrollers development RZ/A Series RZ/A1LU RZ/A2M WXGA and below (1280×768) RZ/A1L RZ/A1H RZ/A1LC RZ/A1M Image display functions only Image display functions Image display functions + 2D graphics + 3D graphics + video support • HMI solutions optimized to match the image resolution, functions, and OS • RZ/G series: Full HD, functions: 3D Gfx, vide, OS: Linux (RichOS) • RZ/A series: WXGA and below, functions: 2D Gfx, camera input processing, OS: RTOS RZ/A2M Group ¢ RZ/A2M block diagram System CPU Interfaces CPU (Arm® Cortex®-A9) 2 • Operating frequency: 528MHz DMAC 16ch Cortex®-A9 528 MHz I C 4ch • Single-precision/double-precision FPU Interrupt Controller NEON FPU SCI • Arm® NEON™ PLL/SSCG 2ch On-chip memory On-chip Debug Memory SCIF (UART) • 4MB (JTAG/SWD) 5ch SRAM: 4MB Main graphics and camera input functions Standby RSPI I CACHE: 32KB D Cache: 32KB 3ch • Video display controller (VDC6): 1 channel (Sleep/Software/Deep/Module) LCD output: Max. WXGA L2 Cache: 128KB CAN-FD 2ch Screen superimposition: 3 layers Timers Ethernet MAC Graphics Video input: Max. XGA OSTM (100M: IEEE1588 v2) • CMOS camera input (CEU): 1 channel 32-bit × 3ch VDC6 (LCDC) LVDS 2ch • MIPI-CSI2 interface: 1 channel MTU3 Timing Controller IMR-LS2 IrDA 32-bit × 1ch Digital Input • Distortion compensation unit (IMR): 1 channel Sprite Engine SSI (I2S) MTU3 • 2D graphics engine: 1 channel 4ch 16-bit × 8ch CMOS Camera I/F 2D Graphics Engine • Sprite engine: 1 channel SPDIF PWM MIPI Camera I/F JPEG Codec Engine 1ch • JPEG coding engine: 1 channel 32-bit × 8ch Main memory interface functions BSC (E×t. Bus I/F) WDT Security (Option) • NOR flash, SDRAM, NAND flash RTC HyperFlash™ / HyperRAM™ • Serial flash: 1-bit/4-bit/8-bit: 1 channel, 8-bit: 1 channel Secure Boot (ability to run stored programs directly) DRP (option) Crypto Engine OctaFlash™ / OctaRAM™ • SD/MMC host interface: 2 channels (Dynamically Reconfigurable Processor) SPI Multi I/O (DDR) TRNG Main communication functions (1,4 or 8bit width) • USB 2.0 High Speed: 2 channels (Host/Function switchable) Device Unique ID NAND Flash I/F (ONFI1.0, ECC) • 10M/100M EtherMAC: 2 channels JTAG Disable USB2.0 • SCIF: 5 channels HS 2ch Host/Peripheral/OTG 2 • I C: 4 channels SDHI (UHS-I)/MMC • SSI: 4 channels 2ch • RSPI: 3 channels GPIO • CAN-FD: 2 channels Optional functions Analog • DRP (Dynamically Reconfigurable Processor) ADC Package 12-bit × 8ch • 176-LFBGA (13mm×13mm, 0.8mm pitch ) • 256-LFBGA (11mm×11mm, 0.5mm pitch • 272-FBGA (17mm×17mm, 0.8mm pitch • 324-FBGA (19mm×19mm, 0.8mm pitch 06-07 RZ/A1H Group and RZ/A1M Group (Pin Compatible) ¢ RZ/A1H,and RZ/A1M block diagram Memory CPU Interfaces CPU (Arm® Cortex®-A9) SRAM Cortex®-A9 400MHz 10/100 Ether MAC • Operating frequency: 400MHz A1H: 10MB/A1M: 5MB SRAM L2 Cache USB2.0 • Single-precision/double-precision FPU NEON FPU 128 KB HS 2ch Host/Func • Arm® NEON™ Cache NAND Flash On-chip memory 32 KB + 32 KB Timers I/F • RZ/A1H: 10MB MTU2 External Bus 32-bit ROM, • RZ/A1M: 5MB System 16-bit × 5ch SRAM, SDRAM, PCMCIA Main graphics and camera input functions WDT DMAC 16ch 8-bit × 1ch SPI Multi • Video display controller (VDC5): 2 channels 2ch Interrupt Controller OS Timer LCD output: Max. WXGA 32-bit × 2ch SCIF RSPI Screen superimposition: 4 layers Clock Generation PWM Timer 8ch 5ch Video input: Max. XGA (CVBS analog input supported) with SSCG 16ch I2C IEBus 4ch 1ch • CMOS camera input (CEU): 1 channel JTAG Debug Real-Time CLK SSI (I2S) SPDIF • PAL/NTSC decoder (DVDEC): 2 channels Secure Boot Engine* 6ch 1ch • Distortion compensation unit (IMR): 1 channel Graphics SDHI MMC • Open VG accelerator: 1 channel Customer Unique ID* Video Display Controller 2ch 1ch • JPEG coding engine: 1 channel 2ch CAN MOST50 Main memory interface functions Audio OpenVG 1.1 5ch 1ch • NOR flash, SDRAM, NAND flash Enhanced eng.
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  • Datasheet (1993)

    Datasheet (1993)

    D A'U 5-11 E E T WD90C33 High Performance VGA Controller ~ WESTERN DIGITAL Copyright © 1993 Western Digital Corporation All Rights Reserved Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corpora­ tion reserves the right to change specHications at any time without notice. Western Digital, AutoSwitch, and Paradise are registered trademarks and CacheFlow, Caviar, FIT Lab, Hyperseek, Interarchitecture, PinScan, Piranha, SAM, Tidbit, and TrueShade are trademarks of Western Digital Corporation. Other marks may be mentioned herein that belong to other Companies. Western Digital Corporation Western Digital Plaza, 8105 Irvine Center Drive, Irvine, CA 92718 For Service and Literature, call: (714) 932-4900 WD90C33 TABLE OF CONTENTS Section Title Page 1.0 INTRODUCTION ......................•.........................•..... 1 1. 1 General Description .. • . .• 1 1. 2 Features • . • . • . .. 1 1. 3 Document Scope .... • . • . .. 2 2.0 WD90C33 ARCHITECTURE ...........•.•............................... 3 3.0 WD9OC33 INTERFACES .••..............••..•..............•.•.•....... 4 3. 1 Introduction .•....................•............................ 4 3. 2 CPU (Host) And BIOS ROM Interface •.............................. 5 3. 3 Local Bus Video Subsystem Interface . • . .. 7 3.4 AT Compatible Bus Subsystem ....•............................... 8 3. 5 AT Compatible Interface (16-bits) and 8-bit BIOS ...................... 9 3.6 AT Compatible Interface (16-bits) and 16-bit BIOS ... " ............... 10 3. 7 DRAM Interface ................•.•............................ 11 3. 8 Two or Four 64K by 16 DRAM Interface ...........................