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Renesas Microprocessor RZ Family RZ FAMILY Renesas Microprocessor www.renesas.com 2017.07 01-02 THE NEXT-GENERATION PROCESSOR TO MEET THE NEEDS OF THE SMART SOCIETY HAS ARRIVED. The utilization of intelligent technology is advancing in all aspects of our lives, including electric household appliances, industrial equipment, building management, power grids, and transportation. The cloud-connected “smart society” is coming ever closer to realization. Microcontrollers are now expected to provide powerful capabilities not available previously, such as high-performance and energy-efficient control combined with interoperation with IT networks, support for human-machine interfaces, and more. To meet the demands of this new age, Renesas has drawn on its unmatched expertise in microcontrollers to create the new RZ family of embedded processors. The lineup of these “next-generation processors that are as easy to use as conventional microcontrollers” spans four product series to meet different customer requirements. The Zenith of the Renesas micro As embedded processors to help build the next generation of advanced products, the RZ family offers features not available elsewhere and brings new value achine In M te to customer applications. n r a f a m c u e H ¢ RZ Family Roadmap RZ/G1H Cortex®-A15x4 (1.4GHz) Cortex®-A7x4(780MHz) G6400, H.264 32bit×2ch DDR3-1600 RZ/G1M Cortex®-A15x2 (1.5GHz) RZ/G-next SGX544MP2, H.264 (T.B.D) 32bit×2ch DDR3L-1600 RZ/G1N Cortex®-A15x2 (1.5GHz) ntr wo SGX544MP2, H.264 Co ol Net rk 32bit×1ch DDR3L-1600 RZ/G series 3D Graphics RZ/G1E RZ/G1C Cortex®-A7x2 (1.0GHz) Cortex®-A7x2 (1.0GHz) HMI MPU SGX540, H.264 SGX531, H.264 32bit×1ch DDR3-1333 32bit×1ch DDR3-1000 RZ/A1H RZ/A-next Cortex®-A9(400MHz) RZ/A1LU Cortex®-A9(400MHz) 10MB, WXGA, 2D RZ/A1M 3MB, XGA, JPEG RZ/A series Cortex®-A9(400MHz) for HMI Apps. RZ/A1L 5MB, WXGA, 2D RZ/A1LC Cortex®-A9(400MHz) Cortex®-A9(400MHz) 3MB XGA RZ/N1D 2MB, XGA Cortex®-A7 Dual (500MHz) RZ/N1S Cortex®-A7 (500MHz) RZ/N series Connectivity RZ/N1L PLC Cortex®-M3 CONTENTS (125MHz) RZ/A SERIES ___________________________________________ 03 RZ/G SERIES ___________________________________________ 09 RZ/T1 RZ/T-next RZ/T SERIES ___________________________________________ 15 Cortex®-R4(600/450MHz) 544K TCM + 1MB, R-IN Engine (TBD) RZ/N SERIES ___________________________________________ 23 RZ/T1 Cortex®-R4(600/450/300MHz) RZ SPECIFICATIONS ______________________________________ 29 RZ/T series 544K TCM + 1MB, EtherCAT for Real-time Ctrl. PACKAGE LINEUP _______________________________________ 38 RZ/T1 Cortex®-R4(450MHz) Development 544K TCM Planning under discussion 2014 2015 2016 2017 2018 CY ARM® and Cortex® are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. 03-04 RZ/A Series ¢ Graphics display and camera input capabilities on a single chip RZ/A Series: Roadmap Video Display Controller ch1 (A1H and A1M only) Integration of multiple layers of data and output to LCD Video Display Controller ch0 Buffer RZ/A1H RZ/A-next Cortex®-A9(400MHz) RZ/A1LU Cortex®-A9(400MHz) CPU 10MB, WXGA, 2D RZ/A1M 3MB, XGA, JPEG RZ/A series Cortex®-A9(400MHz) for HMI Apps. RZ/A1L 5MB, WXGA, 2D RZ/A1LC Cortex®-A9(400MHz) Cortex®-A9(400MHz) 3MB XGA 2MB, XGA Development Internal CPU bus Storage of input images Use of graphics bus by 1 via graphics bus 2014 2015 2016 2017 2018 CY VDC to fetch multiple Internal 2 layers of display data Graphics bus { 3 RZ/A Series: Application Fields 4 Page0 Page1 Page2 Page3 Page4 Page0 Page1 Page2 Page3 Page4 Large-capacity on-chip RAM A1H (10MB) (2MB) (2MB) (2MB) (2MB) (2MB) A1M (5MB) (1MB)[1MB] (1MB)[1MB] (1MB)[1MB] [1MB](1MB) (1MB)[1MB] {512KB} {512KB} {512KB} {512KB} {1MB} Intercoms White goods White goods Vending machines Digital signage Diagnostic panels Industrial panels A1L,A1LU (3MB) (512KB) (512KB) (512KB) (512KB) (1MB) A1LC (2MB) (512MB) (512MB) (512MB) (512MB) (—) Barcode scanners Office equipment Image sensor Data communication modules Multi-function displays Backup cameras Handwriting recognition input devices The bus configuration with independent buses for images and hardware-based superimposition processing make it easy to create graphical applications. (telematics, emergency communications) ¢ Rich peripheral functions and software RZ/A Series Features • Large-capacity on-chip RAM: 10MB Graphics Camera Example system • Graphics display and camera input capabilities on a single chip solution Real-time correction of distorted images • Rich peripheral functions and software RZ/A1 ¢ Large-capacity on-chip RAM: 10MB Input image Output image DRAM-less solution On-chip 2D graphics “Smooth” and“beautiful” CPU accelerator for fast image graphics display by utilizing Ability to process imported Ability to connect analog Conventional MPU concept RZ/A1 concept rendering large-capacity on-chip RAM images and extract a variety of HMI functions CMOS cameras 5V/12V to the full information 5V/12V Higher costs Large-capacity on-chip RAM Regulator Regulator Regulator Regulator Regulator 3.3V 1.2V 1.5V / 0.75V 3.3V 1.2V Network Voice Wired LAN/wireless LAN NOR • Software Conventional MPU DDR3 SPI Flash Flash • Graphics RZ/A1 • Face recognition, human sensing Advantages • Image compression, Reception of necessary •No need to design a decompression Narrowing down by RZ/A1 Reduction of network information over the high-speed interface of only valuable information communication • Voice synthesis, network and voice readout •Reduced mounting area for transmission over the volume/ability to increase Higher costs etc. •Reduced PCB cost network number of cameras flexibly •No DRAM procurement issues •Reduced EMI noise 4 PCB layers for 1.2V, 3.3V With ample peripheral functions and software, a single chip can cover a wide range of fields, including display, camera input, communication, and audio functions. 6 PCB layers for 1.2V, 3.3V, 1.5V/0.75V (DDR3) 05-06 ¢ RZ/A1LU block diagram HMI Solutions RZ/A1LU Group Memory CPU Communications CPU (ARM® Cortex®-A9) SRAM Cortex®-A9 400MHz 10/100 Ether MAC • Operating frequency: 400MHz 3MB SRAML2 Cache NEON FPU CAN • Single-precision/double-precision FPU 128 KB 2ch • ARM® NEON™ Cache USB2.0 Timers HS 2ch Host/Func Full HD On-chip memory 32 KB + 32 KB (1920×1080) • RZ/A1LU: 3MB MTU2 External Bus 32-bit System 16-bit × 5ch ROM, SRAM, Main graphics and camera input functions SDRAM, PCMCIA RZ/G Series • LCD controller (VDC5): 1 channel WDT DMAC 16ch 8-bit × 1ch SPI Multi LCD output: Max. WXGA 1ch Interrupt Controller OS Timer Large-capacity on-chip memory RTOS Screen superimposition: 3 layers 32-bit × 2ch SCIF RSPI Video input: Max. XGA 5ch 3ch Simple HMI development as Compact HMI Clock Generation Real-Time CLK • CMOS camera input (CEU): 1 channel with SSCG I2C with microcontrollers development 4ch • JPEG coding engine: 1 channel JTAG Debug Graphics SSI (I2S) SPDIF Main memory interface functions RZ/A Series Secure Boot Engine* Video Display Controller 4ch 1ch • NOR flash, SDRAM 1ch SDHI MMC RZ/A1LU RZ/A1H • QSPI serial flash: 1 channel (ability to run stored programs directly) Customer Unique ID* CMOS Camera I/F 2ch 1ch WXGA and • SD host interface: 2 channels 1ch Smart Card I/F 2ch below • MMC host interface: 1 channel Audio JPEG Engine (1280×768) RZ/A1L RZ/A1M Main communication functions 1ch IrDA SCUX 4ch ASRC 1ch • USB 2.0 High Speed: 2 channels (Host/Function switchable) • 10M/100M EtherMAC: 1 channel Ethernet AVB RZ/A1LC Analog • SCIF: 5 channels 2 ADC • I C: 4 channels 12-bit × 8ch Image display functions only Image display functions Image display functions • SSI: 4 channels + 2D graphics + 3D graphics + video support • RSPI: 3 channels * =Option • Ethernet AVB: 1 channel • HMI solutions optimized to match the image resolution, functions, and OS • CAN: 2 channels Package • RZ/G series: Full HD, functions: 3D Gfx, vide, OS: Linux (RichOS) • 176-LFBGA (8mm × 8mm,0.5mm pitch) • RZ/A series: WXGA and below, functions: 2D Gfx, camera input processing, OS: RTOS • 176-LFQFP (24mm × 24mm,0.5mm pitch) • 208-LFQFP (28mm × 28mm,0.5mm pitch) ¢ RZ/A1H,and RZ/A1M block diagram ¢ RZ/A1L, RZ/A1LC block diagram RZ/A1H Group and RZ/A1M Group (Pin Compatible) RZ/A1L, RZ/A1LC Group Memory CPU Communications Memory CPU Communications CPU (ARM® Cortex®-A9) SRAM Cortex®-A9 400MHz 10/100 Ether MAC CPU (ARM® Cortex®-A9) SRAM Cortex®-A9 400MHz 10/100 Ether MAC • Operating frequency: 400MHz A1H: 10MB/A1M: 5MB • Operating frequency: 400MHz A1L: 3 MB/A1LC: 2 MB SRAM L2 Cache NEON FPU USB2.0 SRAM L2 Cache NEON FPU USB2.0 • Single-precision/double-precision FPU 128 KB HS 2ch Host/Func • Single-precision/double-precision FPU 128 KB HS 2ch Host/Func • ARM® NEON™ Cache NAND Flash • ARM® NEON™ Cache External Bus 32-bit On-chip memory 32 KB + 32 KB Timers I/F On-chip memory 32 KB + 32 KB Timers ROM, SRAM, • RZ/A1H: 10MB MTU2 External Bus 32-bit ROM, • RZ/A1L: 3MB MTU2 SDRAM, PCMCIA SRAM, SPI Multi • RZ/A1M: 5MB System 16-bit × 5ch • RZ/A1LC: 2MB System 16-bit × 5ch WDT SDRAM, PCMCIA WDT 1ch Main graphics and camera input functions Main graphics and camera input functions DMAC 16ch DMAC 16ch 8-bit × 1ch SPI Multi 8-bit × 1ch SCIF RSPI • LCD controller (VDC5): 2 channels 2ch • LCD controller (VDC5): 1 channel 5ch 3ch Interrupt Controller OS Timer Interrupt Controller OS Timer LCD output: Max. WXGA 32-bit × 2ch SCIF RSPI LCD output: Max. WXGA 32-bit × 2ch I2C IEBus* Screen superimposition: 4 layers Clock Generation PWM Timer 8ch 5ch Screen superimposition: 3 layers Clock Generation 4ch 1ch 2 Real-Time CLK with SSCG I C IEBus with SSCG 2 Video input: Max. XGA (CVBS analog input supported) 16ch Video input: Max.
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