DOCSLIB.ORG

Datasheet (1993)

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Datasheet (1993) D A'U 5-11 E E T WD90C33 High Performance VGA Controller ~ WESTERN DIGITAL Copyright © 1993 Western Digital Corporation All Rights Reserved Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corpora­ tion reserves the right to change specHications at any time without notice. Western Digital, AutoSwitch, and Paradise are registered trademarks and CacheFlow, Caviar, FIT Lab, Hyperseek, Interarchitecture, PinScan, Piranha, SAM, Tidbit, and TrueShade are trademarks of Western Digital Corporation. Other marks may be mentioned herein that belong to other Companies. Western Digital Corporation Western Digital Plaza, 8105 Irvine Center Drive, Irvine, CA 92718 For Service and Literature, call: (714) 932-4900 WD90C33 TABLE OF CONTENTS Section Title Page 1.0 INTRODUCTION ......................•.........................•..... 1 1. 1 General Description .. • . .• 1 1. 2 Features • . • . • . .. 1 1. 3 Document Scope .... • . • . .. 2 2.0 WD90C33 ARCHITECTURE ...........•.•............................... 3 3.0 WD9OC33 INTERFACES .••..............••..•..............•.•.•....... 4 3. 1 Introduction .•....................•............................ 4 3. 2 CPU (Host) And BIOS ROM Interface •.............................. 5 3. 3 Local Bus Video Subsystem Interface . • . .. 7 3.4 AT Compatible Bus Subsystem ....•............................... 8 3. 5 AT Compatible Interface (16-bits) and 8-bit BIOS ...................... 9 3.6 AT Compatible Interface (16-bits) and 16-bit BIOS ... " ............... 10 3. 7 DRAM Interface ................•.•............................ 11 3. 8 Two or Four 64K by 16 DRAM Interface ............................ 11 3. 9 Four or Eight 256K by 4 DRAM Interface ........................... 12 3. 10 Video Interface ................................................ 13 3. 11 External RAMDAC Interface ......•.............................. 13 3. 12 Clock Interface ................................................ 14 3. 13 Selecting The WD90C33 Operating Interface Configuration ............. 14 4.0 SIGNAL DESCRIPTIONS .............................................. 15 4. 1 Introduction .................................................. 15 4. 2 Pin Assignments ...............•.............................. 15 4. 3 Detailed Signal Descriptions ..................................... 18 4.4 Host Interface Pin Multiplexing ................................... 31 5.0 VGAlEGA REGISTERS ................................................ 32 5. 1 EGA Mode Entry .............................................. 32 5. 2 VGA Register Summary ....•................................... 32 5. 3 EGA Register Summary ..•...........••........................ 34 5. 4 General RegisterS .•...••......•............................... 35 5.4.1 Miscellaneous OUtput Register .......................... 35 5.4.2 Input Status Register 0 ................................ 36 5.4.3 Input Status Register 1 ................................ 36 5.4.4 Feature Control Register •.............................. 37 5. 5 Sequencer Registers •....•..................................... 37 5.5.1 Sequencer Index Register .............................. 37 5.5.2 Reset Register .....................................•. 37 ADVANCED INFORMA TION 5/27/93 WD90C33 TABLE OF CONTENTS (Continued) Section Title Page 5.5.3 Clocking Mode Register .•.•.•.....••..•....•....•.••...38 5.5.4 Map Mask Register .........••.•.......................38 5.5.5 Character Map Select Register ...•.......•...............38 5.5.6 Memory Mode Register .................................40 5.6 CRT Controller Registers .............••.......•...........•.....40 5.6.1 CRT Register Index .........•........•..•.............41 5.6.2 Horizontal Total Register •.......•.•...•..•••••.•.•.....41 5.6.3 Horizontal Display Enable End Register ...•...•••.......... 42 5.6.4 Start Horizontal Blanking Register .•..•..........•.•..... .42 5.6.5 End Horizontal Blanking ..•...•.•.........•.......•.....42 5.6.6 Start Horizontal Retrace Pulse Register ...............•....42 5.6.7 End Horizontal Retrace Register ..•......................43 5.6.8 Vertical Total Register ....•........••.......••....•.....43 5.6.9 Overflow Vertical Register •....•...............•........ 43 5.6.10 Preset Row Scan Register ..........•...................44 5.6.11 Maximum Scan Une Register ........................... .44 5.6.12 Block Cursor Start Register ....•........................45 5.6.13 Block Cursor End Register ............•.................45 5.6.14 Start Address High Register ....................... : ..... 46 5.6.15 Start Address Low Register •...••..•....................46 5.6.16 Block Cursor Location High Register .•...•.........•......46 5.6.17 Block Cursor Location Low Register ..•.............••.....46 5.6.18 Vertical Retrace Start Register ....•......................46 5.6.19 Vertical Retrace End Register ............................47 5.6.20 Vertical Display Enable End Register ..................... .47 5.6.21 Offset Register ....••............•...............•.....47 5.6.22 Underline Location Register ........••.....•.......•.....48 5.6.23 Start Vertical Blank Register ........•....................48 5.6.24 End Vertical Blank Register ........•....................48 5.6.25 CRT Mode Control Register •.......•......•............. 49 5.6.26 Un.e Compare Register ....•.....................••.....49 5. 7 Graphics Controller Registers .•............................•......50 5.7.1 Graphics Index Register ...........••...................50 5.7.2 SetlReset Register •..•..........•..............••..... 50 5.7.3 Enable SetlReset Register .• " .....••................... 51 5.7.4 Color Compare Register •.•••.•..•.••................... 51 5.7.5 Data Rotate Register ..•.•........••.....•......••.....51 5.7.6 Read Map Select Register ...•.....••.......•...•..•.... 52 II ADVANCED INFORMATION 5/27/93 WD90C33 TABLE OF CONTENTS (Continued) Section Title Page 5.7.7 Graphics Mode Register ..........•.................... 52 5.7.8 Miscellaneous Register ................................ 54 5.7.9 Color Don't Care Register .............................. 54 5.7.10 Bit Mask Register ..................................... 54 5. 8 Attribute Controller Registers ..........•......................•... 55 5.8.1 Attribute Index Register ................................ 55 5.8.2 VGA - Palette Registers ................................ 55 5.8.3 EGA - Dynamic Color Registers .•..•.................... 56 5.8.4 Attribute Mode Control Register ......................... 56 5.8.5 OVerscan Color Register ............................... 57 5.8.6 Color Plane Enable Register •......•.................... 57 5.8.7 Horizontal Pel Panning Register ......................... 58 5.8.8 Color Select Register .................................. 59 5. 9 Video RAMDAC Ports .......................................... 59 6.0 COMPATIBILITY REGISTERS .......................................... 60 6. 1 Introduction .....•............................................ 60 6. 2 HerculeS/MDA Mode Control Register, MDA Operation ................ 61 6. 3 Hercules Registers ............................................ 61 6.3.1 Enable Mode Register ................................. 61 6.3.2 Hercules Compatibility Register .......................... 62 6. 4 CGA Registers ..•............................................. 62 6.4.1 Color CGA Operation Register .......................... 62 6.4.2 CGA Color Select Register ............................. 62 6.4.3 CRT Status Register, MDA Operation ..................... 63 6.4.4 CRT Status Register, CGA Operation ..................... 64 6.4.5 AT&T/M24 Register ................................... 64 7.0 PARADISE REGISTERS •......•..................•......•............. 65 7. 1 Introduction .....••.•............•.......•.................•.. 65 7. 2 Address Offset Registers PRO(A) and PRO(B) ..•.................... 67 7.2.1 PRO(A) - Address Offset Register A .•.................... 67 7.2.2 PRO(B) - CPU Address Offset Register B .•................ 67 7.3 Paradise (PR) Register Descriptions ............................... 67 7.3.1 PR1 - Memory Size ................................... 67 7.3.2 PR2 - Video Select Register .......•.................... 72 7.3.3 PR3 - CRT Lock Control Register ......•...•............. 73 7.3.4 CRT Controller Register Locking .......•................. 74 7.3.5 PR4 - Video Control Register ..•........................ 75 ADVANCED INFORMATION 5/27/93 iii WD9OC33 TABLE OF CONTENTS (Continued) Section ntle Page 7.3.6 PR5 - General Purpose Status Bits .••..•...•.•.......•...75 7.3.7 PR10 - Unlock PR1A, PR[17:11] ...........•••...........76 7.3.8 PR 11 - Configuration Switches ...........................76 7.3.9 PR12 - Scratch Pad ...................................77 7.3.10 PR 13 - Interlace HI2 Start .•.......•••.......•..•........77 7.3.11 PR14 -Interlace HI2 End ..........•....................78 7.3.12 PR 15 - Miscellaneous Control 1 ..•.••...............•••..78 7.3.13 PR 16 - Miscellaneous Control 2 ...••.........•........... 80 7.3.14 PR 17 - Miscellaneous Control 3 .•........................80 7.3.15 PR18 - CRTC Vertical Timing OVerflow .................... 81 7.3.16 PR19 - Video Signature Analyzer Control
Load more

Recommended publications
  • RZ Family Microprocessors Brochure
    RZ FAMILY Renesas Microprocessor 2018.10 THE NEXT-GENERATION PROCESSOR TO MEET THE NEEDS OF THE SMART SOCIETY HAS ARRIVED. achine In M te n r a f a m c u e H ntr wo Co ol Net rk CONTENTS RZ/A SERIES ___________________________________________ 04 RZ/G SERIES ___________________________________________ 10 RZ/T SERIES ___________________________________________ 16 RZ/N SERIES ___________________________________________ 22 RZ SPECIFICATIONS ______________________________________ 28 PACKAGE LINEUP _______________________________________ 38 02-03 The utilization of intelligent technology is advancing in all aspects of our lives, including electric household appliances, industrial equipment, building management, power grids, and transportation. The cloud-connected “smart society” is coming ever closer to realization. Microcontrollers are now expected to provide powerful capabilities not available previously, such as high-performance and energy-efficient control combined with interoperation with IT networks, support for human-machine interfaces, and more. To meet the demands of this new age, Renesas has drawn on its unmatched expertise in microcontrollers to create the RZ family of embedded processors. The lineup of these “next-generation processors that are as easy to use as conventional microcontrollers” to meet different customer requirements. The Zenith of the Renesas micro As embedded processors to help build the next generation of advanced products, the RZ family offers features not available elsewhere and brings new value to customer applications.
    [Show full text]
  • Computer Architecture (BCA Part-I)
    Biyani's Think Tank Concept based notes Computer Architecture (BCA Part-I) Micky Haldya Revised By: Jyoti Sharma Deptt. of Information Technology Biyani Girls College, Jaipur 2 Published by : Think Tanks Biyani Group of Colleges Concept & Copyright : Biyani Shikshan Samiti Sector-3, Vidhyadhar Nagar, Jaipur-302 023 (Rajasthan) Ph : 0141-2338371, 2338591-95 Fax : 0141-2338007 E-mail : [email protected] Website :www.gurukpo.com; www.biyanicolleges.org ISBN: 978-93-81254-38-0 Edition : 2011 Price : While every effort is taken to avoid errors or omissions in this Publication, any mistake or omission that may have crept in is not intentional. It may be taken note of that neither the publisher nor the author will be responsible for any damage or loss of any kind arising to anyone in any manner on account of such errors and omissions. Leaser Type Setted by : Biyani College Printing Department For More Details: - www.gurukpo.com Computer Architecture 3 Preface am glad to present this book, especially designed to serve the needs of the I students. The book has been written keeping in mind the general weakness in understanding the fundamental concepts of the topics. The book is self-explanatory and adopts the “Teach Yourself” style. It is based on question-answer pattern. The language of book is quite easy and understandable based on scientific approach. Any further improvement in the contents of the book by making corrections, omission and inclusion is keen to be achieved based on suggestions from the readers for which the author shall be obliged. I acknowledge special thanks to Mr.
    [Show full text]
  • Integration of Linux Graphics Component in an Intelligent Device
    Integration of Linux Graphics Component in an Intelligent Device Magnus Erkenfelt M˚ansZigher Lund Institute of Technology Lund University November 9, 2007 ii Abstract In this thesis, a Linux graphics system is proposed, implemented, and dis- cussed. The most common graphics manager of Linux is called the X Server. It uses a server architecture that is not optimal when working with embedded systems, due to its memory footprint and unnecessary power consumption. The idea was to design the architecture so that the graphics system is a component of the operating system and fits into a simple C library. A direct interaction with the graphics hardware is configured and implemented on the system. The thesis introduces the concept of a graphics device called frame buffer as used to communicate with the hardware. It also describes the different modules needed to build a complete embedded Linux system. Using the pro- posed implementation, a fully operational system with a memory footprint under 5 MB can be achieved. iii iv Acknowledgements First of all, our thanks go to Mikrodidakt AB for giving us the opportunity to work on this thesis, especially to our supervisor P¨arL¨ofgrenwho always pushed us in the right direction. Also thanks to Pierre Nugues for ideas and support, and Jens Hellstr¨omfor his Linux expertise. v vi Contents 1 Introduction 1 1.1 The product . 1 1.2 Purpose of Thesis . 4 1.3 Problem Formulation . 4 1.4 Thesis Overview . 5 2 Background 7 2.1 Linux . 7 2.2 The Linux Kernel . 9 2.3 The Linux File System .
    [Show full text]
  • RZ Family Microprocessors Brochure
    RZ FAMILY MICROPROCESSORS 64-Bit & 32-Bit Arm-based high-end MPUs 2021.07 THE NEXT-GENERATION PROCESSOR TO MEET THE NEEDS OF THE SMART SOCIETY HAS ARRIVED. achine In M te n r a f a m c u e H ntr wo Co ol Net rk CONTENTS RZ/V SERIES ___________________________________________ 04 RZ/G SERIES ___________________________________________ 08 RZ/A SERIES ___________________________________________ 16 RZ/T SERIES ___________________________________________ 22 RZ/N SERIES ___________________________________________ 30 PACKAGE LINEUP _______________________________________ 35 02-03 The utilization of intelligent technology is advancing in all aspects of our lives, including electric household appliances, industrial equipment, building management, power grids, and transportation. The cloud-connected “smart society” is coming ever closer to realization. Microcontrollers are now expected to provide powerful capabilities not available previously, such as high-performance and energy-efficient control combined with interoperation with IT networks, support for human-machine interfaces, and more. To meet the demands of this new age, Renesas has drawn on its unmatched expertise in microcontrollers to create the RZ family of embedded processors. The lineup of these “next-generation processors that are as easy to use as conventional microcontrollers” to meet different customer requirements. The Zenith of the Renesas micro As embedded processors to help build the next generation of advanced products, the RZ family offers features not available elsewhere and
    [Show full text]
  • A Hybrid-Parallel Architecture for Applications in Bioinformatics
    A Hybrid-parallel Architecture for Applications in Bioinformatics M.Sc. Jan Christian Kässens Dissertation zur Erlangung des akademischen Grades Doktor der Ingenieurwissenschaften (Dr.-Ing.) der Technischen Fakultät der Christian-Albrechts-Universität zu Kiel eingereicht im Jahr 2017 Kiel Computer Science Series (KCSS) 2017/4 dated 2017-11-08 URN:NBN urn:nbn:de:gbv:8:1-zs-00000335-a3 ISSN 2193-6781 (print version) ISSN 2194-6639 (electronic version) Electronic version, updates, errata available via https://www.informatik.uni-kiel.de/kcss The author can be contacted via [email protected] Published by the Department of Computer Science, Kiel University Computer Engineering Group Please cite as: Ź Jan Christian Kässens. A Hybrid-parallel Architecture for Applications in Bioinformatics Num- ber 2017/4 in Kiel Computer Science Series. Department of Computer Science, 2017. Dissertation, Faculty of Engineering, Kiel University. @book{Kaessens17, author = {Jan Christian K\"assens}, title = {A Hybrid-parallel Architecture for Applications in Bioinformatics}, publisher = {Department of Computer Science, CAU Kiel}, year = {2017}, number = {2017/4}, doi = {10.21941/kcss/2017/4}, series = {Kiel Computer Science Series}, note = {Dissertation, Faculty of Engineering, Kiel University.} } © 2017 by Jan Christian Kässens ii About this Series The Kiel Computer Science Series (KCSS) covers dissertations, habilitation theses, lecture notes, textbooks, surveys, collections, handbooks, etc. written at the Department of Computer Science at Kiel University. It was initiated in 2011 to support authors in the dissemination of their work in electronic and printed form, without restricting their rights to their work. The series provides a unified appearance and aims at high-quality typography. The KCSS is an open access series; all series titles are electronically available free of charge at the department’s website.
    [Show full text]
  • The New Xbox 360 250GB CPU GPU Soc
    The new Xbox 360 250GB CPU GPU SoC Rune Jensen, Microsoft Bob Drehmel, IBM Hot Chips 22 8/23/2010 Xbox 360 250GB System CPU GPU SoC Module • CPU GPU Die • High Performance CPU & GPU • GDDR3 Memory Interface • Video Output • PCIe • Embedded DRAM Die Custom South Bridge • IO Connectivity • System Management Custom Video Display Controller Optical Disk Drive Flash and IO Connectivity 250GB HDD Wireless 802.11N Integration 2 CPU, GPU Process Migrations CPU 90nm, 2005 65nm, 2007 GPU 45nm, 2010 90nm, 2005 65nm, 2008 3 Motivation for Integrated CPU GPU SoC Cost and Power Savings • Front Side Bus Removal • Single Package • IBM 45nm SOI Technology 35x35mm Package, Simplified Console Design 1156 Balls • Motherboard Footprint • Power Delivery • Thermal Design • Single Heatsink + Fan Integrated CPU GPU Embedded DRAM 4 CPU GPU SoC: Features & Block Diagram CPU • Three 3.2 GHz PowerPC® cores • Shared 1MB L2 cache • Per Core: • Dual Thread Execution • 32K L1 I-cache, 32K L1 D-cache • 2-issue per cycle • Branch, Integer, Load/Store Units • VMX128 Units enhanced for games GPU • 48 parallel unified shaders • 24 billion shader instructions per second • 4 billion pixels/sec pixel fill rate • 500 million triangles/sec geometry rate • High Speed IO interface to 10 MB EDRAM Compatibility • Functional and Performance equivalent to prior Xbox 360 GPU/CPU • FSB Latency and BW match prior FSB 5 Technology Chip Statistics • 372M transistors • 45nm SOI, Ultra-low k dielectric CPU Core CPU Core • 10 levels of metal • 153 array types, ~1000 instances • 1.8 million
    [Show full text]
  • RZ/A1H Group Graphics Library "RGA" Introduction This Application Note Describes the Graphics Library RGA (Renesas Graphics Architecture) of RZ/A1H
    Application Note RZ/A1H Group Graphics Library "RGA" Introduction This application note describes the Graphics Library RGA (Renesas Graphics Architecture) of RZ/A1H. The following lists features of the RGA. Allows high-speed drawing using the hardware acceleration. The API created based on the W3C standard HTML Canvas 2D Context achieves easy learning. In addition, the RGA provides C++API that is operable as an interface that is backward compatible with HTML Canvas 2D Context. The memory area provided by the application is available as a drawing destination or for input images. Allows drawing of translucent images and translucent drawing using an alpha mask. The RGA provides a conversion tool that can access image files as global variables. (This conversion tool operates on the host PC.) Target Device RZ/A1H Group RZ/A1M Group RZ/A1L Group When applying the sample program covered in this application note to another microcomputer, modify the program according to the specifications for the target microcomputer and conduct an extensive evaluation of the modified program. Restrictions This library is not compatible with the vector graphics supported by Renesas Graphics Processor for OpenVG™ (R-GPVG2). The hardware acceleration is used only for a part of drawing (Table 1-2), (6.11.1). RZ/A1L does not use hardware acceleration. And it cannot use a part of drawing. (Table 1-3) This library cannot be used in multiple threads. Use the RGA in a single thread. R01AN2162EJ0401 Rev.4.01 Page 1 of 144 Jan.27.21 RZ/A1H Group Graphics Library RGA Contents Graphics Library "RGA" .................................................................................................................
    [Show full text]
  • Renesas Microprocessor RZ Family
    RZ FAMILY Renesas Microprocessor www.renesas.com 2017.07 01-02 THE NEXT-GENERATION PROCESSOR TO MEET THE NEEDS OF THE SMART SOCIETY HAS ARRIVED. The utilization of intelligent technology is advancing in all aspects of our lives, including electric household appliances, industrial equipment, building management, power grids, and transportation. The cloud-connected “smart society” is coming ever closer to realization. Microcontrollers are now expected to provide powerful capabilities not available previously, such as high-performance and energy-efficient control combined with interoperation with IT networks, support for human-machine interfaces, and more. To meet the demands of this new age, Renesas has drawn on its unmatched expertise in microcontrollers to create the new RZ family of embedded processors. The lineup of these “next-generation processors that are as easy to use as conventional microcontrollers” spans four product series to meet different customer requirements. The Zenith of the Renesas micro As embedded processors to help build the next generation of advanced products, the RZ family offers features not available elsewhere and brings new value achine In M te to customer applications. n r a f a m c u e H ¢ RZ Family Roadmap RZ/G1H Cortex®-A15x4 (1.4GHz) Cortex®-A7x4(780MHz) G6400, H.264 32bit×2ch DDR3-1600 RZ/G1M Cortex®-A15x2 (1.5GHz) RZ/G-next SGX544MP2, H.264 (T.B.D) 32bit×2ch DDR3L-1600 RZ/G1N Cortex®-A15x2 (1.5GHz) ntr wo SGX544MP2, H.264 Co ol Net rk 32bit×1ch DDR3L-1600 RZ/G series 3D Graphics RZ/G1E RZ/G1C Cortex®-A7x2 (1.0GHz) Cortex®-A7x2 (1.0GHz) HMI MPU SGX540, H.264 SGX531, H.264 32bit×1ch DDR3-1333 32bit×1ch DDR3-1000 RZ/A1H RZ/A-next Cortex®-A9(400MHz) RZ/A1LU Cortex®-A9(400MHz) 10MB, WXGA, 2D RZ/A1M 3MB, XGA, JPEG RZ/A series Cortex®-A9(400MHz) for HMI Apps.
    [Show full text]
  • PC Hardware Contents
    PC Hardware Contents 1 Computer hardware 1 1.1 Von Neumann architecture ...................................... 1 1.2 Sales .................................................. 1 1.3 Different systems ........................................... 2 1.3.1 Personal computer ...................................... 2 1.3.2 Mainframe computer ..................................... 3 1.3.3 Departmental computing ................................... 4 1.3.4 Supercomputer ........................................ 4 1.4 See also ................................................ 4 1.5 References ............................................... 4 1.6 External links ............................................. 4 2 Central processing unit 5 2.1 History ................................................. 5 2.1.1 Transistor and integrated circuit CPUs ............................ 6 2.1.2 Microprocessors ....................................... 7 2.2 Operation ............................................... 8 2.2.1 Fetch ............................................. 8 2.2.2 Decode ............................................ 8 2.2.3 Execute ............................................ 9 2.3 Design and implementation ...................................... 9 2.3.1 Control unit .......................................... 9 2.3.2 Arithmetic logic unit ..................................... 9 2.3.3 Integer range ......................................... 10 2.3.4 Clock rate ........................................... 10 2.3.5 Parallelism .........................................
    [Show full text]
  • Learn Computer Pre-Tech
    Learn Computer Pre-Tech Copyright 2008 by C. M. Vining Pre-Tech v1.1 Page 1 of 96 Table of Contents Introduction to Computer Pre-Tech........................4 The BIOS Chip and BIOS Recovery................42 Acronyms................................................................5 The BIOS business...........................................43 Curriculum Outline Computer Pre-Tech.................6 CMOS...............................................................43 Rules for Fighting Fires..........................................9 ROM BIOS......................................................43 How to Operate an Extinguisher......................10 POST (Power On Self Test).............................44 The Fire Triangle..............................................11 Undocumented FDISK:....................................44 Classes of Fires.................................................12 FDISK /MBR...................................................44 Computer Equipment Recycling...........................13 Boot Sequence:.................................................44 A+ Exams..............................................................14 Bus Structure.........................................................46 Exam details.....................................................14 First generation.................................................46 Identifying hardware components....................14 Second generation............................................46 Identifying Operating Systems.........................15 Third generation...............................................46
    [Show full text]
  • Intel740™ Graphics Accelerator
    Intel740™ Graphics Accelerator Software Developer’s Manual September 1998 Order Number: 290617-003 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The Intel740 graphics accelerator may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available upon request. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: http://www.intel.com or call 1-800-548-4725 Copyright © Intel Corporation, 1997-1998 *Third-party brands and names are the property of their respective owners.
    [Show full text]
  • RZ/A1H Group QE for Video Display Controller 5 Sample Program
    APPLICATION NOTE RZ/A1H Group R01AN3430EJ0100 Rev.1.00 QE for Video Display Controller 5 Sample Program Oct 17, 2016 Summary This application note describes a sample application for Video Display Controller 5 (VDC5), which interoperates with QE for Video Display Controller 5, a plugin for the e2 studio integrated development environment with support for Renesas microcontrollers. QE for Video Display Controller 5 is a tool that provides a graphical interface for display control to support the development of embedded systems incorporating display devices. Target Device RZ/AH Group Contents 1. Overview ......................................................................................................................... 3 2. Operation Confirmation Conditions .............................................................................. 4 3. Hardware ......................................................................................................................... 5 3.1 Hardware Configuration ............................................................................................................. 5 4. Software .......................................................................................................................... 6 4.1 Operation Overview .................................................................................................................... 6 4.2 Sample Software Details ............................................................................................................ 7 4.3 Memory Map ...............................................................................................................................
    [Show full text]