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Test Pattern Generator for Sequential Cells

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Test Pattern Generator for Sequential Cells UNIVERSIDADE FEDERAL DO RIO GRANDE DO SUL INSTITUTO DE INFORMÁTICA CURSO DE ENGENHARIA DE COMPUTAÇÃO PABLO RAFAEL BODMANN Test Pattern Generator for Sequential Cells Work presented in partial fulfillment of the requirements for the degree of Bachelor in Computer Engeneering Advisor: Prof. Dr. Renato Perez Ribas Porto Alegre January 2018 UNIVERSIDADE FEDERAL DO RIO GRANDE DO SUL Reitor: Prof. Rui Vicente Oppermann Vice-Reitora: Profa. Jane Fraga Tutikian Pró-Reitor de Graduação: Prof. Vladimir Pinheiro do Nascimento Diretora do Instituto de Informática: Profa. Carla Maria Dal Sasso Freitas Coordenador do Curso de Engenharia de Computação: Prof. Renato Ventura Bayan Hen- riques Bibliotecária-chefe do Instituto de Informática: Beatriz Regina Bastos Haro “Computers are like Old Testament gods; lots of rules and no mercy.” — JOSEPH CAMPBELL AGRADECIMENTOS Primeiramente, gostaria de agradecer aos meus pais pelo apoio e suporte durante todos esses anos. Gostaria de agradecer ao Prof. Renato Perez Ribas por me proporcionar um primerio contato no mundo acadêmico e por me incentivar em publicar o trabalho feito durante a bolsa de iniciação científica. Gostaria de agradecer ao Prof. André Inácio Reis e aos integrantes do grupo Logics pot todo apoio dado. ABSTRACT The validation of standard cell libraries used on digital integrated circuit design is a cru- cial task. However, the validation of sequential logic gates is quite complex due to the inherent memory effect found in these devices. In this work, it is proposed a generic test pattern generator to be applied on the validation of sequential cells. This generator is ex- pected to be independent of the cell under test behavior, to change only one input per step and to be cyclic. To solve the problem, it is necessary to model this problem as a graph and find an Euler cycle over it. In order to find a cycle it is proposed the use of a modified Depth-first search. First the generator is validated using behavioral description of several different sequential cells. Also, is is validated using several different topologies. It is also proposed and analyzed the possibility of implementation on hardware. Keywords: Sequential Cell. Testing. Digital Circuit. Standard Cell. Logic Gate. Gerador de Padrões de Teste para Células Sequenciais RESUMO A validação de bibliotecas de Standard Cell usadas no design de circuitos integrados é uma tarefa crucial. No entanto, a validação dos portas seqüenciais é bastante complexa devido ao efeito de memória presente nestes dispositivos. Neste trabalho, propõe-se um gerador de padrões de teste genérico a ser aplicado na validação de células seqüenciais. Espera-se que este gerador seja independente do comportamento da célula sob teste, para alterar apenas uma entrada por etapa e seja cíclico. Para resolver o problema, é necessário modela-lo como um grafo e encontrar um ciclo de Euler sobre ele. Para encontrar um ciclo, propõe-se o uso de uma pesquisa por profundidade modificada. Primeiro, o gerador é validado usando a descrição comportamental de várias células seqüenciais diferentes. Também é validado usando várias topologias diferentes. Também é proposto e analisado a possibilidade de implementação em hardware. Palavras-chave: Células sequenciais. Validação. Circuitos Digitais. Standard Cell. Por- tas lógicas. LIST OF ABBREVIATIONS AND ACRONYMS ASIC Application-specific integrated circuit BFS Breadth First Search BILBO Built-in Logic Block Observer BIST Built-in Self-Test CUT Cell Under Test DFS Depth First Search FFD Type D Flip-Flop FFDR Type D Flip-Flop with asynchronous Reset FFDS Type D Flip-Flop with asynchronous Set FFDRS Type D Flip-Flop with asynchronous Reset and Set FFT Type T Flip-Flop FFTR Type T Flip-Flop with asynchronous Reset FFTS Type T Flip-Flop with asynchronous Set FFTRS Type T Flip-Flop with asynchronous Reset and Set FPGA Field-programmable gate array FSM Finite State Machine IC Integrated Circuit Lat Latch LatD Type D Latch LatDR Type D Latch with asynchronous Reset LatDS Type D Latch with asynchronous Set LatDRSType D Latch with asynchronous Reset and Set NCL Null Convention Logic PWL Piecewise Linear ROM Read-only Memory XOR Exclusive-Or LIST OF FIGURES Figure 3.1 Latch ROS described at (RIBAS et al., 2011a) .............................................20 Figure 3.2 Flip-Flop ROS described at (RIBAS et al., 2011a) .......................................20 Figure 3.3 Shift-register proposed at (RIBAS et al., 2011c)...........................................22 Figure 3.4 Flip-flop testing setup proposed at (RIBAS et al., 2011c).............................23 Figure 4.1 3-Dimensional Hypercube representing a 3 bit Gray Code...........................25 Figure 4.2 Pseudocode for creating Table of adjacency lists ..........................................26 Figure 4.3 Simulation of ROM implementing a 3-input generator.................................28 Figure 4.4 Growth behavior of the Boolean network per number of inputs ...................29 Figure 4.5 Growth behavior of the FPGA per number of inputs ....................................29 Figure 5.1 Proposed improvement ..................................................................................31 Figure 5.2 Flip Flop topology .........................................................................................36 Figure 5.3 SPICE simulation of the first instance flip-flop. ...........................................37 Figure 5.4 SPICE simulation of the second instance flip-flop ........................................38 Figure 5.5 SPICE simulation of the third instance flip-flop............................................38 Figure 5.6 Flip Flop topology .........................................................................................39 Figure 5.7 SPICE simulation of the first instance flip-flop. ...........................................39 Figure 5.8 SPICE simulation of the second instance flip-flop ........................................40 Figure 5.9 SPICE simulation of the third instance flip-flop............................................40 Figure 5.10 First Latch Topology....................................................................................41 Figure 5.11 SPICE simulation of the first instance of the first topology.........................41 Figure 5.12 SPICE simulation of the second instance of the first topology ...................42 Figure 5.13 SPICE simulation of the third instance of the first topology.......................42 Figure 5.14 Second Latch Topology ...............................................................................43 Figure 5.15 SPICE simulation of the first instance of the second topology....................43 Figure 5.16 SPICE simulation of the second instance of the second topology ..............44 Figure 5.17 SPICE simulation of the third instance of the second topology ..................44 LIST OF TABLES Table 1.1 Exclusive-or truth table ...................................................................................13 Table 1.2 Type D Latch truth table..................................................................................13 Table 1.3 Malfunctioning OR gate..................................................................................14 Table 2.1 C-element steady states ...................................................................................17 Table 2.2 D-type latch with asynchronous reset steady states ........................................17 Table 2.3 D-type Flip-Flop with asynchronous reset steady states.................................17 Table 2.4 C-element expected transitions .......................................................................18 Table 2.5 D-type latch with asynchronous reset expected transitions.............................18 Table 2.6 D-type flip-flop with asynchronous reset expected transitions .......................18 Table 2.7 C-element non-expected transitions ................................................................19 Table 2.8 D-type latch with asynchronous reset non-expected transitions ....................19 Table 2.9 D-type flip-flop with asynchronous reset non-expected transitions ................19 Table 4.1 3-bit Gray code and its missing transitions. ....................................................24 Table 4.2 Table containing each node adjacency list representing the graph in Fig. 4.1 26 Table 4.3 2-input sequence..............................................................................................26 Table 4.4 3-input Sequence .............................................................................................26 Table 4.5 Sequence growth .............................................................................................27 Table 5.1 Cell with partial coverage................................................................................31 Table 5.2 States not Covered when disregarding the first iteration.................................32 Table 5.3 Cells used with input ordering and coverage ..................................................33 Table 5.4 Number of instance used .................................................................................34 Table 5.5 Coverage and number of cells used disregarding the first iteration ................35 Table 5.6 Instances Input Setup ......................................................................................37 Table 5.7 Instances Input Setup ......................................................................................41 CONTENTS 1 INTRODUCTION.......................................................................................................12
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