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California State University, Northridge Design For CALIFORNIA STATE UNIVERSITY, NORTHRIDGE DESIGN FOR TESTABILITY APPLICATION AND ANALYSIS USING CADENCE DFT TOOL COMPILER A graduate project submitted in partial fulfillment of the requirements For the degree of Master of Science in Electrical Engineering By Augusto Euler Mannucci December 2018 The graduate project of Augusto Mannucci is approved: __________________________________________ __________________ Dr. Deborah K Van Alphen Date __________________________________________ __________________ Dr. Xiyi Hang Date __________________________________________ __________________ Dr. Jack Ou, Chair Date California State University, Northridge ii Acknowledgement I would like to thank Dr. Jack Ou, Dr. Xiyi Hang, and Dr. Deborah K Van Alphen for being members of my committee, but in particular to Dr. Ou for his genuine interest and support of this project when others would nagat. I would also like to thank Henry Emil for supplying me with all the CADENCE tools I needed to complete this project and Daesung Kim, a friend and mentor, for inspiring me to choose this project and keep pushing forward. iii Table of Contents Signature Page .................................................................................................................................................ii Acknowledgement ......................................................................................................................................... iii List of Figures ...............................................................................................................................................vii ABSTRACT .................................................................................................................................................... x Chapter 1 ......................................................................................................................................................... 1 1.1 Introduction ........................................................................................................................................... 1 1.2 Objective ............................................................................................................................................... 2 1.2 Project Outline....................................................................................................................................... 3 Chapter 2 ......................................................................................................................................................... 4 2.1 Why ATPG? .......................................................................................................................................... 5 2.2 Controllability and Observability .......................................................................................................... 5 2.3 DFT Approach....................................................................................................................................... 6 2.3.1 Ad Hoc DFT ................................................................................................................................... 6 2.3.2 DFT Structure-Based ...................................................................................................................... 8 2.4 DFT in the Design Flow ...................................................................................................................... 10 2.5 DFT Scan Cell Design Techniques ..................................................................................................... 10 2.5.1 Muxed Scan Cell .......................................................................................................................... 10 2.5.2 Clocked-Scan Cell ........................................................................................................................ 12 2.5.3 Level-Sensitive Scan Design (LSSD)........................................................................................... 13 2.5.4 Scan Cell Design Advantages/Disadvantages .............................................................................. 15 2.5.5 Cadence Scan Cell Requirements ................................................................................................. 15 2.6 Scan Architectures ............................................................................................................................... 18 2.6.1 Full-Scan Design .......................................................................................................................... 18 2.6.2 Muxed Full-Scan Design .............................................................................................................. 18 2.6.3 Clocked Full-Scan Design ............................................................................................................ 21 2.7 Scan Design Rules ............................................................................................................................... 22 2.7.1 Bidirectional I/O Connection ....................................................................................................... 22 2.7.2 Tristate Buses ............................................................................................................................... 23 2.7.3 Gated Clocks ................................................................................................................................ 24 2.7.4 Derived Clocks ............................................................................................................................. 25 2.7.5 Combinational Feedback Loops ................................................................................................... 26 2.8 Design Flow – Scan ............................................................................................................................. 27 2.8.1 Scan Design Rule Checking ......................................................................................................... 28 2.8.2 Scan Synthesis .............................................................................................................................. 29 2.8.2.1 Configuration - Scan ............................................................................................................. 29 iv 2.8.2.2 Scan Replacement ................................................................................................................. 31 2.8.2.3 Reordering - Scan .................................................................................................................. 32 2.8.2.4 Scan Stitching ........................................................................................................................ 32 2.8.3 Scan Extraction ............................................................................................................................ 32 2.8.4 Scan Verification .......................................................................................................................... 33 Chapter 3 ....................................................................................................................................................... 34 3.1 UART (Universal Asynchronous Receiver Transmitter) Design ........................................................ 34 3.1.1 Design Overview .......................................................................................................................... 34 3.1.2 Baud Rate Generator Stage .......................................................................................................... 36 3.1.3 FIFO (First In First Out) Memory Module ................................................................................... 38 3.1.4 Transmitter Stage ......................................................................................................................... 43 3.1.5 Receiver Stage .............................................................................................................................. 46 3.1.6 UART Top Level Testbench ........................................................................................................ 50 Chapter 4 ....................................................................................................................................................... 53 4.1 Genus Synthesis Solution .................................................................................................................... 53 4.2 Key Features ........................................................................................................................................ 53 4.3 Key Benefits ........................................................................................................................................ 54 4.4 Preparing to Run Genus Synthesis Solution ........................................................................................ 54 4.4.1 What is Needed to Synthesize a Design ....................................................................................... 55 4.4.2 Genus Run Scripts ........................................................................................................................ 55 4.5 Invoking Genus ................................................................................................................................... 56 4.5.1 Genus Shell & Navigation ...........................................................................................................
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