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Solutions for Emerging Problems in Modular System-On-A-Chip Testing Solutions for Emerging Problems in Modular System-On-A-Chip Testing

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Solutions for Emerging Problems in Modular System-On-A-Chip Testing Solutions for Emerging Problems in Modular System-On-A-Chip Testing SOLUTIONS FOR EMERGING PROBLEMS IN MODULAR SYSTEM-ON-A-CHIP TESTING SOLUTIONS FOR EMERGING PROBLEMS IN MODULAR SYSTEM-ON-A-CHIP TESTING BY QIANG XU AUGUST 2005 A THESIS SUBMITTED TO THE DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF MCMASTER UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY °c Copyright 2005 by Qiang Xu All Rights Reserved DOCTOR OF PHILOSOPHY (2005) McMaster University (Electrical and Computer Engineering) Hamilton, Ontario TITLE: Solutions for Emerging Problems in Modular System-on-a- Chip Testing AUTHOR: Qiang Xu SUPERVISOR: Nicola Nicolici NUMBER OF PAGES: xvii, 211 ii Acknowledgments Finally the long journey has come to the end, and I am really glad that I have now the opportunity to express my gratitude for all the people who have made this thesis possible. The first person I would like to thank is my supervisor, Nicola Nicolici, whose encour- agement, enthusiasm to high-quality work and motivating discussions helped me in all the time of research for and writing of this thesis. In particular, I am deeply grateful to the support and freedom he gave me on my summer travel. It was a great pleasure to me to conduct this thesis under his supervision. Needless to say, I am grateful to all of my colleagues in the computer-aided design and test research group at McMaster University, Bai Hong Fang, Henry Ko, David Lemstra, Adam Kinsman, David Leung and Ehab Anis, those with whom I have shared both hap- piness and sadness as a graduate student. I also would like to thank Theo Gonciari and Paul Rosinger from University of Southampton. In particular, I would like to express my appreciation to Theo Gonciari for his early work and insightful comments on this thesis. Krishnendu Chakrabarty from Duke University also provided constructive suggestions on this thesis and I am deeply indebted to him. Many thanks also go to the faculty, admin- istrative and technical members in Department of Electrical and Computer Engineering at McMaster University, whose assistance was vital for the research. In particular, I would like to express my gratitude to Cheryl Gies, who is of great help whenever needed. My father Zhiqing Xu, my mother Qinghua Zhang, my wife Yujie Cui and my sister Dongdong Xu have loved, trusted and supported me all the time in my life. I cannot live through this Ph.D period without their love and patience. Words cannot express my love and gratitude to my family. iii Abstract Manufacturing test has established itself as an enabling technology for the system-on-a- chip (SOC) design paradigm. Although the IEEE Std. 1500 for embedded core test and prior work on test access mechanism design ease the SOC testing process, there are several emerging problems not treated explicitly or cost-effectively by the state-of-the-art methods. For example, the number of clock domains is stepping-up and the specific test access and isolation problems posed by multi-frequency cores have not been treated explicitly; detec- tion of timing failures, which are predominant in deep sub-micron technologies, requires support from the test access architectures for at-speed application of two successive pat- terns; glue logic defined by system integrators for product differentiation is increasing in size and its test can adversely influence either the chip area or testing time; the continuous growth in the size of SOCs leads to multiple levels of design hierarchy, which imposes an additional constraint on the design and reuse of test architectures. This dissertation shows how at-speed test application, without test hazards, can be achieved for cores with multiple clock domains, by embedding small custom logic in the wrapper. It also introduces novel test architectures for SOCs containing unwrapped logic blocks without any loss in fault coverage, by combining dedicated bus-based test access mechanism and functional interconnects for test data transfer. With some minor changes, this new test architecture can be utilized to effectively apply two-pattern test for core-based SOCs, which is essential for detecting delay faults and CMOS stuck-open faults. Test ac- cess mechanism design algorithms for the new SOC test architectures are also proposed and design trade-offs between test area and testing time are discussed. Finally, this disser- tation presents a new framework for the design space exploration of multi-level test access mechanisms, which is important for future hierarchical SOCs that reuse past-generation SOCs with existing test infrastructure as internal mega-cores. iv List of Abbreviations ATE Automatic Test Equipment ATPG Automatic Test Pattern Generation BIST Built-In Self-Test CMOS Complementary Metal Oxide Silicon CTL Core Test Language CUT Core under Test DFT Design for Testability FF Flip-Flop FIFO First-In First-Out FSM Finite State Machine HDL Hardware Description Language I/O Input/Output IC Integrated Circuit ILP Integer Linear Programming IP Intellectual Property ITRS International Roadmap for Semiconductors LFSR Linear Feedback Shift Register LSSD Level-Sensitive Scan Design MFCW Multi-Frequency Core Wrapper MISR Multiple Input Signature Analyzer NC-PI Non-Controlled Primary Inputs PC-PI Parallelly-Controlled Primary Inputs v PCB Printed Circuit Board PI Primary Input PLL Phase-Locked Loop PO Primary Output PSI Pseudo-Input PSO Pseudo-Output RAM Random Access Memory SA Signature Analyzer SC-PI Serially-Controlled Primary Inputs SECT Standard for Embedded Core Test SFCW Single-Frequency Core Wrapper SFF Scanned Flip-Flop SOC System-on-a-Chip TAM Test Access Mechanism TAT Test Application Time TDC Test Data Compression TPG Test pattern generator UDL User Defined Logic VC Virtual Core VLSI Very Large Scale Integration VTB Virtual Test Bus VTB-DIU Virtual Test Bus De-Multiplexing Interface Unit VTB-MIU Virtual Test Bus Multiplexing Interface Unit WBR Wrapper Boundary Register WBY Wrapper Bypass Register WIC Wrapper Input Cell WIR Wrapper Instruction Register WOC Wrapper Output Cell WPI Wrapper Parallel Input WPO Wrapper Parallel Output vi WSC Wrapper Serial Control WSI Wrapper Serial Input WSO Wrapper Serial Output Wrapper SC Wrapper Scan Chain vii Contents Acknowledgments iii Abstract iv List of Abbreviations v 1 Introduction 1 1.1 Core-Based SOC Design ........................... 2 1.2 Thesis Motivation ............................... 3 1.3 Thesis Organization and Contributions .................... 6 2 Background 9 2.1 VLSI Testing Concepts ............................ 9 2.1.1 Defect vs. Fault Modeling ...................... 10 2.1.2 Test Pattern Generation ........................ 13 2.1.3 Design for Testability (DFT) ..................... 14 2.1.4 Cost of Test .............................. 18 2.2 Scan Design with Multiple Clock Domains . 19 2.2.1 Avoiding Clock Skew during Scan Shift . 19 2.2.2 Avoiding Clock Skew during Scan Capture . 21 2.3 Delay Fault Testing Strategies ........................ 23 2.4 Concluding Remarks ............................. 25 viii 3 Previous Work 26 3.1 IEEE Std. 1500 ................................ 27 3.1.1 Scalable Core Test Wrapper ..................... 27 3.1.2 Wrapper Instruction Set ....................... 30 3.1.3 Core Test Language (CTL) ...................... 31 3.2 SOC Test Access ............................... 32 3.2.1 Direct Access ............................. 32 3.2.2 Isolation Ring Access ........................ 33 3.2.3 Functional Access .......................... 34 3.2.4 Dedicated Bus-Based Access ..................... 36 3.2.5 Cost Analysis for Different SOC Test Access Strategies . 38 3.3 Test Scheduling and Test Architecture Optimization . 40 3.3.1 Test Scheduling ............................ 42 3.3.2 Wrapper Design and Optimization . 44 3.3.3 Integrated Wrapper/TAM Co-Optimization and Test Scheduling . 45 3.4 SOC Test Resource Partitioning ....................... 52 3.4.1 Test Stimuli Compression ...................... 53 3.4.2 Test Response Compaction ...................... 55 3.5 Concluding Remarks ............................. 56 4 Wrapper Design for Multi-Frequency IP Cores 57 4.1 Preliminaries and Summary of Contributions . 57 4.2 Multi-Frequency Core Wrapper Design ................... 61 4.3 Multi-Frequency Core Wrapper Optimization . 68 4.3.1 Wrapper Optimization Using an ILP Model . 69 4.3.2 Wrapper Optimization Using Fast Heuristics . 71 4.4 Experimental Results ............................. 75 4.5 Concluding Remarks ............................. 78 5 Two-Pattern Test of Core-Based SOCs 79 5.1 Preliminaries and Summary of Contributions . 80 5.2 Proposed Architecture for Two-Pattern Test . 85 ix 5.2.1 The Two-Pattern Testing Process ................... 85 5.2.2 1500-Compatible Core Wrapper Design for Two-Pattern Test . 87 5.3 Proposed Architecture Optimization ..................... 88 5.3.1 Test Conflicts ............................. 88 5.3.2 TAM Division into Producer and CUT Groups . 89 5.3.3 Two-Pattern Test Scheduling ..................... 90 5.4 Experimental Results ............................. 95 5.4.1 SOC Specifications .......................... 96 5.4.2 Experiment 1: DFT Area Savings . 96 5.4.3 Experiment 2: Optimal Producer-CUT TAM Configuration . 97 5.4.4 Experiment 3: Test Schedule and Test Application Time . 98 5.5 Concluding Remarks .............................101 6 Modular SOC Testing with Reduced Wrapper Count 104 6.1 Preliminaries and Summary of Contributions . 105 6.1.1 Light Wrapper ............................106 6.1.2 Summary of Contributions . 109 6.2
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