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US 20060180895Al (19) United States (12) Patent Application Publication (10) Pub. No.: US 2006/0180895 A1 Chen et al. (43) Pub. Date: Aug. 17, 2006

(54) DEVICE WITH VERTICALLY (21) Appl. No.: 11/055,933 ARRANGED CAPACITOR REGIONS OF VARIOUS KINDS (22) Filed: Feb. 11, 2005 (75) Inventors: Yueh-You Chen, Hsin-Chu City (TW); Publication Classi?cation Chung-Long Chang, Dou-Liu city (TW); Chih-Ping Chao, Chu-Dong (51) Int. Cl. Town (TW); Chun-Hong Chen, Jhubei H01L 29/93 (2006.01) City (TW) (52) U.S. Cl...... 257/595; 257/E2l Correspondence Address: (57) ABSTRACT DUANE MORRIS, LLP IP DEPARTMENT A capacitor device selectively combines MOM, MIM and 30 SOUTH 17TH STREET varactor regions in the same layout area of an IC. TWo or PHILADELPHIA, PA 19103-4196 (US) more types of capacitor regions arranged vertically on a substrate to form the capacitor device. This increase the (73) Assignee: Taiwan Semiconductor Manufacturing per unit of the capacitor device, Without occu Company, Ltd. pying an extra layout area. 100“ 168\A166\1::: 1:1 162 { 164C 1:: . 160

158, F I

/_\~ ’/'_‘\ 130 Bi- - + - +--E6_,154 /\_ A/A\ 128 i. - + - +--?, 152

122 ' 134 . ,/—\ 142 126 \_/—'—~ . + .. +_-\_, 150

/\'_ ‘/_\ 4 124 i. . + - +--—2, 148 120% 118/1- ] 116f 108

112 112 104 10s \ p — /_/ 106

_ m _ 114 l_/114 110

Patent Application Publication Aug. 17, 2006 Sheet 2 0f 2 US 2006/0180895 A1

200“

- + - +

+ - + -

- + - +

+ - + -

FIG. 2

300%

316% + ' + 314“ 312% + +

310v“ ' 308 “w - + - + 306\___ 304“ + +

FIG. 3 US 2006/0180895 A1 Aug. 17,2006

CAPACITOR DEVICE WITH VERTICALLY SUMMARY ARRANGED CAPACITOR REGIONS OF VARIOUS KINDS [0007] In vieW of the foregoing, the folloWing provides a capacitor device selectively combining MOM, MIM and BACKGROUND varactor regions in the same layout area of an IC. In one [0001] The present invention relates generally to inte embodiment of the present invention, tWo or more types of grated circuit (IC) designs, and more particularly to a capacitor regions are arranged vertically on a substrate to capacitor device With a metal--metal (MIM) capaci form a capacitor device. This increase the capacitance per tor region, metal--metal (MOM) capacitor region, or unit of the capacitor device, Without occupying an extra varactor region vertically arranged on the same layout area. layout area. [0002] The construction of passive electronic circuit ele [0008] The construction and method of operation of the ments, such as , on an IC can be tedious, time invention, hoWever, together With additional objects and consuming, and costly. It is therefore important to assemble advantages thereof Will be best understood from the folloW such IC elements using the processes, materials, and designs ing description of speci?c embodiments When read in con that are relevant to the technology and that are already in nection With the accompanying draWings. production. BRIEF DESCRIPTION OF THE DRAWINGS [0003] Capacitors occur naturally, Whether intended, or not. Such capacitors can be useful. Active IC elements, such [0009] FIG. 1 illustrates a capacitor device, in accordance as bipolar and metal-oxide-semiconductor (MOS) transis With one embodiment of the present invention. tors, and some contain electrical junctions With capacitance. A depletion region of an electrical junction is, [0010] FIG. 2 illustrates an alternative MOM capacitor by nature, a small parallel plate capacitor. That capacitor can region of the capacitor device, in accordance With the embodiment of the invention. be used as a ?xed-value capacitor, or it can be used as a , since its value changes as the voltage [0011] FIG. 3 illustrates another alternative MOM capaci applied to the junction changes. Passive IC elements, such as tor region of the capacitor device, in accordance With the polycrystalline silicon (polysilicon) and metal lines, have embodiment of the invention. inherent capacitance, With respect to each other and to any other conductors. DESCRIPTION [0004] The effort of a designer can be to use available [0012] The folloWing Will provide a detailed description of characteristics of IC elements. The dif?culty With such effort a capacitor device selectively combining MIM, MOM and is that the resulting structures exhibit capacitance values varactor regions in the same layout area of an IC. It is only on the order of femtofarads/micron squared. Achieving understood that different capacitor regions can be used in functional capacitance values in an IC element requires advantageous combinations in mixed signal and/or radio structures that typically are much larger than the active (RF) circuits. elements, especially When used in mixed signal and/or (RF) circuits. This imbalance is uneconomical, [0013] Several capacitor structures are in use in ICs. Each since it forces the circuit designer to dedicated space for one has a characteristic capacitance value per square micron capacitors and produce IC chips that are too large. The (u). A typical MIM capacitor offers about 0.5 femtofarad/p.2 designer can choose among several structural types of (fF/u2). Atypical MOM capacitor offers about 0.15 fF/p.2 per capacitors, but no one type offers a convenient balance of layer. A variable capacitor, or a varactor, offers about 1 to 6 performance and space economy. fF/u2. Different capacitor structures can be used in combi nations in mixed signal and/or RF circuits. This invention [0005] In one example, the voltage-variable capacitance of provides a capacitor device that includes tWo or more an electrical junction can be applied in the construction of a different types of capacitors, such as MIM capacitors, MOM variable capacitor, or a varactor. In another example, the capacitors and varactors, in a vertical arrangement in the dual-damascene techniques typically used With copper mul same layout area. This increases the capacitance value per tilevel interconnection metalliZation on ICs can be used to unit Without occupying layout areas more than a conven construct stacks of copper-?lled vias and trenches. TWo or tional MIM capacitor, MOM capacitor or varactor Would do. more such copper-?lled vias or trenches, separated by oxide , form a capacitor, Which is called a MOM capaci [0014] FIG. 1 illustrates a capacitor device 100 in accor tor. This MOM capacitor requires a complex design, but the dance With one embodiment of the present invention. As Will form is ef?cient and the process steps required are usually be evident, the capacitor device 100 comprises three capaci already involved in the a standard tor regions, all of Which are understood to be constructed in fabrication process. In yet another example, simple horiZon the same layout area of an IC. It is noteworthy that While, in tal parallel plates of metal, separated by dielectrics, form a this embodiment, the capacitor device 100 includes three capacitor, Which is called a MIM capacitor. The horizontal capacitor regions, only tWo are able to increase the capaci form of this MIM capacitor occupies relatively more lateral tance per unit, according to the present invention. For layout space, but is simple to construct. example, a combination of the capacitor regions can be varactor and MOM capacitor regions, MOM and MIM [0006] Since a single type of capacitor does not alWays capacitor regions, or MIM and varactor capacitor regions. provide suf?cient capacitance per unit, it is desirable in the art of designs that additional devices are [0015] A semiconductor P-type substrate 102 is a host to provided to combine various types of capacitors in the same a varactor region 104 having at least one varactor. An active layout area for increasing the capacitance per unit of the area is enclosed by isolation structures 106, such as a same. shalloW trench isolation (STI) or local oxidation of silicon. US 2006/0180895 A1 Aug. 17,2006

A MOS gate 108 is deposited on a MOS gate layer [0018] Above the MOM capacitor region 122 is a dielec 110. The gate 108 may be made of poly-silicon or metal, tric layer 156, Which may be made from the same candidate including, but not limited to, W, Al, AlCu, Cu, Ti, TiSi2, Co, materials as the dielectric layer 120 or 116. Above the CoSi2, Ni, NiSi, TiN, TiW, or TaN. The gate dielectric layer dielectric layer 156 is a metal shielding layer 158 that acts 110 may be made of a material including, but not limited to, as a shield to separate any capacitor structure thereabove Si3N4, nitrided oxide, Hf oxide, A12O5, Ta2O5, metal oxide. from the capacitance of the MOM capacitor region 122 or TWo N+ regions 112, as a diffused source and drain, are any other semiconductor structures therebeloW. The metal disposed in the substrate 102, underneath the MOS gate 108 shielding layer 158 may be made of a material including, but and betWeen the isolation structures 106. Electrical junctions not limited to, Cu, AlCu, Ag, and Au. Above the metal 114, betWeen the N+ regions 112 and the P-type substrate shielding layer 158 is a dielectric layer 160, Which may be 102, have capacitance relative to the MOS gate 108. As the made from the same candidate materials as the dielectric bias on the electrical junctions 114 and the bias on the MOS layer 120, 116 or 156. Above the metal shielding layer 158 gate 108 change, the Width and area of the depletion region and the dielectric layer 160 is a MIM capacitor region 162. under the MOS gate 108 also changes, thereby further The MIM capacitor region 162 having one or more MIM changing the capacitance of the varactor region 104. It is capacitors is constructed of simple horizontal ?at patterned note Worthy that the above-described MOS capacitor is only metal plates 164 and 166 separated by a dielectric layer 168. one exemplary varactor for the varactor region 104. Other The metal plates 164 and 166 may be made of a material types of varactors, such as a junction capacitor or bipolar including, but not limited to, W, Al, AlCu, Cu, Ti, TiSi2, Co, junction capacitor, can also be as a varactor for the CoSi2, Ni, NiSi, TiN, TiW, or TaN. The combination of the varactor region 104. metal plate 166, the metal plate 164, and the dielectric layer [0016] Above the varactor region 104 is a dielectric layer 168 in betWeen forms a parallel plate capacitor, to be further 116, Which may be made of a material including, but not seen as one MIM capacitor. limited to, oxide, silicon oxynitride, silicon nitride, [0019] The combinations of capacitor types listed above oxide, alumina, hafnium oxide, plasma enhanced chemical offer greater capacitance per unit surface area, and therefore, vapor deposition (PECVD) oxide, tetraethylorthosilicate loWer cost, than is achievable With only one type of capaci (TEOS). Above the dielectric layer 116 is a metal shielding tors. Combinations of capacitor types also alloW greater layer 118 that acts as a shield to separate any capacitor design ?exibility for the designer. It is noteWorthy that the structure thereabove from being in?uenced by the capaci vertically sacked capacitor regions can be arranged in an tance of the varactor region 104 or any other semiconductor order other than that described above. For example, the structure therebeloW. The metal shielding layer 118 may be MOM region 122 and the MIM region 162 may be sWitched, made of a material including, but not limited to, poly, Without departing the spirit of the invention. polyside, AlCu, Al, Cu, Ag, and Au. Above the metal shielding layer 118 is a dielectric layer 120, Which can be [0020] FIG. 2 illustrates an alternative MOM capacitor made from the same candidate materials as those of the region 200, in accordance With one embodiment of the dielectric layer 116. invention. The alternative MOM capacitor 200 is similar to the MOM capacitor region 122, as shoWn in FIG. 1, except [0017] A MOM capacitor region 122 is disposed above the that the alternative MOM capacitor 200 is charged in a metal shielding layer 118 and the dielectric layer 120. The different pattern. Speci?cally, in the alternative MOM rectangles shoWn in FIG. 1 are actually cross sections of capacitor region 200, the positive and negative charges on dielectric-separated horizontal bars 124, 126, 128, and 130 individual bars are assigned in a checkerboard pattern. In that run perpendicular to the page and parallel to the other Words, the charge of all oxide-separated horizontal substrate 102. The same is true for dielectric-separated bars immediately adjacent to each oxide-separated horizon horizontal bars 132, 134, 136, 138, 140, 142, 144, 146, 148, tal bar in question is opposite to the charge of that oxide 150, 152 and 154. Each of these bars is formed as metal that separated horizontal bar in question. The total capacitance ?lls a trench in a typical multi-level metal structure. These achievable in the alternative MOM capacitor region 200, horizontal bars may be made of a material including, but not When compared With the MOM capacitor region 122, is limited to, W, Al, AlCu, Cu, Ti, TiSi2, Co, CoSi2, Ni, NiSi, slightly different. TiN, TiW, or TaN. It is understood that While the MOM capacitor region is shoWn to include 16 of such horizontal [0021] FIG. 3 illustrates another alternative MOM capaci bars arranged in a 4x4 fashion, other con?gurations With tor region 300, in accordance With one embodiment of the other arrangements are contemplated. These isolated bars invention. The MOM capacitor region 300 is similar to the are close enough together in an array to offer useable MOM capacitor region 122, as shoWn in FIG. 1, except that capacitance. As an example, a collection of them can offer each column of dielectric-separated horizontal bars are a signi?cant capacitance value. One advantage by arranging connected vertically by vias, ?lled With a conductive mate the bars to form a vertical column of horizontal bars is to rial. For instance, a horizontal bar 304 is connected by a via achieve capacitance While occupying less lateral space. The 306 to a horizontal bar 308. The horizontal bar 308 is also horizontal bars in each vertical column have either a positive connected by a via 310 to a horizontal bar 312. The or a negative charge. Therefore, each column of horizontal horizontal bar 312 is also connected by a via 314 to a bars forms a porous or slatted vertical capacitor plate. The horizontal bar 316. It is understood that the charging patterns dielectric that intervenes betWeen that slatted plate and the of the horizontal bars in the MOM capacitor region 300 are next one acts as a capacitor dielectric. For instance, the similar to the charging patterns of the MOM capacitor region horizontal bars 124, 126, 128 and 130 form a negatively 122, because horizontal bars connected vertically by one or charged slatted ?rst vertical capacitor plate, While the hori more vias must have the same charging pattern. In addition, zontal bars 132, 134, 136 and 138 form a positively charged it is understood that since vias are typically deployed in a slatted second vertical capacitor plate. multiple fashion, each vertical capacitor plate is noW denser, US 2006/0180895 A1 Aug. 17,2006

thereby increasing capacitance. In addition, it is understood 11. The capacitor device of claim 7 Wherein the MOM that the vias add to the surface area of each vertical capacitor region provides a unit capacitance per metal layer of at least plate, thereby further increasing capacitance. 0.15 fF/um2 per layer [0022] The above illustration provides many different 12. A capacitor device having tWo or more types of embodiments or embodiments for implementing different capacitor regions arranged vertically on a substrate, Wherein features of the invention. Speci?c embodiments of compo the capacitor regions are selected from a group consist of a nents and processes are described to help clarify the inven varactor region, a metal-oXide-metal (MOM) capacitor tion. These are, of course, merely embodiments and are not region, and a metal-isolator-metal (MIM) capacitor region. intended to limit the invention from that described in the 13. The capacitor device of claim 12 Wherein the varactor region includes a MOS capacitor, junction capacitor or claims. bipolar junction transistor capacitor. [0023] Although the invention is illustrated and described 14. The capacitor device of claim 12 further comprising a herein as embodied in one or more speci?c examples, it is metal shielding layer for shielding one region from another. nevertheless not intended to be limited to the details shoWn, 15. The capacitor device of claim 12 Wherein the MlM since various modi?cations and structural changes may be capacitor region provides a unit capacitance of at least 0.5 made therein Without departing from the spirit of the inven fF/um2. tion and Within the scope and range of equivalents of the 16. The capacitor device of claim 12 Wherein the varactor claims. Accordingly, it is appropriate that the appended region provides a unit capacitance of at least 1 fF/um2. claims be construed broadly and in a manner consistent With 17. The capacitor device of claim 12 Wherein the MOM the scope of the invention, as set forth in the folloWing region has one or more conductive bars deployed in one or claims. more metal layers. What is claimed is: 18. The capacitor device of claim 17 Wherein the con 1. A capacitor device comprising: ductive bars of the same type of charge are arranged in the same column. a varactor region formed on a substrate; 19. The capacitor device of claim 18 Wherein the con a metal-oXide-metal (MOM) capacitor region formed ductive bars in the same column are connected together With over the varactor region; vias. a metal-isolator-metal (MIM) capacitor region formed on 20. The capacitor device of claim 17 Wherein the con top of the MOM capacitor region, ductive bars of different types of charge are arranged in a checkerboard manner. Wherein the varactor, MOM, and MlM regions are verti 21. The capacitor device of claim 17 Wherein the MOM cally arranged to provide an enhanced unit capacitance. region provides a unit capacitance per metal layer of at least 2. The capacitor device of claim 1 Wherein the varactor 0.15 fF/um2.per layer region includes a MOS capacitor, junction capacitor or 22. A capacitor device having tWo or more types of bipolar junction transistor capacitor. capacitor regions arranged vertically on a substrate for using 3. The capacitor device of claim 1 further comprising a With radio frequency circuits, the device comprising: ?rst metal shielding layer for shielding the varactor region from the MOM capacitor region. a varactor region formed on a substrate providing at least 4. The capacitor device of claim 1 further comprising a a unit capacitance of at least 1 fF/um2; and second metal shielding layer for shielding the MOM capaci tor region from the MlM capacitor region. either a metal-oXide-metal (MOM) capacitor region pro viding a unit capacitance per metal layer of at least 0.15 5. The capacitor device of claim 1 Wherein the MlM fF/um2 per layer a metal-isolator-metal (MIM) capaci capacitor region provides a unit capacitance of at least 0.5 fF/um2. tor region providing at least a unit capacitance of at least 0.5 fF/um2, formed over the varactor region. 6. The capacitor device of claim 1 Wherein the varactor region provides a unit capacitance of at least 1 fF/um2. 23. The capacitor device of claim 22 Wherein the varactor 7. The capacitor device of claim 1 Wherein the MOM region includes a MOS capacitor, junction capacitor or region has one or more conductive bars deployed in one or bipolar junction transistor capacitor. more metal layers. 24. The capacitor device of claim 22 further comprising a 8. The capacitor device of claim 7 Wherein the conductive metal shielding layer for shielding one region from another. bars of the same type of charge are arranged in the same 25. The capacitor device of claim 22 Wherein the MOM column. region has more than one metal layers. 9. The capacitor device of claim 8 Wherein the conductive 26. The capacitor device of claim 22 Wherein both the bars in the same column are connected together With vias. MOM and MlM capacitor regions are arranged one after 10. The capacitor device of claim 7 Wherein the conduc another vertically over the varactor region. tive bars of different types of charge are arranged in a checkerboard manner.